Index: c/src/lib/libcpu/sh/sh7045/include/Makefile.in
===================================================================
--- c/src/lib/libcpu/sh/sh7045/include/Makefile.in	(revision 4a238002e71ec018723229f8669363a5ffb7302e)
+++ c/src/lib/libcpu/sh/sh7045/include/Makefile.in	(revision 4a238002e71ec018723229f8669363a5ffb7302e)
@@ -0,0 +1,46 @@
+#
+# $Id$
+#
+
+@SET_MAKE@
+srcdir = @srcdir@
+top_srcdir = @top_srcdir@
+top_builddir = ../../..
+subdir = sh/sh7045/include
+
+RTEMS_ROOT = @RTEMS_ROOT@
+PROJECT_ROOT = @PROJECT_ROOT@
+
+VPATH = @srcdir@
+
+H_FILES = $(srcdir)/io_types.h $(srcdir)/null.h $(srcdir)/sci.h \
+    $(srcdir)/sh7_pfc.h $(srcdir)/sh7_sci.h
+
+SRCS = $(H_FILES)
+
+include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
+include $(RTEMS_ROOT)/make/leaf.cfg
+
+INSTALL_CHANGE = @INSTALL_CHANGE@
+mkinstalldirs = $(SHELL) $(top_srcdir)/@RTEMS_TOPdir@/mkinstalldirs
+
+INSTALLDIRS = $(PROJECT_INCLUDE)/sh
+
+$(INSTALLDIRS):
+	@$(mkinstalldirs) $(INSTALLDIRS)
+
+CLEAN_ADDITIONS +=
+CLOBBER_ADDITIONS +=
+
+all: install
+
+# NOTE: Unlike other CPUS, we install into a subdirectory to avoid 
+#       file name conflicts
+
+install: 
+	$(mkinstalldirs) $(PROJECT_INCLUDE)/sh
+	@$(INSTALL_CHANGE) -m 644 $(H_FILES) $(PROJECT_INCLUDE)/sh
+
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+	cd $(top_builddir) \
+	 && CONFIG_FILES=$(subdir)/$@ CONFIG_HEADERS= $(SHELL) ./config.status
Index: c/src/lib/libcpu/sh/sh7045/include/io_types.h
===================================================================
--- c/src/lib/libcpu/sh/sh7045/include/io_types.h	(revision 4a238002e71ec018723229f8669363a5ffb7302e)
+++ c/src/lib/libcpu/sh/sh7045/include/io_types.h	(revision 4a238002e71ec018723229f8669363a5ffb7302e)
@@ -0,0 +1,87 @@
+/************************************************************************
+ *
+ *  Data types and constants for Hitachi SH704X on-chip peripherals
+ *
+ *  Author: John M.Mills (jmills@tga.com)
+ *
+ *  COPYRIGHT (c) 1999, TGA Technologies, Norcross, GA, USA
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *  This file may be distributed as part of the RTEMS software item.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *	John M. Mills (jmills@tga.com)
+ *	TGA Technologies, Inc.
+ *  100 Pinnacle Way, Suite 140
+ *	Norcross, GA 30071 U.S.A.
+ *
+ *	This modified file may be copied and distributed in accordance
+ *	the above-referenced license. It is provided for critique and
+ *	developmental purposes without any warranty nor representation
+ *	by the authors or by TGA Technologies.
+ *
+ *  $Id$
+ *
+ *
+ ************************************************************************/
+ 
+#ifndef _sh_io_types_h
+#define _sh_io_types_h
+ 
+#include <rtems/score/iosh7045.h>
+#include <termios.h>
+
+typedef enum {SCI0, SCI1} portNo;
+typedef enum {eight, seven} dataBits;
+typedef enum {one, two} stopBits;
+typedef enum {even, odd} parity;
+
+typedef struct {
+	portNo		line;
+	int				speed_ix;
+	dataBits	dBits;
+	int				parEn;	
+	parity		par;
+	int				mulPro;
+	stopBits	sBits;
+} sci_setup_t;
+
+typedef union{
+	unsigned char Reg;         /* By Register */
+	struct {                   /* By  Field */
+		 unsigned char Sync  :1; /* Async/Sync */
+		 unsigned char DBts  :1; /* Char.Length */
+		 unsigned char ParEn :1; /* Parity En.*/
+		 unsigned char Odd   :1; /* Even/Odd */
+		 unsigned char SBts  :1; /* No.Stop Bits */
+		 unsigned char MulP  :1; /* Multi-Proc. */
+		 unsigned char Dvsr  :2; /* Clock Sel. */
+	} Fld;
+} sci_smr_t;
+
+typedef union {
+	unsigned char Reg;          /*  By Register */
+	struct {                    /*  By Field */
+		 unsigned char TIE :1;    /*  Tx.Int.En. */
+		 unsigned char RIE :1;    /*  Rx.Int.En. */
+		 unsigned char TE  :1;    /*  Tx.En. */
+		 unsigned char RE  :1;    /*  Rx.En. */
+		 unsigned char MPIE:1;    /*  Mult.Pro.Int.En. */
+		 unsigned char TEIE:1;    /*  Tx.End Int.En. */
+		 unsigned char CkSrc :2;   /*  Clock Src. */
+	} Fld;
+} sci_scr_t;
+
+typedef struct {
+  unsigned char n ;
+  unsigned char N ;
+} sci_bitrate_t;
+
+#endif /* _sh_io_types_h */
+
Index: c/src/lib/libcpu/sh/sh7045/include/null.h
===================================================================
--- c/src/lib/libcpu/sh/sh7045/include/null.h	(revision 4a238002e71ec018723229f8669363a5ffb7302e)
+++ c/src/lib/libcpu/sh/sh7045/include/null.h	(revision 4a238002e71ec018723229f8669363a5ffb7302e)
@@ -0,0 +1,72 @@
+/*  null.h
+ *
+ *  Null device driver, derived from rtems' stub driver.
+ *
+ *  Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1989-1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#ifndef __NULL_DRIVER_h
+#define __NULL_DRIVER_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define DEVNULL_DRIVER_TABLE_ENTRY \
+  { null_initialize, null_open, null_close, null_read, \
+    null_write, null_control }
+
+#define NULL_SUCCESSFUL RTEMS_SUCCESSFUL
+
+rtems_device_driver null_initialize(
+  rtems_device_major_number,
+  rtems_device_minor_number,
+  void *
+);
+
+rtems_device_driver null_open(
+  rtems_device_major_number,
+  rtems_device_minor_number,
+  void *
+);
+
+rtems_device_driver null_close(
+  rtems_device_major_number,
+  rtems_device_minor_number,
+  void *
+);
+
+rtems_device_driver null_read(
+  rtems_device_major_number,
+  rtems_device_minor_number,
+  void *
+);
+
+rtems_device_driver null_write(
+  rtems_device_major_number,
+  rtems_device_minor_number,
+  void *
+);
+
+rtems_device_driver null_control(
+  rtems_device_major_number,
+  rtems_device_minor_number,
+  void *
+);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/* end of include file */
Index: c/src/lib/libcpu/sh/sh7045/include/sci.h
===================================================================
--- c/src/lib/libcpu/sh/sh7045/include/sci.h	(revision 4a238002e71ec018723229f8669363a5ffb7302e)
+++ c/src/lib/libcpu/sh/sh7045/include/sci.h	(revision 4a238002e71ec018723229f8669363a5ffb7302e)
@@ -0,0 +1,85 @@
+/*
+ *  Driver for the sh2 704x on-chip serial devices (sci)
+ *
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * 
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#ifndef _sh_sci_h
+#define _sh_sci_h
+
+#ifdef __cplusplus
+extern"C" {
+#endif
+
+/*
+ * Devices are set to 9600 bps, 8 databits, 1 stopbit, no
+ * parity and asynchronous mode by default. 
+ *
+ * NOTE:
+ *       The onboard serial devices of the SH do not support hardware 
+ *       handshake.
+ */ 
+
+#define DEVSCI_DRIVER_TABLE_ENTRY \
+  { sh_sci_initialize, sh_sci_open, sh_sci_close, sh_sci_read, \
+      sh_sci_write, sh_sci_control }
+
+extern rtems_device_driver sh_sci_initialize(
+  rtems_device_major_number,
+  rtems_device_minor_number,
+  void *
+);
+
+extern rtems_device_driver sh_sci_open(
+  rtems_device_major_number,
+  rtems_device_minor_number,
+  void *
+);
+
+extern rtems_device_driver sh_sci_close(
+  rtems_device_major_number,
+  rtems_device_minor_number,
+  void *
+);
+
+extern rtems_device_driver sh_sci_read(
+  rtems_device_major_number,
+  rtems_device_minor_number,
+  void *
+);
+
+extern rtems_device_driver sh_sci_write(
+  rtems_device_major_number,
+  rtems_device_minor_number,
+  void *
+);
+
+extern rtems_device_driver sh_sci_control(
+  rtems_device_major_number,
+  rtems_device_minor_number,
+  void *
+);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
Index: c/src/lib/libcpu/sh/sh7045/include/sh7_pfc.h
===================================================================
--- c/src/lib/libcpu/sh/sh7045/include/sh7_pfc.h	(revision 4a238002e71ec018723229f8669363a5ffb7302e)
+++ c/src/lib/libcpu/sh/sh7045/include/sh7_pfc.h	(revision 4a238002e71ec018723229f8669363a5ffb7302e)
@@ -0,0 +1,118 @@
+/*
+ * Bit values for the pin function controller of the Hitachi SH704x
+ *
+ * From Hitachi tutorials
+ *
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#ifndef _sh7_pfc_h
+#define _sh7_pfc_h
+
+#include <rtems/score/iosh7045.h>
+
+/*
+ * Port B IO Register (PBIOR)
+ */
+#define PBIOR           PFC_PBIOR
+#define PB15IOR         0x8000
+#define PB14IOR         0x4000
+#define PB13IOR         0x2000
+#define PB12IOR         0x1000
+#define PB11IOR         0x0800
+#define PB10IOR         0x0400
+#define PB9IOR          0x0200
+#define PB8IOR          0x0100
+#define PB7IOR          0x0080
+#define PB6IOR          0x0040
+#define PB5IOR          0x0020
+#define PB4IOR          0x0010
+#define PB3IOR          0x0008
+#define PB2IOR          0x0004
+#define PB1IOR          0x0002
+#define PB0IOR          0x0001
+
+/*
+ * Port B Control Register (PBCR1)
+ */
+#define PBCR1           PFC_PBCR1
+#define PB15MD1         0x8000
+#define PB15MD0         0x4000
+#define PB14MD1         0x2000
+#define PB14MD0         0x1000
+#define PB13MD1         0x0800
+#define PB13MD0         0x0400
+#define PB12MD1         0x0200
+#define PB12MD0         0x0100
+#define PB11MD1         0x0080
+#define PB11MD0         0x0040
+#define PB10MD1         0x0020
+#define PB10MD0         0x0010
+#define PB9MD1          0x0008
+#define PB9MD0          0x0004
+#define PB8MD1          0x0002
+#define PB8MD0          0x0001
+
+#define PB15MD          PB15MD1|PB14MD0
+#define PB14MD          PB14MD1|PB14MD0
+#define PB13MD          PB13MD1|PB13MD0
+#define PB12MD          PB12MD1|PB12MD0
+#define PB11MD          PB11MD1|PB11MD0
+#define PB10MD          PB10MD1|PB10MD0
+#define PB9MD           PB9MD1|PB9MD0
+#define PB8MD           PB8MD1|PB8MD0
+
+#define PB_TXD1         PB11MD1
+#define PB_RXD1         PB10MD1
+#define PB_TXD0         PB9MD1
+#define PB_RXD0         PB8MD1
+
+/*
+ * Port B Control Register (PBCR2)
+ */
+#define PBCR2   PFC_PBCR2
+#define PB7MD1  0x8000
+#define PB7MD0  0x4000
+#define PB6MD1  0x2000
+#define PB6MD0  0x1000
+#define PB5MD1  0x0800
+#define PB5MD0  0x0400
+#define PB4MD1  0x0200
+#define PB4MD0  0x0100
+#define PB3MD1  0x0080
+#define PB3MD0  0x0040
+#define PB2MD1  0x0020
+#define PB2MD0  0x0010
+#define PB1MD1  0x0008
+#define PB1MD0  0x0004
+#define PB0MD1  0x0002
+#define PB0MD0  0x0001
+	
+#define PB7MD   PB7MD1|PB7MD0
+#define PB6MD   PB6MD1|PB6MD0
+#define PB5MD   PB5MD1|PB5MD0
+#define PB4MD   PB4MD1|PB4MD0
+#define PB3MD   PB3MD1|PB3MD0
+#define PB2MD   PB2MD1|PB2MD0
+#define PB1MD   PB1MD1|PB1MD0
+#define PB0MD   PB0MD1|PB0MD0
+
+#endif /* _sh7_pfc_h */
Index: c/src/lib/libcpu/sh/sh7045/include/sh7_sci.h
===================================================================
--- c/src/lib/libcpu/sh/sh7045/include/sh7_sci.h	(revision 4a238002e71ec018723229f8669363a5ffb7302e)
+++ c/src/lib/libcpu/sh/sh7045/include/sh7_sci.h	(revision 4a238002e71ec018723229f8669363a5ffb7302e)
@@ -0,0 +1,91 @@
+/*
+ * Bit values for the serial control registers of the Hitachi SH704X
+ *
+ * From Hitachi tutorials
+ *
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#ifndef _sh7_sci_h
+#define _sh7_sci_h
+
+#include <rtems/score/iosh7045.h>
+
+/*
+ * Serial mode register bits
+ */
+
+#define SCI_SYNC_MODE               0x80
+#define SCI_SEVEN_BIT_DATA          0x40
+#define SCI_PARITY_ON               0x20
+#define SCI_ODD_PARITY              0x10
+#define SCI_STOP_BITS_2             0x08
+#define SCI_ENABLE_MULTIP           0x04
+#define SCI_PHI_64                  0x03
+#define SCI_PHI_16                  0x02
+#define SCI_PHI_4                   0x01
+#define SCI_PHI_0                   0x00
+
+/*
+ * Serial register offsets, relative to SCI0_SMR or SCI1_SMR
+ */
+
+#define SCI_SMR			0x00
+#define SCI_BRR			0x01
+#define SCI_SCR			0x02
+#define SCI_TDR			0x03
+#define SCI_SSR			0x04
+#define SCI_RDR			0x05
+
+/*
+ * Serial control register bits
+ */
+#define SCI_TIE                 0x80    /* Transmit interrupt enable */
+#define SCI_RIE                 0x40    /* Receive interrupt enable */
+#define SCI_TE                  0x20    /* Transmit enable */
+#define SCI_RE                  0x10    /* Receive enable */
+#define SCI_MPIE                0x08    /* Multiprocessor interrupt enable */
+#define SCI_TEIE                0x04    /* Transmit end interrupt enable */
+#define SCI_CKE1                0x02    /* Clock enable 1 */
+#define SCI_CKE0                0x01    /* Clock enable 0 */
+
+/*
+ * Serial status register bits
+ */
+#define SCI_TDRE                0x80    /* Transmit data register empty */
+#define SCI_RDRF                0x40    /* Receive data register full */
+#define SCI_ORER                0x20    /* Overrun error */
+#define SCI_FER                 0x10    /* Framing error */
+#define SCI_PER                 0x08    /* Parity error */
+#define SCI_TEND                0x04    /* Transmit end */
+#define SCI_MPB                 0x02    /* Multiprocessor bit */
+#define SCI_MPBT                0x01    /* Multiprocessor bit transfer */
+
+/*
+ * INTC Priority Settings
+ */
+
+#define SCI0_IPMSK	0x00F0
+#define SCI0_LOWIP	0x0010
+#define SCI1_IPMSK	0x000F
+#define SCI1_LOWIP	0x0001
+
+#endif /* _sh7_sci_h */
