Changeset 494df99f in rtems


Ignore:
Timestamp:
Dec 19, 2014, 11:13:41 AM (7 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, 5, master
Children:
7d26f60
Parents:
5175ac6a
git-author:
Sebastian Huber <sebastian.huber@…> (12/19/14 11:13:41)
git-committer:
Sebastian Huber <sebastian.huber@…> (01/09/15 13:03:33)
Message:

bsps/powerpc: Support for 64 byte cache lines

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/shared/src/bsp-start-zero.S

    r5175ac6a r494df99f  
    88
    99/*
    10  * Copyright (c) 2010 embedded brains GmbH.  All rights reserved.
     10 * Copyright (c) 2010-2014 embedded brains GmbH.  All rights reserved.
    1111 *
    1212 *  embedded brains GmbH
    13  *  Obere Lagerstr. 30
     13 *  Dornierstr. 4
    1414 *  82178 Puchheim
    1515 *  Germany
     
    2222
    2323#include <rtems/asm.h>
     24#include <rtems/powerpc/powerpc.h>
    2425#include <bspopts.h>
    2526
     
    3536        li      r0, 0
    3637        subi    r11, r3, 1
    37         clrrwi  r11, r11, 5
    38         addi    r10, r11, 32
     38        clrrwi  r11, r11, PPC_CACHE_ALIGN_POWER
     39        addi    r10, r11, PPC_CACHE_ALIGNMENT
    3940        subf    r11, r3, r10
    4041        cmplw   cr7, r11, r4
     
    5657
    5758        subf    r11, r3, r9
    58         srwi    r11, r11, 5
     59        srwi    r11, r11, PPC_CACHE_ALIGN_POWER
    5960        addi    r11, r11, 1
    6061        mtctr   r11
     
    6768        dcbf    r0, r3
    6869#else
     70  #if PPC_CACHE_ALIGNMENT >= 32
    6971        stw     r0, 0(r3)
    7072        stw     r0, 4(r3)
     
    7577        stw     r0, 24(r3)
    7678        stw     r0, 28(r3)
     79    #if PPC_CACHE_ALIGNMENT == 64
     80        stw     r0, 32(r3)
     81        stw     r0, 36(r3)
     82        stw     r0, 40(r3)
     83        stw     r0, 44(r3)
     84        stw     r0, 48(r3)
     85        stw     r0, 52(r3)
     86        stw     r0, 56(r3)
     87        stw     r0, 60(r3)
     88    #else
     89      #error "unsupported cache alignment"
     90    #endif
     91  #else
     92    #error "unsupported cache alignment"
     93  #endif
    7794#endif
    78         addi    r3, r3, 32
     95        addi    r3, r3, PPC_CACHE_ALIGNMENT
    7996main_loop_update:
    8097        bdnz+   main_loop_begin
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