Index: c/src/lib/libbsp/arm/edb7312/include/bsp.h
===================================================================
--- c/src/lib/libbsp/arm/edb7312/include/bsp.h	(revision 3d6e1740aec7aff18257d691afd8ef9f6b51acec)
+++ c/src/lib/libbsp/arm/edb7312/include/bsp.h	(revision 49232d06500801051d8bf43e5979c1d7c0f0fd14)
@@ -1,2 +1,8 @@
+/**
+ * @file
+ * @ingroup arm_edb7312
+ * @brief Global BSP definitions.
+ */
+
 /*
  * Cirrus EP7312 BSP header file
@@ -25,8 +31,15 @@
 #define BSP_FEATURE_IRQ_EXTENSION
 
-/*
- *  Define the interrupt mechanism for Time Test 27
+/**
+ * @defgroup arm_edb7312 EDB7312 Support
+ * @ingroup bsp_arm
+ * @brief EDB7312 Support Package
+ * @{
+ */
+
+/**
+ * @brief Define the interrupt mechanism for Time Test 27
  *
- *  NOTE: Following are not defined and are board independent
+ * NOTE: Following are not defined and are board independent
  *
  */
@@ -35,9 +48,15 @@
                           int                          attaching);
 
-/*
- * Network driver configuration
+/**
+ * @name Network driver configuration
+ * @{
  */
+
 #define RTEMS_BSP_NETWORK_DRIVER_NAME	"eth0"
 #define RTEMS_BSP_NETWORK_DRIVER_ATTACH	cs8900_driver_attach
+
+/** @} */
+
+/** @} */
 
 #ifdef __cplusplus
Index: c/src/lib/libbsp/arm/edb7312/include/ep7312.h
===================================================================
--- c/src/lib/libbsp/arm/edb7312/include/ep7312.h	(revision 3d6e1740aec7aff18257d691afd8ef9f6b51acec)
+++ c/src/lib/libbsp/arm/edb7312/include/ep7312.h	(revision 49232d06500801051d8bf43e5979c1d7c0f0fd14)
@@ -1,2 +1,8 @@
+/**
+ * @file
+ * @ingroup edb7312_registers
+ * @brief Register declarations.
+ */
+
 /*
  * Cirrus EP7312 register declarations
@@ -20,4 +26,11 @@
 
 #define EP7312_REG_BASE 0x80000000
+
+/**
+ * @defgroup edb7312_registers Register Definitions
+ * @ingroup arm_edb7312
+ * @brief Cirrus EP7312 Register Definitions
+ * @{
+ */
 
 #define EP7312_PADR    ((volatile uint8_t*)(EP7312_REG_BASE + 0x0000))
@@ -90,5 +103,10 @@
 
 /* serial port bits */
-/* BITS in UBRLCR1 */
+
+/**
+ * @name BITS in UBRLCR1
+ * @{
+ */
+
 #define EP7312_UART_WRDLEN5    0x00000000
 #define EP7312_UART_WRDLEN6    0x00020000
@@ -101,20 +119,45 @@
 #define EP7312_UART_BREAK      0x00001000
 
-/* BITS in INTSR1 */
+/** @} */
+
+/**
+ * @name BITS in INTSR1
+ * @{
+ */
+
 #define EP7312_UART_UTXINT1    0x00002000
 #define	EP7312_UART_URXINT1    0x00001000
 
-/* BITS in UARTTDR1 */
+/** @} */
+
+/**
+ * @name BITS in UARTTDR1
+ * @{
+ */
+
 #define EP7312_UART_FRMERR     0x00000100
 #define EP7312_UART_PARERR     0x00000200
 #define EP7312_UART_OVERR      0x00000400
 
-/* BITS in system status flag register 1 */
+/** @} */
+
+/**
+ * @name BITS in system status flag register 1
+ * @{
+ */
+
 #define EP7312_UART_UBUSY1     0x00000800
 #define EP7312_UART_URXFE1     0x00400000
 #define EP7312_UART_UTXFF1     0x00800000
 
+/** @} */
+
 /* system configuration bits */
-/* BITS in SYSCON1 */
+
+/**
+ * @name  BITS in SYSCON1
+ * @{
+ */
+
 #define EP7312_SYSCON1_UART1EN       0x00000100
 #define EP7312_SYSCON1_TC1_PRESCALE  0x00000010
@@ -123,5 +166,11 @@
 #define EP7312_SYSCON1_TC2_512KHZ    0x00000080
 
-/* INTR1 (Interrupt 1) mask/status register bits */
+/** @} */
+
+/**
+ * @name INTR1 (Interrupt 1) mask/status register bits
+ * @{
+ */
+
 #define EP7312_INTR1_EXTFIQ  0x00000001
 #define EP7312_INTR1_BLINT   0x00000002
@@ -141,5 +190,11 @@
 #define EP7312_INTR1_SSEOTI  0x00008000
 
-/* INTR2 (Interrupt 2) mask/status register bits */
+/** @} */
+
+/**
+ * @name INTR2 (Interrupt 2) mask/status register bits
+ * @{
+ */
+
 #define EP7312_INTR2_KBDINT  0x00000001
 #define EP7312_INTR2_SS2RX   0x00000002
@@ -148,6 +203,16 @@
 #define EP7312_INTR2_UTXINT2 0x00002000
 
-/* INTR3 (Interrupt 3) mask/status register bits */
+/** @} */
+
+/**
+ * @name INTR3 (Interrupt 3) mask/status register bits
+ * @{
+ */
+
 #define EP7312_INTR2_DAIINT  0x00000001
 
+/** @} */
+
+/** @} */
+
 #endif /* __EP7312_H__ */
Index: c/src/lib/libbsp/arm/edb7312/irq/irq.h
===================================================================
--- c/src/lib/libbsp/arm/edb7312/irq/irq.h	(revision 3d6e1740aec7aff18257d691afd8ef9f6b51acec)
+++ c/src/lib/libbsp/arm/edb7312/irq/irq.h	(revision 49232d06500801051d8bf43e5979c1d7c0f0fd14)
@@ -1,2 +1,8 @@
+/**
+ * @file
+ * @ingroup edb7312_interrupt
+ * @brief Interrupt definitions.
+ */
+
 /*
  * Cirrus EP7312 Intererrupt handler
@@ -24,5 +30,16 @@
 #endif /* __asm__ */
 
-  /* int interrupt status/mask register 1 */
+/**
+ * @defgroup edb7312_interrupt Interrupt Support
+ * @ingroup arm_edb7312
+ * @brief Interrupt Support
+ * @{
+ */
+
+/**
+ * @name int interrupt status/mask register 1
+ * @{
+ */
+
 #define BSP_EXTFIQ     0
 #define BSP_BLINT      1
@@ -41,5 +58,12 @@
 #define BSP_UMSINT    14
 #define BSP_SSEOTI    15
- /* int interrupt status/mask register 2 */
+
+/** @} */
+
+/**
+ * @name int interrupt status/mask register 2
+ * @{
+ */
+
 #define BSP_KBDINT    16
 #define BSP_SS2RX     17
@@ -47,7 +71,16 @@
 #define BSP_UTXINT2   19
 #define BSP_URXINT2   20
- /* int interrupt status/mask register 3 */
+
+/** @} */
+
+/**
+ * @name int interrupt status/mask register 3
+ * @{
+ */
+
 #define BSP_DAIINT    21
 #define BSP_MAX_INT   22
+
+/** @} */
 
 #define BSP_INTERRUPT_VECTOR_MIN 0
@@ -55,3 +88,5 @@
 #define BSP_INTERRUPT_VECTOR_MAX (BSP_MAX_INT - 1)
 
+/** @} */
+
 #endif /* __IRQ_H__ */
