Changeset 49232d0 in rtems


Ignore:
Timestamp:
Dec 21, 2013, 9:50:55 PM (5 years ago)
Author:
Daniel Ramirez <javamonn@…>
Branches:
4.11, master
Children:
582553d9
Parents:
3d6e174
git-author:
Daniel Ramirez <javamonn@…> (12/21/13 21:50:55)
git-committer:
Gedare Bloom <gedare@…> (12/22/13 19:04:22)
Message:

arm_edb7312: added new doxygen

Location:
c/src/lib/libbsp/arm/edb7312
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/edb7312/include/bsp.h

    r3d6e174 r49232d0  
     1/**
     2 * @file
     3 * @ingroup arm_edb7312
     4 * @brief Global BSP definitions.
     5 */
     6
    17/*
    28 * Cirrus EP7312 BSP header file
     
    2531#define BSP_FEATURE_IRQ_EXTENSION
    2632
    27 /*
    28  *  Define the interrupt mechanism for Time Test 27
     33/**
     34 * @defgroup arm_edb7312 EDB7312 Support
     35 * @ingroup bsp_arm
     36 * @brief EDB7312 Support Package
     37 * @{
     38 */
     39
     40/**
     41 * @brief Define the interrupt mechanism for Time Test 27
    2942 *
    30  *  NOTE: Following are not defined and are board independent
     43 * NOTE: Following are not defined and are board independent
    3144 *
    3245 */
     
    3548                          int                          attaching);
    3649
    37 /*
    38  * Network driver configuration
     50/**
     51 * @name Network driver configuration
     52 * @{
    3953 */
     54
    4055#define RTEMS_BSP_NETWORK_DRIVER_NAME   "eth0"
    4156#define RTEMS_BSP_NETWORK_DRIVER_ATTACH cs8900_driver_attach
     57
     58/** @} */
     59
     60/** @} */
    4261
    4362#ifdef __cplusplus
  • c/src/lib/libbsp/arm/edb7312/include/ep7312.h

    r3d6e174 r49232d0  
     1/**
     2 * @file
     3 * @ingroup edb7312_registers
     4 * @brief Register declarations.
     5 */
     6
    17/*
    28 * Cirrus EP7312 register declarations
     
    2026
    2127#define EP7312_REG_BASE 0x80000000
     28
     29/**
     30 * @defgroup edb7312_registers Register Definitions
     31 * @ingroup arm_edb7312
     32 * @brief Cirrus EP7312 Register Definitions
     33 * @{
     34 */
    2235
    2336#define EP7312_PADR    ((volatile uint8_t*)(EP7312_REG_BASE + 0x0000))
     
    90103
    91104/* serial port bits */
    92 /* BITS in UBRLCR1 */
     105
     106/**
     107 * @name BITS in UBRLCR1
     108 * @{
     109 */
     110
    93111#define EP7312_UART_WRDLEN5    0x00000000
    94112#define EP7312_UART_WRDLEN6    0x00020000
     
    101119#define EP7312_UART_BREAK      0x00001000
    102120
    103 /* BITS in INTSR1 */
     121/** @} */
     122
     123/**
     124 * @name BITS in INTSR1
     125 * @{
     126 */
     127
    104128#define EP7312_UART_UTXINT1    0x00002000
    105129#define EP7312_UART_URXINT1    0x00001000
    106130
    107 /* BITS in UARTTDR1 */
     131/** @} */
     132
     133/**
     134 * @name BITS in UARTTDR1
     135 * @{
     136 */
     137
    108138#define EP7312_UART_FRMERR     0x00000100
    109139#define EP7312_UART_PARERR     0x00000200
    110140#define EP7312_UART_OVERR      0x00000400
    111141
    112 /* BITS in system status flag register 1 */
     142/** @} */
     143
     144/**
     145 * @name BITS in system status flag register 1
     146 * @{
     147 */
     148
    113149#define EP7312_UART_UBUSY1     0x00000800
    114150#define EP7312_UART_URXFE1     0x00400000
    115151#define EP7312_UART_UTXFF1     0x00800000
    116152
     153/** @} */
     154
    117155/* system configuration bits */
    118 /* BITS in SYSCON1 */
     156
     157/**
     158 * @name  BITS in SYSCON1
     159 * @{
     160 */
     161
    119162#define EP7312_SYSCON1_UART1EN       0x00000100
    120163#define EP7312_SYSCON1_TC1_PRESCALE  0x00000010
     
    123166#define EP7312_SYSCON1_TC2_512KHZ    0x00000080
    124167
    125 /* INTR1 (Interrupt 1) mask/status register bits */
     168/** @} */
     169
     170/**
     171 * @name INTR1 (Interrupt 1) mask/status register bits
     172 * @{
     173 */
     174
    126175#define EP7312_INTR1_EXTFIQ  0x00000001
    127176#define EP7312_INTR1_BLINT   0x00000002
     
    141190#define EP7312_INTR1_SSEOTI  0x00008000
    142191
    143 /* INTR2 (Interrupt 2) mask/status register bits */
     192/** @} */
     193
     194/**
     195 * @name INTR2 (Interrupt 2) mask/status register bits
     196 * @{
     197 */
     198
    144199#define EP7312_INTR2_KBDINT  0x00000001
    145200#define EP7312_INTR2_SS2RX   0x00000002
     
    148203#define EP7312_INTR2_UTXINT2 0x00002000
    149204
    150 /* INTR3 (Interrupt 3) mask/status register bits */
     205/** @} */
     206
     207/**
     208 * @name INTR3 (Interrupt 3) mask/status register bits
     209 * @{
     210 */
     211
    151212#define EP7312_INTR2_DAIINT  0x00000001
    152213
     214/** @} */
     215
     216/** @} */
     217
    153218#endif /* __EP7312_H__ */
  • c/src/lib/libbsp/arm/edb7312/irq/irq.h

    r3d6e174 r49232d0  
     1/**
     2 * @file
     3 * @ingroup edb7312_interrupt
     4 * @brief Interrupt definitions.
     5 */
     6
    17/*
    28 * Cirrus EP7312 Intererrupt handler
     
    2430#endif /* __asm__ */
    2531
    26   /* int interrupt status/mask register 1 */
     32/**
     33 * @defgroup edb7312_interrupt Interrupt Support
     34 * @ingroup arm_edb7312
     35 * @brief Interrupt Support
     36 * @{
     37 */
     38
     39/**
     40 * @name int interrupt status/mask register 1
     41 * @{
     42 */
     43
    2744#define BSP_EXTFIQ     0
    2845#define BSP_BLINT      1
     
    4158#define BSP_UMSINT    14
    4259#define BSP_SSEOTI    15
    43  /* int interrupt status/mask register 2 */
     60
     61/** @} */
     62
     63/**
     64 * @name int interrupt status/mask register 2
     65 * @{
     66 */
     67
    4468#define BSP_KBDINT    16
    4569#define BSP_SS2RX     17
     
    4771#define BSP_UTXINT2   19
    4872#define BSP_URXINT2   20
    49  /* int interrupt status/mask register 3 */
     73
     74/** @} */
     75
     76/**
     77 * @name int interrupt status/mask register 3
     78 * @{
     79 */
     80
    5081#define BSP_DAIINT    21
    5182#define BSP_MAX_INT   22
     83
     84/** @} */
    5285
    5386#define BSP_INTERRUPT_VECTOR_MIN 0
     
    5588#define BSP_INTERRUPT_VECTOR_MAX (BSP_MAX_INT - 1)
    5689
     90/** @} */
     91
    5792#endif /* __IRQ_H__ */
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