- Timestamp:
- 12/15/14 14:22:18 (9 years ago)
- Branches:
- 4.11, 5, master
- Children:
- 481054e0
- Parents:
- a0b1b5ed
- git-author:
- Sebastian Huber <sebastian.huber@…> (12/15/14 14:22:18)
- git-committer:
- Sebastian Huber <sebastian.huber@…> (12/16/14 10:34:47)
- Location:
- doc/cpu_supplement
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
doc/cpu_supplement/arm.t
ra0b1b5ed r48cfe68 52 52 53 53 @end itemize 54 55 @c 56 @c 57 @c 58 @section Multilibs 59 60 The following multilibs are available: 61 62 @enumerate 63 @item @code{.}: ARMv4T, ARM instruction set 64 @item @code{thumb}: ARMv4T, Thumb-1 instruction set 65 @item @code{thumb/armv6-m}: ARMv6M, subset of Thumb-2 instruction set 66 @item @code{thumb/armv7-a}: ARMv7-A, Thumb-2 instruction set 67 @item @code{thumb/armv7-a/neon/hard}: ARMv7-A, Thumb-2 instruction set with 68 hard-float ABI Neon and VFP-D32 support 69 @item @code{thumb/armv7-r}: ARMv7-R, Thumb-2 instruction set 70 @item @code{thumb/armv7-r/vfpv3-d16/hard}: ARMv7-R, Thumb-2 instruction set 71 with hard-float ABI VFP-D16 support 72 @item @code{thumb/armv7-m}: ARMv7-M, Thumb-2 instruction set with hardware 73 integer division (SDIV/UDIV) 74 @item @code{thumb/armv7-m/fpv4-sp-d16}: ARMv7-M, Thumb-2 instruction set with 75 hardware integer division (SDIV/UDIV) and hard-float ABI FPv4-SP support 76 @item @code{eb/thumb/armv7-r}: ARMv7-R, Big-endian Thumb-2 instruction set 77 @item @code{eb/thumb/armv7-r/vfpv3-d16/hard}: ARMv7-R, Big-endian Thumb-2 78 instruction set with hard-float ABI VFP-D16 support 79 @end enumerate 80 81 Multilib 1. and 2. support the standard ARM7TDMI and ARM926EJ-S targets. 82 83 Multilib 3. supports the Cortex-M0 and Cortex-M1 cores. 84 85 Multilib 8. supports the Cortex-M3 and Cortex-M4 cores, which have a special 86 hardware integer division instruction (this is not present in the A and R 87 profiles). 88 89 Multilib 9. supports the Cortex-M4 cores with a floating point unit. 90 91 Multilib 4. and 5. support the Cortex-A processors. 92 93 Multilib 6., 7., 10. and 11. support the Cortex-R processors. Here also 94 big-endian variants are available. 95 96 Use for example the following GCC options 97 98 @example 99 -mthumb -march=armv7-a -mfpu=neon -mfloat-abi=hard -mtune=cortex-a9 100 @end example 101 102 to build an application or BSP for the ARMv7-A architecture and tune the code 103 for a Cortex-A9 processor. It is important to select the options used for the 104 multilibs. For example 105 106 @example 107 -mthumb -mcpu=cortex-a9 108 @end example 109 110 alone will not select the ARMv7-A multilib. 54 111 55 112 @section Calling Conventions -
doc/cpu_supplement/general.t
ra0b1b5ed r48cfe68 99 99 100 100 @end itemize 101 102 @c 103 @c 104 @c 105 @section Multilibs 106 107 Newlib and GCC provide several target libraries like the @file{libc.a}, 108 @file{libm.a} and @file{libgcc.a}. These libraries are artifacts of the GCC 109 build process. Newlib is built together with GCC. To provide optimal support 110 for various chip derivatives and instruction set revisions multiple variants of 111 these libraries are available for each architecture. For example one set may 112 use software floating point support and another set may use hardware floating 113 point instructions. These sets of libraries are called @emph{multilibs}. Each 114 library set corresponds to an application binary interface (ABI) and 115 instruction set. 116 117 A multilib variant can be usually detected via built-in compiler defines at 118 compile-time. This mechanism is used by RTEMS to select for example the 119 context switch support for a particular BSP. The built-in compiler defines 120 corresponding to multilibs are the only architecture specific defines allowed 121 in the @code{cpukit} area of the RTEMS sources. 122 123 Invoking the GCC with the @code{-print-multi-lib} option lists the available 124 multilibs. Each line of the output describes one multilib variant. The 125 default variant is denoted by @code{.} which is selected when no or 126 contradicting GCC machine options are selected. The multilib selection for a 127 target is specified by target makefile fragments (see file @file{t-rtems} in 128 the GCC sources and section 129 @uref{https://gcc.gnu.org/onlinedocs/gccint/Target-Fragment.html#Target-Fragment,The Target Makefile Fragment} 130 in the @uref{https://gcc.gnu.org/onlinedocs/gccint/,GCC Internals Manual}. 101 131 102 132 @c -
doc/cpu_supplement/powerpc.t
ra0b1b5ed r48cfe68 178 178 179 179 @end table 180 181 @c 182 @c 183 @c 184 @section Multilibs 185 186 The following multilibs are available: 187 188 @enumerate 189 @item @code{.}: 32-bit PowerPC with FPU 190 @item @code{nof}: 32-bit PowerPC with software floating point support 191 @item @code{m403}: Instruction set for PPC403 with FPU 192 @item @code{m505}: Instruction set for MPC505 with FPU 193 @item @code{m603e}: Instruction set for MPC603e with FPU 194 @item @code{m603e/nof}: Instruction set for MPC603e with software floating 195 point support 196 @item @code{m604}: Instruction set for MPC604 with FPU 197 @item @code{m604/nof}: Instruction set for MPC604 with software floating point 198 support 199 @item @code{m860}: Instruction set for MPC860 with FPU 200 @item @code{m7400}: Instruction set for MPC7500 with FPU 201 @item @code{m7400/nof}: Instruction set for MPC7500 with software floating 202 point support 203 @item @code{m8540}: Instruction set for e200, e500 and e500v2 cores with 204 single-precision FPU and SPE 205 @item @code{m8540/gprsdouble}: Instruction set for e200, e500 and e500v2 cores 206 with double-precision FPU and SPE 207 @item @code{m8540/nof/nospe}: Instruction set for e200, e500 and e500v2 cores 208 with software floating point support and no SPE 209 @item @code{me6500/m32}: 32-bit instruction set for e6500 core with FPU and 210 AltiVec 211 @item @code{me6500/m32/nof/noaltivec}: 32-bit instruction set for e6500 core 212 with software floating point support and no AltiVec 213 @end enumerate 180 214 181 215 @c
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