Changeset 487b94e7 in rtems


Ignore:
Timestamp:
Apr 15, 2014, 11:34:24 AM (5 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, master
Children:
b80f920
Parents:
598f39cd
git-author:
Sebastian Huber <sebastian.huber@…> (04/15/14 11:34:24)
git-committer:
Sebastian Huber <sebastian.huber@…> (04/16/14 07:07:33)
Message:

bsps/powerpc: SMP support for SPR functions

These registers are local to a processor, there is no need to use SMP
locks here.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/powerpc/shared/include/powerpc-utility.h

    r598f39cd r487b94e7  
    99
    1010/*
    11  * Copyright (c) 2008-2013 embedded brains GmbH.
     11 * Copyright (c) 2008-2014 embedded brains GmbH.
    1212 *
    1313 *  embedded brains GmbH
     
    579579#define PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS(spr, bits) \
    580580  do { \
    581     rtems_interrupt_level level; \
     581    ISR_Level level; \
    582582    uint32_t val; \
    583583    uint32_t mybits = bits; \
    584     rtems_interrupt_disable(level); \
     584    _ISR_Disable_without_giant(level); \
    585585    val = PPC_SPECIAL_PURPOSE_REGISTER(spr); \
    586586    val |= mybits; \
    587587    PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val); \
    588     rtems_interrupt_enable(level); \
     588    _ISR_Enable_without_giant(level); \
    589589  } while (0)
    590590
     
    598598#define PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS_MASKED(spr, bits, mask) \
    599599  do { \
    600     rtems_interrupt_level level; \
     600    ISR_Level level; \
    601601    uint32_t val; \
    602602    uint32_t mybits = bits; \
    603603    uint32_t mymask = mask; \
    604     rtems_interrupt_disable(level); \
     604    _ISR_Disable_without_giant(level); \
    605605    val = PPC_SPECIAL_PURPOSE_REGISTER(spr); \
    606606    val &= ~mymask; \
    607607    val |= mybits; \
    608608    PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val); \
    609     rtems_interrupt_enable(level); \
     609    _ISR_Enable_without_giant(level); \
    610610  } while (0)
    611611
     
    618618#define PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS(spr, bits) \
    619619  do { \
    620     rtems_interrupt_level level; \
     620    ISR_Level level; \
    621621    uint32_t val; \
    622622    uint32_t mybits = bits; \
    623     rtems_interrupt_disable(level); \
     623    _ISR_Disable_without_giant(level); \
    624624    val = PPC_SPECIAL_PURPOSE_REGISTER(spr); \
    625625    val &= ~mybits; \
    626626    PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val); \
    627     rtems_interrupt_enable(level); \
     627    _ISR_Enable_without_giant(level); \
    628628  } while (0)
    629629
     
    668668#define PPC_SET_DEVICE_CONTROL_REGISTER_BITS(dcr, bits) \
    669669  do { \
    670     rtems_interrupt_level level; \
     670    ISR_Level level; \
    671671    uint32_t val; \
    672672    uint32_t mybits = bits; \
    673     rtems_interrupt_disable(level); \
     673    _ISR_Disable_without_giant(level); \
    674674    val = PPC_DEVICE_CONTROL_REGISTER(dcr); \
    675675    val |= mybits; \
    676676    PPC_SET_DEVICE_CONTROL_REGISTER(dcr, val); \
    677     rtems_interrupt_enable(level); \
     677    _ISR_Enable_without_giant(level); \
    678678  } while (0)
    679679
     
    687687#define PPC_SET_DEVICE_CONTROL_REGISTER_BITS_MASKED(dcr, bits, mask) \
    688688  do { \
    689     rtems_interrupt_level level; \
     689    ISR_Level level; \
    690690    uint32_t val; \
    691691    uint32_t mybits = bits; \
    692692    uint32_t mymask = mask; \
    693     rtems_interrupt_disable(level); \
     693    _ISR_Disable_without_giant(level); \
    694694    val = PPC_DEVICE_CONTROL_REGISTER(dcr); \
    695695    val &= ~mymask; \
    696696    val |= mybits; \
    697697    PPC_SET_DEVICE_CONTROL_REGISTER(dcr, val); \
    698     rtems_interrupt_enable(level); \
     698    _ISR_Enable_without_giant(level); \
    699699  } while (0)
    700700
     
    707707#define PPC_CLEAR_DEVICE_CONTROL_REGISTER_BITS(dcr, bits) \
    708708  do { \
    709     rtems_interrupt_level level; \
     709    ISR_Level level; \
    710710    uint32_t val; \
    711711    uint32_t mybits = bits; \
    712     rtems_interrupt_disable(level); \
     712    _ISR_Disable_without_giant(level); \
    713713    val = PPC_DEVICE_CONTROL_REGISTER(dcr); \
    714714    val &= ~mybits; \
    715715    PPC_SET_DEVICE_CONTROL_REGISTER(dcr, val); \
    716     rtems_interrupt_enable(level); \
     716    _ISR_Enable_without_giant(level); \
    717717  } while (0)
    718718
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