Changeset 479c86dd in rtems


Ignore:
Timestamp:
Sep 23, 1998, 1:22:43 PM (21 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
1cf2df40
Parents:
8a496e46
Message:

Patch from Erik Ivanenko <erik.ivanenko@…>:

Please find attached the two files that have been changed relative to
980921 . The changes here are in the handling of the counter-timer used
as the basis for the rtems executive clock. For the most part, these
are housekeeping changes.

The PSCLK frequency change in start.s... was a part of several
bug-fixes. The fix improves executive clock and timer accuracy.

changes :

start.s -- All timers are disabled by the initialization routine

-- PSCLK ( used by clock and timers ) frequency changed to 1MHz

The clock_initialize routine now assumes that the PSCLK frequency is
exactly 1 MHz.

ckinit.c

Clock_isr -- removed division by 1000. Now use 'static'
variable -- clock_intial_isr_value -- to reset Clock_isrs variable.
clock_initialize -- moved counter timer initialization here. Values
used to configure the timer are totally dependent on
BSP_configuration.microseconds_per_tick ( and the PSCLK assumption).
Initializes clock_initial_isr_value used by th Clock_isr to reset
Clock_isrs.

clock_on -- no longer configures the timer, just enables it.

Since altering the number of sections in the BSP, I decided to give it a
good "once over" . The clock handling is now cleaner.

Location:
c/src/lib/libbsp/i386/i386ex
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/i386/i386ex/clock/ckinit.c

    r8a496e46 r479c86dd  
    3434
    3535rtems_unsigned32 Clock_isrs;              /* ISRs until next tick */
     36static rtems_unsigned32 Clock_initial_isr_value;
    3637
    3738volatile rtems_unsigned32 Clock_driver_ticks;
     
    5657  if ( Clock_isrs == 1 ) {
    5758    rtems_clock_tick();
    58     Clock_isrs = BSP_Configuration.microseconds_per_tick / 1000;
     59    Clock_isrs = Clock_initial_isr_value; /* BSP_Configuration.microseconds_per_tick / 1000;*/
    5960  }
    6061  else
     
    6465void ClockOff(const rtems_irq_connect_data* unused)
    6566{
    66   /* should do something here */;
    67   outport_byte  ( TMRCFG , 0x80 );
     67  outport_byte  ( TMRCFG , 0x80 ); /* disable the counter timer */
    6868}
    6969
    7070void ClockOn(const rtems_irq_connect_data* unused)
    7171{
    72   outport_byte  ( TMRCFG , 0x80 );
    73 
    74   outport_byte    ( TMRCON , 0x34 );
    75   outport_byte  ( TMR0   , 0xA8 );
    76   outport_byte    ( TMR0   , 0x04 );
    77 
    78   outport_byte    ( TMRCFG , 0x00 );
     72  outport_byte    ( TMRCFG , 0x00 ); /* enable the counter timer */
    7973}
    8074
     
    9690)
    9791{
     92  unsigned timer_counter_init_value;
     93  unsigned char clock_lsb, clock_msb;
     94 
    9895  Clock_driver_ticks = 0;
    99   Clock_isrs = BSP_Configuration.microseconds_per_tick / 1000;
     96
     97  Clock_isrs = Clock_initial_isr_value = BSP_Configuration.microseconds_per_tick / 1000; /* ticks per clock_isr */
     98 
     99  /*
     100   * configure the counter timer ( should be based on microsecs/tick )
     101   * NB. The divisor(Clock_isrs) resolves the  is the same number that appears in confdefs.h
     102   * when setting the microseconds_per_tick value.
     103   */
     104  ClockOff      ( &clockIrqData );
     105 
     106  timer_counter_init_value  =  BSP_Configuration.microseconds_per_tick / Clock_isrs;
     107  clock_lsb = (unsigned char)timer_counter_init_value;
     108  clock_msb = timer_counter_init_value >> 8;
     109
     110  printk("timer_counter_init_value = 0x%x, lsb = 0x%x, msb = 0x%x, Clock_isrs = %d\n",timer_counter_init_value,
     111         clock_lsb, clock_msb, Clock_isrs);
     112 
     113  outport_byte  ( TMRCON , 0x34 );
     114  outport_byte  ( TMR0   , clock_lsb );       /* load LSB first */
     115  outport_byte  ( TMR0   , clock_msb );  /* then MSB       */
     116 
    100117  if (!pc386_install_rtems_irq_handler (&clockIrqData)) {
    101118    printk("Unable to initialize system clock\n");
    102119    rtems_fatal_error_occurred(1);
    103120  }
     121
    104122  /*
    105123   * make major/minor avail to others such as shared memory driver
  • c/src/lib/libbsp/i386/i386ex/start/start.s

    r8a496e46 r479c86dd  
    4545 */                     
    4646
     47#define NEXT_GAS
     48       
    4749        EXTERN (boot_card)         /* exits to bspstart   */
    4850        EXTERN (stack_start)       /* defined in startup/linkcmds */
     
    150152 * Initialize clock and power mgmt unit for:   
    151153 *      Clock Frequency = 50 Mhz
    152  *      Prescaled clock output = 1.19318 Mhz
    153  *      ( matches standard PC )
     154 *      Prescaled clock output = 1 Mhz
    154155 *      Normal halt instructions
    155156 */
     
    157158SYM(InitClk):   
    158159        SetExRegByte( PWRCON, 0x0 )
    159         SetExRegWord( CLKPRS, 0x13)
     160        SetExRegWord( CLKPRS, 0x17)   # 0x13 for 1.19318 MHz.  0x17 for 1MHz.
    160161
    161162/**************************************************************
     
    275276
    276277        SetExRegByte(TMRCON , 0x34 ) # prepare to write counter 0 LSB,MSB
    277         SetExRegByte(TMR0   , 0xA8 ) # LSB = 0B count, followed by MSB
    278         SetExRegByte(TMR0   , 0x04 ) # for INT every 50 msec. MSB = 0xE900
    279                                      # for INT every 5  msec. 0x174c
    280                                      # for INT every 1 msec. 0x04A8
    281                                      #  was 0xe900
    282        
     278        SetExRegByte(TMR0   , 0x00 ) # sfa
     279        SetExRegByte(TMR0   , 0x00 ) # sfa
     280
     281                       
    283282        SetExRegByte(TMRCON , 0x70 ) # mode 0 disables on Gate= Vcc
    284283        SetExRegByte(TMR1   , 0x00 ) # sfa
     
    287286        SetExRegByte(TMRCON , 0xB0 ) # mode 0 disables on gate =Vcc
    288287        SetExRegByte(TMR2   , 0x00 ) # 
    289         SetExRegByte(TMR2   , 0x00 ) #
    290         SetExRegByte(TMRCFG , 0x80 ) # Enable timers = 0x00
    291  
     288        SetExRegByte(TMR2   , 0x00 ) # 
     289
     290        SetExRegByte(TMRCFG , 0x80 ) # Enable = 0x00
    292291
    293292/*
Note: See TracChangeset for help on using the changeset viewer.