Ignore:
Timestamp:
Apr 7, 2010, 2:20:21 PM (10 years ago)
Author:
Thomas Doerfler <Thomas.Doerfler@…>
Branches:
4.10, 4.11, master
Children:
7417f7b7
Parents:
88919d0
Message:

fix sdram timing for MPC5200B chips

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/gen5200/start/start.S

    r88919d0 r456d9b2  
    461461        /* See Erratum 342/339 in MPC5200_Errata_L25R_3_June.pdf:       */
    462462        /* set 5 delays to their maximum to support two banks           */
    463         LWI     r30, 0xCC222600                 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x2 */
    464         stw     r30, CFG1(r31)                  /* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */
     463#if 0
     464        LWI     r30, 0xCC222600                 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x2 */
     465#else
     466        /* EB 04.12.08:
     467         * on MPC5200B, Erratum342 is no longer applicable.
     468         * on MPC5200_, Single Write2Read/Prec is only 3 bits,
     469         *     therefore the MSB of the set value (1100) was ignored
     470         * in the MPC5200B, this bit is implemented in results in
     471         *     SSSLLLOOOWWW access to SDRAM. To make the mem ctrl settings compatible with the MPC5200_,
     472         *     we use a 4 for now.
     473         */
     474        LWI     r30, 0xC4222600                 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x4 */
     475#endif
     476        stw     r30, CFG1(r31)                  /* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */
    465477                                                /* Refr.2No-Read delay=0x06, Write latency=0x0 */
    466 
    467         LWI     r30, 0xCCC70004                 /* Burst2Read Prec.delay=0x8, Burst Write delay=0x8 */
     478       
     479        LWI     r30, 0xCCC70004                 /* Burst2Read Prec.delay=0x8, Burst Write delay=0x8 */ 
    468480        stw     r30, CFG2(r31)                  /* Burst Read2Write delay=0xB, Burst length=0x7, Read Tap=0x4 */
    469481
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