Changeset 455bd4e in rtems


Ignore:
Timestamp:
Jan 4, 2013, 2:49:56 PM (7 years ago)
Author:
Alex Ivanov <alexivanov97@…>
Branches:
4.11, master
Children:
a1f9934
Parents:
2305f97
git-author:
Alex Ivanov <alexivanov97@…> (01/04/13 14:49:56)
git-committer:
Jennifer Averett <jennifer.averett@…> (01/04/13 14:49:56)
Message:

score: Doxygen Clean Up Task #9

Location:
cpukit/score/cpu/avr/avr
Files:
20 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/avr/avr/io2333.h

    r2305f97 r455bd4e  
    4747#endif
    4848
    49 /* I/O registers */
    50 
     49/**
     50 * @name I/O Registers
     51 *
     52 * @{
     53 */
    5154/* UART Baud Rate Register high */
    5255#define UBRRH   _SFR_IO8(0x03)
     
    172175/* General Interrupt MaSK register */
    173176#define GIMSK   _SFR_IO8(0x3B)
    174 
    175 /* Interrupt vectors */
    176 
     177/** @} */
     178
     179/**
     180 * @name Interrupt Vectors
     181 *
     182 * @{
     183 */
    177184/* External Interrupt 0 */
    178185#define INT0_vect                       _VECTOR(1)
     
    228235
    229236#define _VECTORS_SIZE 28
     237/** @} */
    230238
    231239/*
     
    435443#define    EERE      0
    436444
    437 /* Constants */
     445/**
     446 * @name Constants
     447 *
     448 * @{
     449 */
    438450#define    RAMEND   0xDF    /*Last On-Chip SRAM location*/
    439451#define    XRAMEND  RAMEND
    440452#define    E2END    0x7F
    441453#define    FLASHEND 0x7FF
     454/** @} */
    442455
    443456#endif /* _AVR_IO2333_H_ */
  • cpukit/score/cpu/avr/avr/io43u35x.h

    r2305f97 r455bd4e  
    4747#endif
    4848
    49 /* I/O registers */
    50 
     49/**
     50 * @name I/O Registers
     51 *
     52 * @{
     53 */
    5154/* ADC Data Register */
    5255#ifndef __ASSEMBLER__
     
    180183/* General Interrupt Mask register */
    181184#define GIMSK   _SFR_IO8(0x3B)
    182 
    183 /* Interrupt vectors */
    184 
     185/** @} */
     186
     187/**
     188 * @name Interrupt Vectors
     189 *
     190 * @{
     191 */
    185192#define SIG_INTERRUPT0          _VECTOR(1)  /* suspend/resume */
    186193#define SIG_INTERRUPT1          _VECTOR(2)
     
    197204
    198205#define _VECTORS_SIZE 52
     206/** @} */
    199207
    200208/*
    201    The Register Bit names are represented by their bit number (0-7).
    202 */
     209 * The Register Bit names are represented by their bit number (0-7).
     210 */
    203211
    204212/* Timer/Counter Interrupt MaSK register */
     
    419427#define    ADPS0    0 
    420428
    421 /* Constants */
     429/**
     430 * @name Constants
     431 *
     432 * @{
     433 */
    422434#define    RAMEND   0x045F     /*Last On-Chip SRAM Location*/
    423435#define    XRAMEND  RAMEND
    424436#define    E2END    0x0000
    425437#define    FLASHEND 0x5FFF
     438/** @} */
    426439
    427440#endif /* _AVR_43USB355_H_ */
  • cpukit/score/cpu/avr/avr/iom16a.h

    r2305f97 r455bd4e  
    4848#define _AVR_ATmega16A_H_ 1
    4949
    50 
    51 /* Registers and associated bit numbers. */
    52 
     50/**
     51 * @name Registers and Associated Bit Numbers
     52 *
     53 * @{
     54 */
    5355#define TWBR _SFR_IO8(0x00)
    5456#define TWBR0 0
     
    655657#define OCR0_7 7
    656658
    657 
    658 /* Interrupt vectors */
     659/** @} */
     660
     661/**
     662 * @name Interrupt Vectors
     663 *
     664 * @{
     665 */
    659666/* Vector 0 is the reset vector */
    660667#define INT0_vect_num  1
     
    669676#define TIMER1_CAPT_vect      _VECTOR(5)  /* Timer/Counter1 Capture Event */
    670677#define TIMER1_COMPA_vect_num  6
    671 #define TIMER1_COMPA_vect      _VECTOR(6)  /* Timer/Counter1 Compare Match A */
     678/* Timer/Counter1 Compare Match A */
     679#define TIMER1_COMPA_vect      _VECTOR(6) 
    672680#define TIMER1_COMPB_vect_num  7
    673 #define TIMER1_COMPB_vect      _VECTOR(7)  /* Timer/Counter1 Compare Match B */
     681/* Timer/Counter1 Compare Match B */
     682#define TIMER1_COMPB_vect      _VECTOR(7) 
    674683#define TIMER1_OVF_vect_num  8
    675684#define TIMER1_OVF_vect      _VECTOR(8)  /* Timer/Counter1 Overflow */
     
    701710#define _VECTOR_SIZE 4 /* Size of individual vector. */
    702711#define _VECTORS_SIZE (21 * _VECTOR_SIZE)
    703 
    704 
    705 /* Constants */
     712/** @} */
     713
     714/**
     715 * @name Constants
     716 *
     717 * @{
     718 */
    706719#define SPM_PAGESIZE (128)
    707720#define RAMSTART     (0x60)
     
    714727#define E2PAGESIZE   (4)
    715728#define FLASHEND     (0x3FFF)
    716 
    717 
    718 /* Fuses */
     729/** @} */
     730
     731/**
     732 * @name Fuses
     733 *
     734 * @{
     735 */
    719736#define FUSE_MEMORY_SIZE 2
    720737
     
    727744#define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
    728745#define FUSE_BODEN  (unsigned char)~_BV(6)  /* Brown out detector enable */
    729 #define FUSE_BODLEVEL  (unsigned char)~_BV(7)  /* Brown out detector trigger level */
    730 #define LFUSE_DEFAULT (FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1)
     746/* Brown out detector trigger level */
     747#define FUSE_BODLEVEL  (unsigned char)~_BV(7) 
     748#define LFUSE_DEFAULT (FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & \
     749                       FUSE_CKSEL2 & FUSE_CKSEL1)
    731750
    732751/* High Fuse Byte */
     
    734753#define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
    735754#define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
    736 #define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
     755/* EEPROM memory is preserved through chip erase */
     756#define FUSE_EESAVE  (unsigned char)~_BV(3) 
    737757#define FUSE_CKOPT  (unsigned char)~_BV(4)  /* Oscillator Options */
    738 #define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
     758/* Enable Serial programming and Data Downloading */
     759#define FUSE_SPIEN  (unsigned char)~_BV(5) 
    739760#define FUSE_JTAGEN  (unsigned char)~_BV(6)  /* Enable JTAG */
    740761#define FUSE_OCDEN  (unsigned char)~_BV(7)  /* Enable OCD */
    741762#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
    742 
    743 
    744 /* Lock Bits */
     763/** @} */
     764
     765/**
     766 * @name Lock Bits
     767 *
     768 * @{
     769 */
    745770#define __LOCK_BITS_EXIST
    746771#define __BOOT_LOCK_BITS_0_EXIST
    747772#define __BOOT_LOCK_BITS_1_EXIST
    748 
    749 
    750 /* Signature */
     773/** @} */
     774
     775/**
     776 * @name Signature
     777 *
     778 * @{
     779 */
    751780#define SIGNATURE_0 0x1E
    752781#define SIGNATURE_1 0x94
    753782#define SIGNATURE_2 0x03
    754 
    755 
    756 /* Device Pin Definitions */
     783/** @} */
     784
     785/**
     786 * @name Device Pin Definitions
     787 *
     788 * @{
     789 */
    757790#define MOSI_DDR   DDRB
    758791#define MOSI_PORT  PORTB
     
    899932#define SS_PIN   PINB
    900933#define SS_BIT   4
     934/** @} */
    901935
    902936#endif /* _AVR_ATmega16A_H_ */
  • cpukit/score/cpu/avr/avr/iom2560.h

    r2305f97 r455bd4e  
    3737#include <avr/iomxx0_1.h>
    3838
    39 /* Constants */
     39/**
     40 * @name Constants
     41 *
     42 * @{
     43 */
    4044#define SPM_PAGESIZE    256
    4145#define RAMEND          0x21FF
     
    4448#define E2PAGESIZE      8
    4549#define FLASHEND        0x3FFFF
     50/** @} */
    4651
    47 
    48 /* Fuses */
    49 
     52/**
     53 * @name Fuses
     54 *
     55 * @{
     56 */
    5057#define FUSE_MEMORY_SIZE 3
    5158
     
    5966#define FUSE_CKOUT       (unsigned char)~_BV(6)
    6067#define FUSE_CKDIV8      (unsigned char)~_BV(7)
    61 #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
     68#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & \
     69                       FUSE_SUT0 & FUSE_CKDIV8)
    6270
    6371/* High Fuse Byte */
     
    7785#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
    7886#define EFUSE_DEFAULT (0xFF)
     87/** @} */
    7988
    80 
    81 /* Lock Bits */
     89/**
     90 * @name Lock Bits
     91 *
     92 * @{
     93 */
    8294#define __LOCK_BITS_EXIST
    8395#define __BOOT_LOCK_BITS_0_EXIST
    8496#define __BOOT_LOCK_BITS_1_EXIST
     97/** @} */
    8598
    86 
    87 /* Signature */
     99/**
     100 * @name Signature
     101 *
     102 * @{
     103 */
    88104#define SIGNATURE_0 0x1E
    89105#define SIGNATURE_1 0x98
    90106#define SIGNATURE_2 0x01
    91 
     107/** @} */
    92108
    93109#endif /* _AVR_IOM2560_H_ */
  • cpukit/score/cpu/avr/avr/iom3250.h

    r2305f97 r455bd4e  
    4747#endif
    4848
    49 /* Registers and associated bit numbers */
    50 
     49/**
     50 * @name Registers and Associated Bit Numbers
     51 *
     52 * @{
     53 */
    5154#define PINA    _SFR_IO8(0x00)
    5255#define PINA7   7
     
    296299#define EEARH   _SFR_IO8(0X22)
    297300
    298 /* 6-char sequence denoting where to find the EEPROM registers in memory space.
    299    Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
    300    subroutines.
    301    First two letters:  EECR address.
    302    Second two letters: EEDR address.
    303    Last two letters:   EEAR address.  */
     301/*
     302 * 6-char sequence denoting where to find the EEPROM registers in
     303 * memory space.
     304 * Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
     305 * subroutines.
     306 * First two letters:  EECR address.
     307 * Second two letters: EEDR address.
     308 * Last two letters:   EEAR address. 
     309 */
    304310#define __EEPROM_REG_LOCATIONS__ 1F2021
    305311
     
    752758
    753759/* Reserved [0xDE..0xFF] */
    754 
    755 
    756 /* Interrupt vectors */
     760/** @} */
     761
     762/**
     763 * @name Interrupt Vectors
     764 *
     765 * @{
     766 */
    757767/* Vector 0 is the reset vector */
    758768/* External Interrupt Request 0 */
     
    852862
    853863#define _VECTORS_SIZE 100
    854 
    855 
    856 /* Constants */
     864/** @} */
     865
     866/**
     867 * @name Constants
     868 *
     869 * @{
     870 */
    857871#define SPM_PAGESIZE    128
    858872#define RAMEND          0x8FF
     
    861875#define E2PAGESIZE      4
    862876#define FLASHEND        0x7FFF
    863 
    864 
    865 /* Fuses */
    866 
     877/** @} */
     878
     879/**
     880 * @name Fuses
     881 *
     882 * @{
     883 */
    867884#define FUSE_MEMORY_SIZE 3
    868885
     
    876893#define FUSE_CKOUT       (unsigned char)~_BV(6)
    877894#define FUSE_CKDIV8      (unsigned char)~_BV(7)
    878 #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
     895#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & \
     896                       FUSE_SUT0 & FUSE_CKDIV8)
    879897
    880898/* High Fuse Byte */
     
    894912#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
    895913#define EFUSE_DEFAULT (0xFF)
    896 
    897 
    898 /* Lock Bits */
     914/** @} */
     915
     916/**
     917 * @name Lock Bits
     918 *
     919 * @{
     920 */
    899921#define __LOCK_BITS_EXIST
    900922#define __BOOT_LOCK_BITS_0_EXIST
    901923#define __BOOT_LOCK_BITS_1_EXIST
    902 
    903 
    904 /* Signature */
     924/** @} */
     925
     926/**
     927 * @name Signature
     928 *
     929 * @{
     930 */
    905931#define SIGNATURE_0 0x1E
    906932#define SIGNATURE_1 0x95
    907933#define SIGNATURE_2 0x06
    908 
     934/** @} */
    909935
    910936#endif /* _AVR_IOM3250_H_ */
  • cpukit/score/cpu/avr/avr/iom329.h

    r2305f97 r455bd4e  
    4747#endif
    4848
    49 /* Registers and associated bit numbers */
    50 
     49/**
     50 * @name Registers and Associated Bit Numbers
     51 *
     52 * @{
     53 */
    5154#define PINA    _SFR_IO8(0x00)
    5255#define PINA7   7
     
    292295#define EEARH  _SFR_IO8(0X22)
    293296
    294 /* 6-char sequence denoting where to find the EEPROM registers in memory space.
    295    Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
    296    subroutines.
    297    First two letters:  EECR address.
    298    Second two letters: EEDR address.
    299    Last two letters:   EEAR address.  */
     297/*
     298 * 6-char sequence denoting where to find the EEPROM registers in
     299 * memory space.
     300 * Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
     301 * subroutines.
     302 * First two letters:  EECR address.
     303 * Second two letters: EEDR address.
     304 * Last two letters:   EEAR address. 
     305 */
    300306#define __EEPROM_REG_LOCATIONS__ 1F2021
    301307
     
    853859
    854860/* Reserved [0xFF] */
    855 
    856 /* Interrupt vectors */
     861/** @} */
     862
     863/**
     864 * @name Interrupt Vectors
     865 *
     866 * @{
     867 */
    857868/* Vector 0 is the reset vector */
    858869/* External Interrupt Request 0 */
     
    945956
    946957#define _VECTORS_SIZE 92
    947 
    948 
    949 /* Constants */
     958/** @} */
     959
     960/**
     961 * @name Constants
     962 *
     963 * @{
     964 */
    950965#define SPM_PAGESIZE    128
    951966#define RAMEND          0x8FF
     
    954969#define E2PAGESIZE      4
    955970#define FLASHEND        0x7FFF
    956 
    957 
    958 /* Fuses */
    959 
     971/** @} */
     972
     973/**
     974 * @name Fuses
     975 *
     976 * @{
     977 */
    960978#define FUSE_MEMORY_SIZE 3
    961979
     
    969987#define FUSE_CKOUT       (unsigned char)~_BV(6)
    970988#define FUSE_CKDIV8      (unsigned char)~_BV(7)
    971 #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
     989#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & \
     990                       FUSE_SUT0 & FUSE_CKDIV8)
    972991
    973992/* High Fuse Byte */
     
    980999#define FUSE_JTAGEN      (unsigned char)~_BV(6)
    9811000#define FUSE_OCDEN       (unsigned char)~_BV(7)
    982 #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
     1001#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & \
     1002                       FUSE_SPIEN & FUSE_JTAGEN)
    9831003
    9841004/* Extended Fuse Byte */
     
    9871007#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
    9881008#define EFUSE_DEFAULT (0xFF)
    989 
    990 
    991 /* Lock Bits */
     1009/** @} */
     1010
     1011/**
     1012 * @name Lock Bits
     1013 *
     1014 * @{
     1015 */
    9921016#define __LOCK_BITS_EXIST
    9931017#define __BOOT_LOCK_BITS_0_EXIST
    9941018#define __BOOT_LOCK_BITS_1_EXIST
    995 
    996 
    997 /* Signature */
     1019/** @} */
     1020
     1021/**
     1022 * @name Signature
     1023 *
     1024 * @{
     1025 */
    9981026#define SIGNATURE_0 0x1E
    9991027#define SIGNATURE_1 0x95
    10001028#define SIGNATURE_2 0x03
    1001 
     1029/** @} */
    10021030
    10031031#endif /* _AVR_IOM329_H_ */
  • cpukit/score/cpu/avr/avr/iom32u2.h

    r2305f97 r455bd4e  
    4848#define _AVR_ATmega32U2_H_ 1
    4949
    50 
    51 /* Registers and associated bit numbers. */
    52 
     50/**
     51 * @name Registers and Associated Bit Numbers
     52 *
     53 * @{
     54 */
    5355#define PINB _SFR_IO8(0x03)
    5456#define PINB0 0
     
    852854#define UPWE0 6
    853855#define UPWE1 7
    854 
    855 
    856 /* Interrupt vectors */
     856/** @} */
     857
     858/**
     859 * @name Interrupt Vectors
     860 *
     861 * @{
     862 */
    857863/* Vector 0 is the reset vector */
    858864#define INT0_vect_num  1
     
    879885#define USB_GEN_vect      _VECTOR(11)  /* USB General Interrupt Request */
    880886#define USB_COM_vect_num  12
    881 #define USB_COM_vect      _VECTOR(12)  /* USB Endpoint/Pipe Interrupt Communication Request */
     887/* USB Endpoint/Pipe Interrupt Communication Request */
     888#define USB_COM_vect      _VECTOR(12) 
    882889#define WDT_vect_num  13
    883890#define WDT_vect      _VECTOR(13)  /* Watchdog Time-out Interrupt */
     
    885892#define TIMER1_CAPT_vect      _VECTOR(14)  /* Timer/Counter2 Capture Event */
    886893#define TIMER1_COMPA_vect_num  15
    887 #define TIMER1_COMPA_vect      _VECTOR(15)  /* Timer/Counter2 Compare Match B */
     894/* Timer/Counter2 Compare Match B */
     895#define TIMER1_COMPA_vect      _VECTOR(15) 
    888896#define TIMER0_COMPA_vect_num  19
    889 #define TIMER0_COMPA_vect      _VECTOR(19)  /* Timer/Counter0 Compare Match A */
     897/* Timer/Counter0 Compare Match A */
     898#define TIMER0_COMPA_vect      _VECTOR(19) 
    890899#define TIMER0_COMPB_vect_num  20
    891 #define TIMER0_COMPB_vect      _VECTOR(20)  /* Timer/Counter0 Compare Match B */
     900/* Timer/Counter0 Compare Match B */
     901#define TIMER0_COMPB_vect      _VECTOR(20) 
    892902#define TIMER0_OVF_vect_num  21
    893903#define TIMER0_OVF_vect      _VECTOR(21)  /* Timer/Counter0 Overflow */
     
    907917#define SPM_READY_vect      _VECTOR(28)  /* Store Program Memory Read */
    908918#define TIMER1_COMPB_vect_num  16
    909 #define TIMER1_COMPB_vect      _VECTOR(16)  /* Timer/Counter2 Compare Match B */
     919/* Timer/Counter2 Compare Match B */
     920#define TIMER1_COMPB_vect      _VECTOR(16) 
    910921#define TIMER1_COMPC_vect_num  17
    911 #define TIMER1_COMPC_vect      _VECTOR(17)  /* Timer/Counter2 Compare Match C */
     922/* Timer/Counter2 Compare Match C */
     923#define TIMER1_COMPC_vect      _VECTOR(17) 
    912924#define TIMER1_OVF_vect_num  18
    913925#define TIMER1_OVF_vect      _VECTOR(18)  /* Timer/Counter1 Overflow */
     
    915927#define _VECTOR_SIZE 4 /* Size of individual vector. */
    916928#define _VECTORS_SIZE (38 * _VECTOR_SIZE)
    917 
     929/** @} */
    918930
    919931/* Constants */
     
    928940#define E2PAGESIZE   (4)
    929941#define FLASHEND     (0x7FFF)
    930 
    931 
    932 /* Fuses */
     942/** @} */
     943
     944/**
     945 * @name Fuses
     946 *
     947 * @{
     948 */
    933949#define FUSE_MEMORY_SIZE 3
    934950
     
    942958#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Oscillator options */
    943959#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
    944 #define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1)
     960#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & \
     961                       FUSE_CKSEL2 & FUSE_CKSEL1)
    945962
    946963/* High Fuse Byte */
     
    948965#define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
    949966#define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
    950 #define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
     967/* EEPROM memory is preserved through chip erase */
     968#define FUSE_EESAVE  (unsigned char)~_BV(3)
    951969#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog timer always on */
    952 #define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
     970/* Enable Serial programming and Data Downloading */
     971#define FUSE_SPIEN  (unsigned char)~_BV(5) 
    953972#define FUSE_RSTDISBL  (unsigned char)~_BV(6)  /* External Reset Disable */
    954973#define FUSE_DWEN  (unsigned char)~_BV(7)  /* dwbugWIRE Enable */
     
    956975
    957976/* Extended Fuse Byte */
    958 #define FUSE_BODLEVEL0  (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
    959 #define FUSE_BODLEVEL1  (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
    960 #define FUSE_BODLEVEL2  (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
     977/* Brown-out Detector trigger level */
     978#define FUSE_BODLEVEL0  (unsigned char)~_BV(0) 
     979/* Brown-out Detector trigger level */
     980#define FUSE_BODLEVEL1  (unsigned char)~_BV(1) 
     981/* Brown-out Detector trigger level */
     982#define FUSE_BODLEVEL2  (unsigned char)~_BV(2) 
    961983#define FUSE_HWBE  (unsigned char)~_BV(3)  /* Hardware Boot Enable */
    962984#define EFUSE_DEFAULT (0xFF)
    963 
    964 
    965 /* Lock Bits */
     985/** @} */
     986
     987/**
     988 * @name Lock Bits
     989 *
     990 * @{
     991 */
    966992#define __LOCK_BITS_EXIST
    967993#define __BOOT_LOCK_BITS_0_EXIST
    968994#define __BOOT_LOCK_BITS_1_EXIST
    969 
    970 
    971 /* Signature */
     995/** @} */
     996
     997/**
     998 * @name Signature
     999 *
     1000 * @{
     1001 */
    9721002#define SIGNATURE_0 0x1E
    9731003#define SIGNATURE_1 0x95
    9741004#define SIGNATURE_2 0x8A
    975 
     1005/** @} */
    9761006
    9771007/* Device Pin Definitions */
  • cpukit/score/cpu/avr/avr/iom644p.h

    r2305f97 r455bd4e  
    3737#include <avr/iomxx4.h>
    3838
    39 /* Constants */
     39/**
     40 * @name Constants
     41 *
     42 * @{
     43 */
    4044#define SPM_PAGESIZE 256
    4145#define RAMEND       0x10FF
     
    4448#define E2PAGESIZE   8
    4549#define FLASHEND     0xFFFF
     50/** @} */
    4651
    47 
    48 /* Fuses */
    49 
     52/**
     53 * @name Fuses
     54 *
     55 * @{
     56 */
    5057#define FUSE_MEMORY_SIZE 3
    5158
     
    5966#define FUSE_CKOUT       (unsigned char)~_BV(6)
    6067#define FUSE_CKDIV8      (unsigned char)~_BV(7)
    61 #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8)
     68#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & \
     69                       FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8)
    6270
    6371/* High Fuse Byte */
     
    7785#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
    7886#define EFUSE_DEFAULT (0xFF)
     87/** @} */
    7988
    80 
    81 /* Lock Bits */
     89/**
     90 * @name Lock Bits
     91 *
     92 * @{
     93 */
    8294#define __LOCK_BITS_EXIST
    8395#define __BOOT_LOCK_BITS_0_EXIST
    8496#define __BOOT_LOCK_BITS_1_EXIST
     97/** @} */
    8598
    86 
    87 /* Signature */
     99/**
     100 * @name Signature
     101 *
     102 * @{
     103 */
    88104#define SIGNATURE_0 0x1E
    89105#define SIGNATURE_1 0x96
    90106#define SIGNATURE_2 0x0A
    91 
     107/** @} */
    92108
    93109#endif /* _AVR_IOM644P_H_ */
  • cpukit/score/cpu/avr/avr/iom64m1.h

    r2305f97 r455bd4e  
    4949
    5050
    51 /* Registers and associated bit numbers. */
    52 
     51/**
     52 * @name Registers and Associated Bit Numbers
     53 *
     54 * @{
     55 */
    5356#define PINB _SFR_IO8(0x03)
    5457#define PINB0 0
     
    14161419#define MSG6 6
    14171420#define MSG7 7
    1418 
    1419 
    1420 /* Interrupt vectors */
     1421/** @} */
     1422
     1423/**
     1424 * @name Interrupt Vectors
     1425 *
     1426 * @{
     1427 */
    14211428/* Vector 0 is the reset vector */
    14221429#define ANACOMP0_vect_num  1
     
    14431450#define TIMER1_CAPT_vect      _VECTOR(11)  /* Timer/Counter1 Capture Event */
    14441451#define TIMER1_COMPA_vect_num  12
    1445 #define TIMER1_COMPA_vect      _VECTOR(12)  /* Timer/Counter1 Compare Match A */
     1452/* Timer/Counter1 Compare Match A */
     1453#define TIMER1_COMPA_vect      _VECTOR(12) 
    14461454#define TIMER1_COMPB_vect_num  13
    1447 #define TIMER1_COMPB_vect      _VECTOR(13)  /* Timer/Counter1 Compare Match B */
     1455/* Timer/Counter1 Compare Match B */
     1456#define TIMER1_COMPB_vect      _VECTOR(13) 
    14481457#define TIMER1_OVF_vect_num  14
    14491458#define TIMER1_OVF_vect      _VECTOR(14)  /* Timer1/Counter1 Overflow */
    14501459#define TIMER0_COMPA_vect_num  15
    1451 #define TIMER0_COMPA_vect      _VECTOR(15)  /* Timer/Counter0 Compare Match A */
     1460/* Timer/Counter0 Compare Match A */
     1461#define TIMER0_COMPA_vect      _VECTOR(15) 
    14521462#define TIMER0_COMPB_vect_num  16
    1453 #define TIMER0_COMPB_vect      _VECTOR(16)  /* Timer/Counter0 Compare Match B */
     1463/* Timer/Counter0 Compare Match B */
     1464#define TIMER0_COMPB_vect      _VECTOR(16) 
    14541465#define TIMER0_OVF_vect_num  17
    14551466#define TIMER0_OVF_vect      _VECTOR(17)  /* Timer/Counter0 Overflow */
     
    14831494#define _VECTOR_SIZE 4 /* Size of individual vector. */
    14841495#define _VECTORS_SIZE (31 * _VECTOR_SIZE)
    1485 
    1486 
    1487 /* Constants */
     1496/** @} */
     1497
     1498/**
     1499 * @name Constants
     1500 *
     1501 * @{
     1502 */
    14881503#define SPM_PAGESIZE (256)
    14891504#define RAMSTART     (0x0100)
     
    14961511#define E2PAGESIZE   (8)
    14971512#define FLASHEND     (0xFFFF)
    1498 
    1499 
    1500 /* Fuses */
     1513/** @} */
     1514
     1515/**
     1516 * @name Fuses
     1517 *
     1518 * @{
     1519 */
    15011520#define FUSE_MEMORY_SIZE 3
    15021521
     
    15101529#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Oscillator output option */
    15111530#define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
    1512 #define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1)
     1531#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & \
     1532                       FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1)
    15131533
    15141534/* High Fuse Byte */
     
    15161536#define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
    15171537#define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
    1518 #define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
     1538/* EEPROM memory is preserved through chip erase */
     1539#define FUSE_EESAVE  (unsigned char)~_BV(3) 
    15191540#define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog timer always on */
    1520 #define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
     1541/* Enable Serial programming and Data Downloading */
     1542#define FUSE_SPIEN  (unsigned char)~_BV(5) 
    15211543#define FUSE_DWEN  (unsigned char)~_BV(6)  /* DebugWIRE Enable */
    15221544#define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External Reset Disable */
     
    15241546
    15251547/* Extended Fuse Byte */
    1526 #define FUSE_BODLEVEL0  (unsigned char)~_BV(0)  /* Brown-out Detector Trigger Level */
    1527 #define FUSE_BODLEVEL1  (unsigned char)~_BV(1)  /* Brown-out Detector Trigger Level */
    1528 #define FUSE_BODLEVEL2  (unsigned char)~_BV(2)  /* Brown-out Detector Trigger Level */
     1548/* Brown-out Detector Trigger Level */
     1549#define FUSE_BODLEVEL0  (unsigned char)~_BV(0) 
     1550/* Brown-out Detector Trigger Level */
     1551#define FUSE_BODLEVEL1  (unsigned char)~_BV(1) 
     1552/* Brown-out Detector Trigger Level */
     1553#define FUSE_BODLEVEL2  (unsigned char)~_BV(2) 
    15291554#define FUSE_PSCRVB  (unsigned char)~_BV(3)  /* PSC Outputs xB Reset Value */
    15301555#define FUSE_PSCRVA  (unsigned char)~_BV(4)  /* PSC Outputs xA Reset Value */
    15311556#define FUSE_PSCRB  (unsigned char)~_BV(5)  /* PSC Reset Behavior */
    15321557#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_BODLEVEL1)
    1533 
    1534 
    1535 /* Lock Bits */
     1558/** @} */
     1559
     1560/**
     1561 * @name Lock Bits
     1562 *
     1563 * @{
     1564 */
    15361565#define __LOCK_BITS_EXIST
    15371566#define __BOOT_LOCK_BITS_0_EXIST
    15381567#define __BOOT_LOCK_BITS_1_EXIST
    1539 
    1540 
    1541 /* Signature */
     1568/** @} */
     1569
     1570/**
     1571 * @name Signature
     1572 *
     1573 * @{
     1574 */
    15421575#define SIGNATURE_0 0x1E
    15431576#define SIGNATURE_1 0x96
    15441577#define SIGNATURE_2 0x84
    1545 
     1578/** @} */
    15461579
    15471580#endif /* _AVR_ATmega64M1_H_ */
  • cpukit/score/cpu/avr/avr/iom8535.h

    r2305f97 r455bd4e  
    4747#endif
    4848
    49 /* I/O registers */
    50 
     49/**
     50 * @name I/O Registers
     51 *
     52 * @{
     53 */
    5154/* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */
    5255#define TWBR    _SFR_IO8(0x00)
     
    228231
    229232/* 0x3F SREG */
    230 
    231 /* Interrupt vectors */
    232 
     233/** @} */
     234
     235/**
     236 * @name Interrupt Vectors
     237 *
     238 * @{
     239 */
    233240/* External Interrupt 0 */
    234241#define INT0_vect                       _VECTOR(1)
     
    312319
    313320#define _VECTORS_SIZE 42
    314 
     321/** @} */
    315322/*
    316    The Register Bit names are represented by their bit number (0-7).
    317 */
     323 * The Register Bit names are represented by their bit number (0-7).
     324 */
    318325
    319326/* General Interrupt Control Register */
     
    395402
    396403/*
    397    The ADHSM bit has been removed from all documentation,
    398    as being not needed at all since the comparator has proven
    399    to be fast enough even without feeding it more power.
    400 */
     404 * The ADHSM bit has been removed from all documentation,
     405 * as being not needed at all since the comparator has proven
     406 * to be fast enough even without feeding it more power.
     407 */
    401408
    402409/* Special Function IO Register */
     
    664671#define    EERE         0
    665672
    666 /* Constants */
     673/**
     674 * @name Constants
     675 *
     676 * @{
     677 */
    667678#define SPM_PAGESIZE 64
    668679#define RAMEND       0x25F    /* Last On-Chip SRAM Location */
     
    671682#define E2PAGESIZE   4
    672683#define FLASHEND     0x1FFF
    673 
    674 
    675 /* Fuses */
    676 
     684/** @} */
     685
     686/**
     687 * @name Fuses
     688 *
     689 * @{
     690 */
    677691#define FUSE_MEMORY_SIZE 2
    678692
     
    686700#define FUSE_BODEN       (unsigned char)~_BV(6)
    687701#define FUSE_BODLEVEL    (unsigned char)~_BV(7)
    688 #define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1)
     702#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & \
     703                       FUSE_SUT0 & FUSE_SUT1)
    689704
    690705/* High Fuse Byte */
     
    698713#define FUSE_S8535C      (unsigned char)~_BV(7)
    699714#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN)
    700 
    701 
    702 /* Lock Bits */
     715/** @} */
     716
     717/**
     718 * @name Lock Bits
     719 *
     720 * @{
     721 */
    703722#define __LOCK_BITS_EXIST
    704723#define __BOOT_LOCK_BITS_0_EXIST
    705724#define __BOOT_LOCK_BITS_1_EXIST
    706 
    707 
    708 /* Signature */
     725/** @} */
     726
     727/**
     728 * @name Signature
     729 *
     730 * @{
     731 */
    709732#define SIGNATURE_0 0x1E
    710733#define SIGNATURE_1 0x93
    711734#define SIGNATURE_2 0x08
    712 
     735/** @} */
    713736
    714737#endif /* _AVR_IOM8535_H_ */
  • cpukit/score/cpu/avr/avr/iomx8.h

    r2305f97 r455bd4e  
    4747#endif
    4848
    49 /* I/O registers */
    50 
     49/**
     50 * @name I/O Registers
     51 *
     52 * @{
     53 */
    5154/* Port B */
    5255
     
    204207#define EEARH   _SFR_IO8(0X22)
    205208/*
    206 Even though EEARH is not used by the mega48, the EEAR8 bit in the register
    207 must be written to 0, according to the datasheet, hence the EEARH register
    208 must be defined for the mega48.
    209 */
    210 /* 6-char sequence denoting where to find the EEPROM registers in memory space.
    211    Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
    212    subroutines.
    213    First two letters:  EECR address.
    214    Second two letters: EEDR address.
    215    Last two letters:   EEAR address.  */
     209 * Even though EEARH is not used by the mega48, the EEAR8 bit in the register
     210 * must be written to 0, according to the datasheet, hence the EEARH register
     211 * must be defined for the mega48.
     212 */
     213/*
     214 * 6-char sequence denoting where to find the EEPROM registers in
     215 * memory space.
     216 * Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
     217 * subroutines.
     218 * First two letters:  EECR address.
     219 * Second two letters: EEDR address.
     220 * Last two letters:   EEAR address. 
     221 */
    216222#define __EEPROM_REG_LOCATIONS__ 1F2021
    217223
     
    618624#define UBRR0H  _SFR_MEM8 (0xC5)
    619625#define UDR0    _SFR_MEM8 (0xC6)
    620 
    621 /* Interrupt vectors */
    622 
     626/** @} */
     627
     628/**
     629 * @name Interrupt Vectors
     630 *
     631 * @{
     632 */
    623633/* External Interrupt Request 0 */
    624634#define INT0_vect                       _VECTOR(1)
     
    722732#define SIG_SPM_READY                   _VECTOR(25)
    723733
    724 /* The mega48 and mega88 vector tables are single instruction entries (16 bits
    725    per entry for an RJMP) while the mega168 table has double instruction
    726    entries (32 bits per entry for a JMP). */
     734/*
     735 * The mega48 and mega88 vector tables are single instruction entries (16 bits
     736 * per entry for an RJMP) while the mega168 table has double instruction
     737 * entries (32 bits per entry for a JMP).
     738 */
    727739
    728740#if defined (__AVR_ATmega168__)
     
    731743#  define _VECTORS_SIZE 52
    732744#endif
     745/** @} */
    733746
    734747#endif /* _AVR_IOM8_H_ */
  • cpukit/score/cpu/avr/avr/iotn13a.h

    r2305f97 r455bd4e  
    4848#define _AVR_ATTINY13A_H_ 1
    4949
    50 
    51 /* Registers and associated bit numbers. */
    52 
     50/**
     51 * @name Registers and Associated Bit Numbers
     52 *
     53 * @{
     54 */
    5355#define ADCSRB _SFR_IO8(0x03)
    5456#define ADTS0 0
     
    307309#define PCIE 5
    308310#define INT0 6
    309 
    310 
    311 /* Interrupt vectors */
     311/** @} */
     312
     313/**
     314 * @name Interrupt Vectors
     315 *
     316 * @{
     317 */
    312318/* Vector 0 is the reset vector */
    313319#define INT0_vect_num  1
     
    332338#define _VECTOR_SIZE 2 /* Size of individual vector. */
    333339#define _VECTORS_SIZE (10 * _VECTOR_SIZE)
    334 
    335 
    336 /* Constants */
     340/** @} */
     341
     342/**
     343 * @name Constants
     344 *
     345 * @{
     346 */
    337347#define SPM_PAGESIZE (32)
    338348#define RAMSTART     (0x60)
     
    345355#define E2PAGESIZE   (4)
    346356#define FLASHEND     (1024 - 1)
    347 
    348 
    349 /* Fuses */
     357/** @} */
     358
     359/**
     360 * @name Fuses
     361 *
     362 * @{
     363 */
    350364#define FUSE_MEMORY_SIZE 2
    351365
     
    355369#define FUSE_SUT0 (unsigned char)~_BV(2)  /* Select start-up time */
    356370#define FUSE_SUT1 (unsigned char)~_BV(3)  /* Select start-up time */
    357 #define FUSE_CKDIV8 (unsigned char)~_BV(4)  /* Start up with system clock divided by 8 */
     371/* Start up with system clock divided by 8 */
     372#define FUSE_CKDIV8 (unsigned char)~_BV(4) 
    358373#define FUSE_WDTON (unsigned char)~_BV(5)  /* Watch dog timer always on */
    359 #define FUSE_EESAVE (unsigned char)~_BV(6)  /* Keep EEprom contents during chip erase */
     374/* Keep EEprom contents during chip erase */
     375#define FUSE_EESAVE (unsigned char)~_BV(6) 
    360376#define FUSE_SPIEN (unsigned char)~_BV(7)  /* SPI programming enable */
    361377#define LFUSE_DEFAULT (FUSE_SPIEN & FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL0)
     
    363379/* High Fuse Byte */
    364380#define FUSE_RSTDISBL (unsigned char)~_BV(0)  /* Disable external reset */
    365 #define FUSE_BODLEVEL0 (unsigned char)~_BV(1)  /* Enable BOD and select level */
    366 #define FUSE_BODLEVEL1 (unsigned char)~_BV(2)  /* Enable BOD and select level */
     381/* Enable BOD and select level */
     382#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) 
     383/* Enable BOD and select level */
     384#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) 
    367385#define FUSE_DWEN (unsigned char)~_BV(3)  /* DebugWire Enable */
    368386#define FUSE_SELFPRGEN (unsigned char)~_BV(4)  /* Self Programming Enable */
    369387#define HFUSE_DEFAULT (0xFF)
    370 
    371 
    372 /* Lock Bits */
     388/** @} */
     389
     390/**
     391 * @name Lock Bits
     392 *
     393 * @{
     394 */
    373395#define __LOCK_BITS_EXIST
    374 
    375 
    376 /* Signature */
     396/** @} */
     397
     398/**
     399 * @name Signature
     400 *
     401 * @{
     402 */
    377403#define SIGNATURE_0 0x1E
    378404#define SIGNATURE_1 0x90
    379405#define SIGNATURE_2 0x07
    380 
     406/** @} */
    381407
    382408#endif /* _AVR_ATTINY13A_H_ */
  • cpukit/score/cpu/avr/avr/iotn861.h

    r2305f97 r455bd4e  
    3737#include <avr/iotnx61.h>
    3838
    39 /* Constants */
     39/**
     40 * @name Constants
     41 *
     42 * @{
     43 */
    4044#define SPM_PAGESIZE 64
    4145#define RAMEND       0x25F
     
    4448#define E2PAGESIZE   4
    4549#define FLASHEND     0x1FFF
     50/** @} */
    4651
    47 
    48 /* Fuses */
     52/**
     53 * @name Fuses
     54 *
     55 * @{
     56 */
    4957#define FUSE_MEMORY_SIZE 3
    5058
     
    5866#define FUSE_CKOUT       (unsigned char)~_BV(6)
    5967#define FUSE_CKDIV8      (unsigned char)~_BV(7)
    60 #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
     68#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & \
     69                       FUSE_SUT0 & FUSE_CKDIV8)
    6170
    6271/* High Fuse Byte */
     
    7483#define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
    7584#define EFUSE_DEFAULT (0xFF)
     85/** @} */
    7686
     87/**
     88 * @name Lock Bits
     89 *
     90 * @{
     91 */
     92#define __LOCK_BITS_EXIST
     93/** @} */
    7794
    78 /* Lock Bits */
    79 #define __LOCK_BITS_EXIST
    80 
    81 
    82 /* Signature */
     95/**
     96 * @name Signature
     97 *
     98 * @{
     99 */
    83100#define SIGNATURE_0 0x1E
    84101#define SIGNATURE_1 0x93
    85102#define SIGNATURE_2 0x0D
    86 
     103/** @} */
    87104
    88105#endif /* _AVR_IOTN861_H_ */
  • cpukit/score/cpu/avr/avr/iotnx4.h

    r2305f97 r455bd4e  
    4747#endif
    4848
    49 /* I/O registers */
    50 
     49/**
     50 * @name I/O Registers
     51 *
     52 * @{
     53 */
    5154#define PRR     _SFR_IO8 (0x00)
    5255#define PRTIM1  3
     
    379382/* 0x3F SREG      [defined in <avr/io.h>] */
    380383
    381 ///---
    382 
    383 /* Interrupt vectors */
     384/** @} */
     385
     386/**
     387 * @name Interrupt Vectors
     388 *
     389 * @{
     390 */
    384391/* Interrupt vector 0 is the reset vector. */
    385392/* External Interrupt Request 0 */
     
    453460#define _VECTORS_SIZE 34
    454461
     462/** @} */
     463
    455464#endif /* _AVR_IOTNX4_H_ */
  • cpukit/score/cpu/avr/avr/iousb162.h

    r2305f97 r455bd4e  
    3737#include <avr/iousbxx2.h>
    3838
    39 /* Constants */
     39/**
     40 * @name Constants
     41 *
     42 * @{
     43 */
    4044#define SPM_PAGESIZE 128
    4145#define RAMEND       0x2FF
     
    4448#define E2PAGESIZE   4
    4549#define FLASHEND     0x3FFF
     50/** @} */
    4651
    47 
    48 /* Fuses */
     52/**
     53 * @name Fuses
     54 *
     55 * @{
     56 */
    4957#define FUSE_MEMORY_SIZE 3
    5058
     
    7785#define FUSE_HWBE        (unsigned char)~_BV(3)
    7886#define EFUSE_DEFAULT (BODLEVEL0 & BODLEVEL1 & HWBE)
     87/** @} */
    7988
    80 
    81 /* Lock Bits */
     89/**
     90 * @name Lock Bits
     91 *
     92 * @{
     93 */
    8294#define __LOCK_BITS_EXIST
    8395#define __BOOT_LOCK_BITS_0_EXIST
    8496#define __BOOT_LOCK_BITS_1_EXIST
     97/** @} */
    8598
    86 
    87 /* Signature */
     99/**
     100 * @name Signature
     101 *
     102 * @{
     103 */
    88104#define SIGNATURE_0 0x1E
    89105#define SIGNATURE_1 0x94
    90106#define SIGNATURE_2 0x82
    91 
     107/** @} */
    92108
    93109#endif /* _AVR_AT90USB162_H_ */
  • cpukit/score/cpu/avr/avr/iox128a1.h

    r2305f97 r455bd4e  
    118118    }
    119119
    120 
    121 /*
    122 ==========================================================================
    123 IO Module Structures
    124 ==========================================================================
    125 */
    126 
     120/**
     121 * @name IO Module Structures
     122 *
     123 * @{
     124 */
    127125
    128126/*
     
    187185    CLK_SCLKSEL_RC32M_gc = (0x01<<0),  /* Internal 32MHz RC Oscillator */
    188186    CLK_SCLKSEL_RC32K_gc = (0x02<<0),  /* Internal 32kHz RC Oscillator */
    189     CLK_SCLKSEL_XOSC_gc = (0x03<<0),  /* External Crystal Oscillator or Clock */
     187    /* External Crystal Oscillator or Clock */
     188    CLK_SCLKSEL_XOSC_gc = (0x03<<0), 
    190189    CLK_SCLKSEL_PLL_gc = (0x04<<0),  /* Phase Locked Loop */
    191190} CLK_SCLKSEL_t;
     
    219218{
    220219    CLK_RTCSRC_ULP_gc = (0x00<<1),  /* 1kHz from internal 32kHz ULP */
    221     CLK_RTCSRC_TOSC_gc = (0x01<<1),  /* 1kHz from 32kHz crystal oscillator on TOSC */
    222     CLK_RTCSRC_RCOSC_gc = (0x02<<1),  /* 1kHz from internal 32kHz RC oscillator */
    223     CLK_RTCSRC_TOSC32_gc = (0x05<<1),  /* 32kHz from 32kHz crystal oscillator on TOSC */
     220    /* 1kHz from 32kHz crystal oscillator on TOSC */
     221    CLK_RTCSRC_TOSC_gc = (0x01<<1), 
     222    /* 1kHz from internal 32kHz RC oscillator */
     223    CLK_RTCSRC_RCOSC_gc = (0x02<<1), 
     224    /* 32kHz from 32kHz crystal oscillator on TOSC */
     225    CLK_RTCSRC_TOSC32_gc = (0x05<<1), 
    224226} CLK_RTCSRC_t;
    225227
     
    260262    register8_t STATUS;  /* Status Register */
    261263    register8_t XOSCCTRL;  /* External Oscillator Control Register */
    262     register8_t XOSCFAIL;  /* External Oscillator Failure Detection Register */
    263     register8_t RC32KCAL;  /* 32kHz Internal Oscillator Calibration Register */
     264    /* External Oscillator Failure Detection Register */
     265    register8_t XOSCFAIL; 
     266    /* 32kHz Internal Oscillator Calibration Register */
     267    register8_t RC32KCAL; 
    264268    register8_t PLLCTRL;  /* PLL Control REgister */
    265269    register8_t DFLLCTRL;  /* DFLL Control Register */
     
    485489    DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6),  /* Reload at end of block */
    486490    DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6),  /* Reload at end of burst */
    487     DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6),  /* Reload at end of transaction */
     491    /* Reload at end of transaction */
     492    DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), 
    488493} DMA_CH_SRCRELOAD_t;
    489494
     
    502507    DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2),  /* Reload at end of block */
    503508    DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2),  /* Reload at end of burst */
    504     DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2),  /* Reload at end of transaction */
     509    /* Reload at end of transaction */
     510    DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2),
    505511} DMA_CH_DESTRELOAD_t;
    506512
     
    524530    DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0),  /* ADCA Channel 2 */
    525531    DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0),  /* ADCA Channel 3 */
    526     DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0),  /* ADCA Channel 0,1,2,3 combined */
     532    /* ADCA Channel 0,1,2,3 combined */
     533    DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), 
    527534    DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0),  /* DACA Channel 0 */
    528535    DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0),  /* DACA Channel 1 */
     
    531538    DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0),  /* ADCB Channel 2 */
    532539    DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0),  /* ADCB Channel 3 */
    533     DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0),  /* ADCB Channel 0,1,2,3 combined */
     540    /* ADCB Channel 0,1,2,3 combined */
     541    DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), 
    534542    DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0),  /* DACB Channel 0 */
    535543    DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0),  /* DACB Channel 1 */
    536544    DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0),  /* Timer/Counter C0 Overflow */
    537545    DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0),  /* Timer/Counter C0 Error */
    538     DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0),  /* Timer/Counter C0 Compare or Capture A */
    539     DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0),  /* Timer/Counter C0 Compare or Capture B */
    540     DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0),  /* Timer/Counter C0 Compare or Capture C */
    541     DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0),  /* Timer/Counter C0 Compare or Capture D */
     546     /* Timer/Counter C0 Compare or Capture A */
     547    DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0),
     548    /* Timer/Counter C0 Compare or Capture B */
     549    DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), 
     550    /* Timer/Counter C0 Compare or Capture C */
     551    DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), 
     552    /* Timer/Counter C0 Compare or Capture D */
     553    DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), 
    542554    DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0),  /* Timer/Counter C1 Overflow */
    543555    DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0),  /* Timer/Counter C1 Error */
    544     DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0),  /* Timer/Counter C1 Compare or Capture A */
    545     DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0),  /* Timer/Counter C1 Compare or Capture B */
     556    /* Timer/Counter C1 Compare or Capture A */
     557    DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), 
     558    /* Timer/Counter C1 Compare or Capture B */
     559    DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), 
    546560    DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0),  /* SPI C Transfer Complete */
    547     DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0),  /* USART C0 Receive Complete */
    548     DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0),  /* USART C0 Data Register Empty */
    549     DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0),  /* USART C1 Receive Complete */
    550     DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0),  /* USART C1 Data Register Empty */
     561    /* USART C0 Receive Complete */
     562    DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), 
     563    /* USART C0 Data Register Empty */
     564    DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), 
     565    /* USART C1 Receive Complete */
     566    DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), 
     567    /* USART C1 Data Register Empty */
     568    DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), 
    551569    DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0),  /* Timer/Counter D0 Overflow */
    552570    DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0),  /* Timer/Counter D0 Error */
    553     DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0),  /* Timer/Counter D0 Compare or Capture A */
    554     DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0),  /* Timer/Counter D0 Compare or Capture B */
    555     DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0),  /* Timer/Counter D0 Compare or Capture C */
    556     DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0),  /* Timer/Counter D0 Compare or Capture D */
     571    /* Timer/Counter D0 Compare or Capture A */
     572    DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), 
     573    /* Timer/Counter D0 Compare or Capture B */
     574    DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), 
     575    /* Timer/Counter D0 Compare or Capture C */
     576    DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), 
     577    /* Timer/Counter D0 Compare or Capture D */
     578    DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), 
    557579    DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0),  /* Timer/Counter D1 Overflow */
    558580    DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0),  /* Timer/Counter D1 Error */
    559     DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0),  /* Timer/Counter D1 Compare or Capture A */
    560     DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0),  /* Timer/Counter D1 Compare or Capture B */
     581    /* Timer/Counter D1 Compare or Capture A */
     582    DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), 
     583    /* Timer/Counter D1 Compare or Capture B */
     584    DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), 
    561585    DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0),  /* SPI D Transfer Complete */
    562     DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0),  /* USART D0 Receive Complete */
    563     DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0),  /* USART D0 Data Register Empty */
    564     DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0),  /* USART D1 Receive Complete */
    565     DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0),  /* USART D1 Data Register Empty */
     586    /* USART D0 Receive Complete */
     587    DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), 
     588    /* USART D0 Data Register Empty */
     589    DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), 
     590    /* USART D1 Receive Complete */
     591    DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), 
     592    /* USART D1 Data Register Empty */
     593    DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), 
    566594    DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0),  /* Timer/Counter E0 Overflow */
    567595    DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0),  /* Timer/Counter E0 Error */
    568     DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0),  /* Timer/Counter E0 Compare or Capture A */
    569     DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0),  /* Timer/Counter E0 Compare or Capture B */
    570     DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0),  /* Timer/Counter E0 Compare or Capture C */
    571     DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0),  /* Timer/Counter E0 Compare or Capture D */
     596    /* Timer/Counter E0 Compare or Capture A */
     597    DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), 
     598    /* Timer/Counter E0 Compare or Capture B */
     599    DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), 
     600    /* Timer/Counter E0 Compare or Capture C */
     601    DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), 
     602    /* Timer/Counter E0 Compare or Capture D */
     603    DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0),
    572604    DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0),  /* Timer/Counter E1 Overflow */
    573605    DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0),  /* Timer/Counter E1 Error */
    574     DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0),  /* Timer/Counter E1 Compare or Capture A */
    575     DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0),  /* Timer/Counter E1 Compare or Capture B */
     606    /* Timer/Counter E1 Compare or Capture A */
     607    DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), 
     608    /* Timer/Counter E1 Compare or Capture B */
     609    DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), 
    576610    DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0),  /* SPI E Transfer Complete */
    577     DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0),  /* USART E0 Receive Complete */
    578     DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0),  /* USART E0 Data Register Empty */
    579     DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0),  /* USART E1 Receive Complete */
    580     DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0),  /* USART E1 Data Register Empty */
     611    /* USART E0 Receive Complete */
     612    DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0),
     613    /* USART E0 Data Register Empty */
     614    DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), 
     615    /* USART E1 Receive Complete */
     616    DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), 
     617    /* USART E1 Data Register Empty */
     618    DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), 
    581619    DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0),  /* Timer/Counter F0 Overflow */
    582620    DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0),  /* Timer/Counter F0 Error */
    583     DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0),  /* Timer/Counter F0 Compare or Capture A */
    584     DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0),  /* Timer/Counter F0 Compare or Capture B */
    585     DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0),  /* Timer/Counter F0 Compare or Capture C */
    586     DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0),  /* Timer/Counter F0 Compare or Capture D */
     621    /* Timer/Counter F0 Compare or Capture A */
     622    DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), 
     623    /* Timer/Counter F0 Compare or Capture B */
     624    DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), 
     625    /* Timer/Counter F0 Compare or Capture C */
     626    DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), 
     627    /* Timer/Counter F0 Compare or Capture D */
     628    DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), 
    587629    DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0),  /* Timer/Counter F1 Overflow */
    588630    DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0),  /* Timer/Counter F1 Error */
    589     DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0),  /* Timer/Counter F1 Compare or Capture A */
    590     DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0),  /* Timer/Counter F1 Compare or Capture B */
     631    /* Timer/Counter F1 Compare or Capture A */
     632    DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), 
     633    /* Timer/Counter F1 Compare or Capture B */
     634    DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), 
    591635    DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0),  /* SPI F Transfer Complete */
    592     DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0),  /* USART F0 Receive Complete */
    593     DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0),  /* USART F0 Data Register Empty */
    594     DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0),  /* USART F1 Receive Complete */
    595     DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0),  /* USART F1 Data Register Empty */
     636    /* USART F0 Receive Complete */
     637    DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), 
     638    /* USART F0 Data Register Empty */
     639    DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), 
     640    /* USART F1 Receive Complete */
     641    DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), 
     642    /* USART F1 Data Register Empty */
     643    DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), 
    596644} DMA_CH_TRIGSRC_t;
    597645
     
    600648{
    601649    DMA_DBUFMODE_DISABLED_gc = (0x00<<2),  /* Double buffering disabled */
    602     DMA_DBUFMODE_CH01_gc = (0x01<<2),  /* Double buffering enabled on channel 0/1 */
    603     DMA_DBUFMODE_CH23_gc = (0x02<<2),  /* Double buffering enabled on channel 2/3 */
    604     DMA_DBUFMODE_CH01CH23_gc = (0x03<<2),  /* Double buffering enabled on ch. 0/1 and ch. 2/3 */
     650    /* Double buffering enabled on channel 0/1 */
     651    DMA_DBUFMODE_CH01_gc = (0x01<<2), 
     652    /* Double buffering enabled on channel 2/3 */
     653    DMA_DBUFMODE_CH23_gc = (0x02<<2), 
     654    /* Double buffering enabled on ch. 0/1 and ch. 2/3 */
     655    DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), 
    605656} DMA_DBUFMODE_t;
    606657
     
    609660{
    610661    DMA_PRIMODE_RR0123_gc = (0x00<<0),  /* Round Robin */
    611     DMA_PRIMODE_CH0RR123_gc = (0x01<<0),  /* Channel 0 > Round Robin on channel 1/2/3 */
    612     DMA_PRIMODE_CH01RR23_gc = (0x02<<0),  /* Channel 0 > channel 1 > Round Robin on channel 2/3 */
    613     DMA_PRIMODE_CH0123_gc = (0x03<<0),  /* Channel 0 > channel 1 > channel 2 > channel 3 */
     662    /* Channel 0 > Round Robin on channel 1/2/3 */
     663    DMA_PRIMODE_CH0RR123_gc = (0x01<<0), 
     664    /* Channel 0 > channel 1 > Round Robin on channel 2/3 */
     665    DMA_PRIMODE_CH01RR23_gc = (0x02<<0), 
     666    /* Channel 0 > channel 1 > channel 2 > channel 3 */
     667    DMA_PRIMODE_CH0123_gc = (0x03<<0), 
    614668} DMA_PRIMODE_t;
    615669
     
    762816    EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),  /* Prescaler, divide by 256 */
    763817    EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),  /* Prescaler, divide by 512 */
    764     EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),  /* Prescaler, divide by 1024 */
    765     EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),  /* Prescaler, divide by 2048 */
    766     EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),  /* Prescaler, divide by 4096 */
    767     EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),  /* Prescaler, divide by 8192 */
    768     EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),  /* Prescaler, divide by 16384 */
    769     EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),  /* Prescaler, divide by 32768 */
     818    /* Prescaler, divide by 1024 */
     819    EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), 
     820    /* Prescaler, divide by 2048 */
     821    EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), 
     822    /* Prescaler, divide by 4096 */
     823    EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), 
     824    /* Prescaler, divide by 8192 */
     825    EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), 
     826    /* Prescaler, divide by 16384 */
     827    EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), 
     828    /* Prescaler, divide by 32768 */
     829    EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), 
    770830    EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),  /* Timer/Counter C0 Overflow */
    771831    EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),  /* Timer/Counter C0 Error */
    772     EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),  /* Timer/Counter C0 Compare or Capture A */
    773     EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),  /* Timer/Counter C0 Compare or Capture B */
    774     EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),  /* Timer/Counter C0 Compare or Capture C */
    775     EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),  /* Timer/Counter C0 Compare or Capture D */
     832    /* Timer/Counter C0 Compare or Capture A */
     833    EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), 
     834    /* Timer/Counter C0 Compare or Capture B */
     835    EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), 
     836    /* Timer/Counter C0 Compare or Capture C */
     837    EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), 
     838    /* Timer/Counter C0 Compare or Capture D */
     839    EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), 
    776840    EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),  /* Timer/Counter C1 Overflow */
    777841    EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),  /* Timer/Counter C1 Error */
    778     EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),  /* Timer/Counter C1 Compare or Capture A */
    779     EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),  /* Timer/Counter C1 Compare or Capture B */
     842    /* Timer/Counter C1 Compare or Capture A */
     843    EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), 
     844    /* Timer/Counter C1 Compare or Capture B */
     845    EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), 
    780846    EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),  /* Timer/Counter D0 Overflow */
    781847    EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),  /* Timer/Counter D0 Error */
    782     EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),  /* Timer/Counter D0 Compare or Capture A */
    783     EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),  /* Timer/Counter D0 Compare or Capture B */
    784     EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),  /* Timer/Counter D0 Compare or Capture C */
    785     EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),  /* Timer/Counter D0 Compare or Capture D */
     848    /* Timer/Counter D0 Compare or Capture A */
     849    EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), 
     850    /* Timer/Counter D0 Compare or Capture B */
     851    EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), 
     852    /* Timer/Counter D0 Compare or Capture C */
     853    EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), 
     854    /* Timer/Counter D0 Compare or Capture D */
     855    EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), 
    786856    EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),  /* Timer/Counter D1 Overflow */
    787857    EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),  /* Timer/Counter D1 Error */
    788     EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),  /* Timer/Counter D1 Compare or Capture A */
    789     EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),  /* Timer/Counter D1 Compare or Capture B */
     858    /* Timer/Counter D1 Compare or Capture A */
     859    EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), 
     860    /* Timer/Counter D1 Compare or Capture B */
     861    EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), 
    790862    EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),  /* Timer/Counter E0 Overflow */
    791863    EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),  /* Timer/Counter E0 Error */
    792     EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),  /* Timer/Counter E0 Compare or Capture A */
    793     EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),  /* Timer/Counter E0 Compare or Capture B */
    794     EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),  /* Timer/Counter E0 Compare or Capture C */
    795     EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),  /* Timer/Counter E0 Compare or Capture D */
     864    /* Timer/Counter E0 Compare or Capture A */
     865    EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), 
     866    /* Timer/Counter E0 Compare or Capture B */
     867    EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), 
     868    /* Timer/Counter E0 Compare or Capture C */
     869    EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), 
     870    /* Timer/Counter E0 Compare or Capture D */
     871    EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), 
    796872    EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),  /* Timer/Counter E1 Overflow */
    797873    EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),  /* Timer/Counter E1 Error */
    798     EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),  /* Timer/Counter E1 Compare or Capture A */
    799     EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),  /* Timer/Counter E1 Compare or Capture B */
     874    /* Timer/Counter E1 Compare or Capture A */
     875    EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), 
     876    /* Timer/Counter E1 Compare or Capture B */
     877    EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), 
    800878    EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),  /* Timer/Counter F0 Overflow */
    801879    EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),  /* Timer/Counter F0 Error */
    802     EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),  /* Timer/Counter F0 Compare or Capture A */
    803     EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),  /* Timer/Counter F0 Compare or Capture B */
    804     EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),  /* Timer/Counter F0 Compare or Capture C */
    805     EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),  /* Timer/Counter F0 Compare or Capture D */
     880    /* Timer/Counter F0 Compare or Capture A */
     881    EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), 
     882    /* Timer/Counter F0 Compare or Capture B */
     883    EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), 
     884    /* Timer/Counter F0 Compare or Capture C */
     885    EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), 
     886    /* Timer/Counter F0 Compare or Capture D */
     887    EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), 
    806888    EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),  /* Timer/Counter F1 Overflow */
    807889    EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),  /* Timer/Counter F1 Error */
    808     EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),  /* Timer/Counter F1 Compare or Capture A */
    809     EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),  /* Timer/Counter F1 Compare or Capture B */
     890    /* Timer/Counter F1 Compare or Capture A */
     891    EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), 
     892    /* Timer/Counter F1 Compare or Capture B */
     893    EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), 
    810894} EVSYS_CHMUX_t;
    811895
     
    9541038    NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),  /* Write user signature row */
    9551039    NVM_CMD_ERASE_APP_gc = (0x20<<0),  /* Erase Application Section */
    956     NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),  /* Erase Application Section page */
     1040    /* Erase Application Section page */
     1041    NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), 
    9571042    NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),  /* Load Flash page buffer */
    958     NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),  /* Write Application Section page */
    959     NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),  /* Erase-and-write Application Section page */
    960     NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),  /* Erase/flush Flash page buffer */
     1043    /* Write Application Section page */
     1044    NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), 
     1045    /* Erase-and-write Application Section page */
     1046    NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), 
     1047    /* Erase/flush Flash page buffer */
     1048    NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), 
    9611049    NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),  /* Erase Boot Section page */
    9621050    NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),  /* Write Boot Section page */
    963     NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),  /* Erase-and-write Boot Section page */
     1051    /* Erase-and-write Boot Section page */
     1052    NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), 
    9641053    NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),  /* Erase EEPROM */
    9651054    NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),  /* Erase EEPROM page */
    9661055    NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),  /* Load EEPROM page buffer */
    9671056    NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),  /* Write EEPROM page */
    968     NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),  /* Erase-and-write EEPROM page */
    969     NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),  /* Erase/flush EEPROM page buffer */
     1057    /* Erase-and-write EEPROM page */
     1058    NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), 
     1059    /* Erase/flush EEPROM page buffer */
     1060    NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), 
    9701061    NVM_CMD_APP_CRC_gc = (0x38<<0),  /* Generate Application section CRC */
    9711062    NVM_CMD_BOOT_CRC_gc = (0x39<<0),  /* Generate Boot Section CRC */
     
    12731364{
    12741365    ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),  /* Internal inputs, no gain */
    1275     ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),  /* Single-ended input, no gain */
     1366    /* Single-ended input, no gain */
     1367    ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), 
    12761368    ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),  /* Differential input, no gain */
    1277     ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),  /* Differential input, with gain */
     1369    /* Differential input, with gain */
     1370    ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), 
    12781371} ADC_CH_INPUTMODE_t;
    12791372
     
    12951388    ADC_RESOLUTION_12BIT_gc = (0x00<<1),  /* 12-bit right-adjusted result */
    12961389    ADC_RESOLUTION_8BIT_gc = (0x02<<1),  /* 8-bit right-adjusted result */
    1297     ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),  /* 12-bit left-adjusted result */
     1390    /* 12-bit left-adjusted result */
     1391    ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),
    12981392} ADC_RESOLUTION_t;
    12991393
     
    13351429    ADC_EVACT_CH0_gc = (0x01<<0),  /* First event triggers channel 0 */
    13361430    ADC_EVACT_CH01_gc = (0x02<<0),  /* First two events trigger channel 0,1 */
    1337     ADC_EVACT_CH012_gc = (0x03<<0),  /* First three events trigger channel 0,1,2 */
     1431    /* First three events trigger channel 0,1,2 */
     1432    ADC_EVACT_CH012_gc = (0x03<<0), 
    13381433    ADC_EVACT_CH0123_gc = (0x04<<0),  /* Events trigger channel 0,1,2,3 */
    13391434    ADC_EVACT_SWEEP_gc = (0x05<<0),  /* First event triggers sweep */
    1340     ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0),  /* First event triggers synchronized sweep */
     1435    /* First event triggers synchronized sweep */
     1436    ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), 
    13411437} ADC_EVACT_t;
    13421438
     
    13441440typedef enum ADC_CH_INTMODE_enum
    13451441{
    1346     ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),  /* Interrupt on conversion complete */
    1347     ADC_CH_INTMODE_BELOW_gc = (0x01<<2),  /* Interrupt on result below compare value */
    1348     ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),  /* Interrupt on result above compare value */
     1442    /* Interrupt on conversion complete */
     1443    ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), 
     1444    /* Interrupt on result below compare value */
     1445    ADC_CH_INTMODE_BELOW_gc = (0x01<<2), 
     1446    /* Interrupt on result above compare value */
     1447    ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),
    13491448} ADC_CH_INTMODE_t;
    13501449
     
    14211520typedef enum DAC_CHSEL_enum
    14221521{
    1423     DAC_CHSEL_SINGLE_gc = (0x00<<5),  /* Single channel operation (Channel A only) */
    1424     DAC_CHSEL_DUAL_gc = (0x02<<5),  /* Dual channel operation (S/H on both channels) */
     1522    /* Single channel operation (Channel A only) */
     1523    DAC_CHSEL_SINGLE_gc = (0x00<<5), 
     1524    /* Dual channel operation (S/H on both channels) */
     1525    DAC_CHSEL_DUAL_gc = (0x02<<5), 
    14251526} DAC_CHSEL_t;
    14261527
     
    14301531    DAC_REFSEL_INT1V_gc = (0x00<<3),  /* Internal 1V  */
    14311532    DAC_REFSEL_AVCC_gc = (0x01<<3),  /* Analog supply voltage */
    1432     DAC_REFSEL_AREFA_gc = (0x02<<3),  /* External reference on AREF on PORTA */
    1433     DAC_REFSEL_AREFB_gc = (0x03<<3),  /* External reference on AREF on PORTB */
     1533    /* External reference on AREF on PORTA */
     1534    DAC_REFSEL_AREFA_gc = (0x02<<3), 
     1535    /* External reference on AREF on PORTB */
     1536    DAC_REFSEL_AREFB_gc = (0x03<<3), 
    14341537} DAC_REFSEL_t;
    14351538
     
    18111914{
    18121915    TWI_MASTER_CMD_NOACT_gc = (0x00<<0),  /* No Action */
    1813     TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),  /* Issue Repeated Start Condition */
     1916    /* Issue Repeated Start Condition */
     1917    TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), 
    18141918    TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),  /* Receive or Transmit Data */
    18151919    TWI_MASTER_CMD_STOP_gc = (0x03<<0),  /* Issue Stop Condition */
     
    18211925    TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),  /* Unknown Bus State */
    18221926    TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),  /* Bus is Idle */
    1823     TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),  /* This Module Controls The Bus */
     1927    /* This Module Controls The Bus */
     1928    TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), 
    18241929    TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),  /* The Bus is Busy */
    18251930} TWI_MASTER_BUSSTATE_t;
     
    18381943{
    18391944    TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),  /* No Action */
    1840     TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),  /* Used To Complete a Transaction */
    1841     TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),  /* Used in Response to Address/Data Interrupt */
     1945    /* Used To Complete a Transaction */
     1946    TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), 
     1947    /* Used in Response to Address/Data Interrupt */
     1948    TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),
    18421949} TWI_SLAVE_CMD_t;
    18431950
     
    20062113{
    20072114    PORTCFG_EVOUT_OFF_gc = (0x00<<4),  /* Event Output Disabled */
    2008     PORTCFG_EVOUT_PC7_gc = (0x01<<4),  /* Event Channel 7 Output on Port C pin 7 */
    2009     PORTCFG_EVOUT_PD7_gc = (0x02<<4),  /* Event Channel 7 Output on Port D pin 7 */
    2010     PORTCFG_EVOUT_PE7_gc = (0x03<<4),  /* Event Channel 7 Output on Port E pin 7 */
     2115    /* Event Channel 7 Output on Port C pin 7 */
     2116    PORTCFG_EVOUT_PC7_gc = (0x01<<4), 
     2117    /* Event Channel 7 Output on Port D pin 7 */
     2118    PORTCFG_EVOUT_PD7_gc = (0x02<<4), 
     2119    /* Event Channel 7 Output on Port E pin 7 */
     2120    PORTCFG_EVOUT_PE7_gc = (0x03<<4), 
    20112121} PORTCFG_EVOUT_t;
    20122122
     
    20332143{
    20342144    PORT_OPC_TOTEM_gc = (0x00<<3),  /* Totempole */
    2035     PORT_OPC_BUSKEEPER_gc = (0x01<<3),  /* Totempole w/ Bus keeper on Input and Output */
     2145    /* Totempole w/ Bus keeper on Input and Output */
     2146    PORT_OPC_BUSKEEPER_gc = (0x01<<3), 
    20362147    PORT_OPC_PULLDOWN_gc = (0x02<<3),  /* Totempole w/ Pull-down on Input */
    20372148    PORT_OPC_PULLUP_gc = (0x03<<3),  /* Totempole w/ Pull-up on Input */
     
    22452356    TC_WGMODE_SS_gc = (0x03<<0),  /* Single Slope */
    22462357    TC_WGMODE_DS_T_gc = (0x05<<0),  /* Dual Slope, Update on TOP */
    2247     TC_WGMODE_DS_TB_gc = (0x06<<0),  /* Dual Slope, Update on TOP and BOTTOM */
     2358    /* Dual Slope, Update on TOP and BOTTOM */
     2359    TC_WGMODE_DS_TB_gc = (0x06<<0), 
    22482360    TC_WGMODE_DS_B_gc = (0x07<<0),  /* Dual Slope, Update on BOTTOM */
    22492361} TC_WGMODE_t;
     
    23502462{
    23512463    HIRES_HREN_NONE_gc = (0x00<<0),  /* No Fault Protection */
    2352     HIRES_HREN_TC0_gc = (0x01<<0),  /* Enable High Resolution on Timer/Counter 0 */
    2353     HIRES_HREN_TC1_gc = (0x02<<0),  /* Enable High Resolution on Timer/Counter 1 */
    2354     HIRES_HREN_BOTH_gc = (0x03<<0),  /* Enable High Resolution both Timer/Counters */
     2464    /* Enable High Resolution on Timer/Counter 0 */
     2465    HIRES_HREN_TC0_gc = (0x01<<0), 
     2466    /* Enable High Resolution on Timer/Counter 1 */
     2467    HIRES_HREN_TC1_gc = (0x02<<0), 
     2468    /* Enable High Resolution both Timer/Counters */
     2469    HIRES_HREN_BOTH_gc = (0x03<<0), 
    23552470} HIRES_HREN_t;
    23562471
     
    24832598{
    24842599    register8_t CTRL;  /* Control Register */
    2485     register8_t TXPLCTRL;  /* IrDA Transmitter Pulse Length Control Register */
     2600    /* IrDA Transmitter Pulse Length Control Register */
     2601    register8_t TXPLCTRL; 
    24862602    register8_t RXPLCTRL;  /* IrDA Receiver Pulse Length Control Register */
    24872603} IRCOM_t;
     
    25262642    AES_INTLVL_HI_gc = (0x03<<0),  /* High Level */
    25272643} AES_INTLVL_t;
    2528 
    2529 
    2530 
    2531 /*
    2532 ==========================================================================
    2533 IO Module Instances. Mapped to memory.
    2534 ==========================================================================
    2535 */
    2536 
     2644/** @} */
     2645
     2646/**
     2647 * @name IO Module Instances. Mapped to Memory
     2648 *
     2649 * @{
     2650 */
    25372651#define GPIO    (*(GPIO_t *) 0x0000)  /* General Purpose IO Registers */
    25382652#define VPORT0    (*(VPORT_t *) 0x0010)  /* Virtual Port 0 */
     
    25842698#define AWEXC    (*(AWEX_t *) 0x0880)  /* Advanced Waveform Extension C */
    25852699#define HIRESC    (*(HIRES_t *) 0x0890)  /* High-Resolution Extension C */
    2586 #define USARTC0    (*(USART_t *) 0x08A0)  /* Universal Asynchronous Receiver-Transmitter C0 */
    2587 #define USARTC1    (*(USART_t *) 0x08B0)  /* Universal Asynchronous Receiver-Transmitter C1 */
     2700/* Universal Asynchronous Receiver-Transmitter C0 */
     2701#define USARTC0    (*(USART_t *) 0x08A0) 
     2702/* Universal Asynchronous Receiver-Transmitter C1 */
     2703#define USARTC1    (*(USART_t *) 0x08B0) 
    25882704#define SPIC    (*(SPI_t *) 0x08C0)  /* Serial Peripheral Interface C */
    25892705#define IRCOM    (*(IRCOM_t *) 0x08F8)  /* IR Communication Module */
     
    25912707#define TCD1    (*(TC1_t *) 0x0940)  /* Timer/Counter D1 */
    25922708#define HIRESD    (*(HIRES_t *) 0x0990)  /* High-Resolution Extension D */
    2593 #define USARTD0    (*(USART_t *) 0x09A0)  /* Universal Asynchronous Receiver-Transmitter D0 */
    2594 #define USARTD1    (*(USART_t *) 0x09B0)  /* Universal Asynchronous Receiver-Transmitter D1 */
     2709/* Universal Asynchronous Receiver-Transmitter D0 */
     2710#define USARTD0    (*(USART_t *) 0x09A0) 
     2711/* Universal Asynchronous Receiver-Transmitter D1 */
     2712#define USARTD1    (*(USART_t *) 0x09B0) 
    25952713#define SPID    (*(SPI_t *) 0x09C0)  /* Serial Peripheral Interface D */
    25962714#define TCE0    (*(TC0_t *) 0x0A00)  /* Timer/Counter E0 */
     
    25982716#define AWEXE    (*(AWEX_t *) 0x0A80)  /* Advanced Waveform Extension E */
    25992717#define HIRESE    (*(HIRES_t *) 0x0A90)  /* High-Resolution Extension E */
    2600 #define USARTE0    (*(USART_t *) 0x0AA0)  /* Universal Asynchronous Receiver-Transmitter E0 */
    2601 #define USARTE1    (*(USART_t *) 0x0AB0)  /* Universal Asynchronous Receiver-Transmitter E1 */
     2718/* Universal Asynchronous Receiver-Transmitter E0 */
     2719#define USARTE0    (*(USART_t *) 0x0AA0) 
     2720/* Universal Asynchronous Receiver-Transmitter E1 */
     2721#define USARTE1    (*(USART_t *) 0x0AB0) 
    26022722#define SPIE    (*(SPI_t *) 0x0AC0)  /* Serial Peripheral Interface E */
    26032723#define TCF0    (*(TC0_t *) 0x0B00)  /* Timer/Counter F0 */
    26042724#define TCF1    (*(TC1_t *) 0x0B40)  /* Timer/Counter F1 */
    26052725#define HIRESF    (*(HIRES_t *) 0x0B90)  /* High-Resolution Extension F */
    2606 #define USARTF0    (*(USART_t *) 0x0BA0)  /* Universal Asynchronous Receiver-Transmitter F0 */
    2607 #define USARTF1    (*(USART_t *) 0x0BB0)  /* Universal Asynchronous Receiver-Transmitter F1 */
     2726/* Universal Asynchronous Receiver-Transmitter F0 */
     2727#define USARTF0    (*(USART_t *) 0x0BA0) 
     2728/* Universal Asynchronous Receiver-Transmitter F1 */
     2729#define USARTF1    (*(USART_t *) 0x0BB0) 
    26082730#define SPIF    (*(SPI_t *) 0x0BC0)  /* Serial Peripheral Interface F */
    26092731
    26102732
    26112733#endif /* !defined (__ASSEMBLER__) */
    2612 
    2613 
    2614 /* ========== Flattened fully qualified IO register names ========== */
     2734/** @} */
     2735
     2736/**
     2737 * @name Flattened Fully Qualified IO Register Names
     2738 *
     2739 * @{
     2740 */
    26152741
    26162742/* GPIO - General Purpose IO Registers */
     
    36303756#define SPIF_STATUS  _SFR_MEM8(0x0BC2)
    36313757#define SPIF_DATA  _SFR_MEM8(0x0BC3)
    3632 
    3633 
    3634 
    3635 /*================== Bitfield Definitions ================== */
    3636 
     3758/** @} */
     3759
     3760/**
     3761 * @name Bitfield Definitions
     3762 *
     3763 * @{
     3764 */
    36373765/* XOCD - On-Chip Debug System */
    36383766/* OCD.OCDR1  bit masks and bit positions */
     
    37153843#define CLK_PSADIV4_bp  6  /* Prescaler A Division Factor bit 4 position. */
    37163844
    3717 #define CLK_PSBCDIV_gm  0x03  /* Prescaler B and C Division factor group mask. */
    3718 #define CLK_PSBCDIV_gp  0  /* Prescaler B and C Division factor group position. */
    3719 #define CLK_PSBCDIV0_bm  (1<<0)  /* Prescaler B and C Division factor bit 0 mask. */
    3720 #define CLK_PSBCDIV0_bp  0  /* Prescaler B and C Division factor bit 0 position. */
    3721 #define CLK_PSBCDIV1_bm  (1<<1)  /* Prescaler B and C Division factor bit 1 mask. */
    3722 #define CLK_PSBCDIV1_bp  1  /* Prescaler B and C Division factor bit 1 position. */
     3845/* Prescaler B and C Division factor group mask. */
     3846#define CLK_PSBCDIV_gm  0x03 
     3847/* Prescaler B and C Division factor group position. */
     3848#define CLK_PSBCDIV_gp  0 
     3849/* Prescaler B and C Division factor bit 0 mask. */
     3850#define CLK_PSBCDIV0_bm  (1<<0) 
     3851/* Prescaler B and C Division factor bit 0 position. */
     3852#define CLK_PSBCDIV0_bp  0 
     3853/* Prescaler B and C Division factor bit 1 mask. */
     3854#define CLK_PSBCDIV1_bm  (1<<1)
     3855/* Prescaler B and C Division factor bit 1 position. */
     3856#define CLK_PSBCDIV1_bp  1 
    37233857
    37243858
     
    38964030#define OSC_XOSCEN_bp  3  /* External Oscillator Enable bit position. */
    38974031
    3898 #define OSC_RC32KEN_bm  0x04  /* Internal 32kHz RC Oscillator Enable bit mask. */
    3899 #define OSC_RC32KEN_bp  2  /* Internal 32kHz RC Oscillator Enable bit position. */
    3900 
    3901 #define OSC_RC32MEN_bm  0x02  /* Internal 32MHz RC Oscillator Enable bit mask. */
    3902 #define OSC_RC32MEN_bp  1  /* Internal 32MHz RC Oscillator Enable bit position. */
    3903 
    3904 #define OSC_RC2MEN_bm  0x01  /* Internal 2MHz RC Oscillator Enable bit mask. */
    3905 #define OSC_RC2MEN_bp  0  /* Internal 2MHz RC Oscillator Enable bit position. */
     4032/* Internal 32kHz RC Oscillator Enable bit mask. */
     4033#define OSC_RC32KEN_bm  0x04
     4034/* Internal 32kHz RC Oscillator Enable bit position. */
     4035#define OSC_RC32KEN_bp  2 
     4036
     4037/* Internal 32MHz RC Oscillator Enable bit mask. */
     4038#define OSC_RC32MEN_bm  0x02 
     4039/* Internal 32MHz RC Oscillator Enable bit position. */
     4040#define OSC_RC32MEN_bp  1 
     4041
     4042/* Internal 2MHz RC Oscillator Enable bit mask. */
     4043#define OSC_RC2MEN_bm  0x01 
     4044/* Internal 2MHz RC Oscillator Enable bit position. */
     4045#define OSC_RC2MEN_bp  0 
    39064046
    39074047
     
    39134053#define OSC_XOSCRDY_bp  3  /* External Oscillator Ready bit position. */
    39144054
    3915 #define OSC_RC32KRDY_bm  0x04  /* Internal 32kHz RC Oscillator Ready bit mask. */
    3916 #define OSC_RC32KRDY_bp  2  /* Internal 32kHz RC Oscillator Ready bit position. */
    3917 
    3918 #define OSC_RC32MRDY_bm  0x02  /* Internal 32MHz RC Oscillator Ready bit mask. */
    3919 #define OSC_RC32MRDY_bp  1  /* Internal 32MHz RC Oscillator Ready bit position. */
    3920 
    3921 #define OSC_RC2MRDY_bm  0x01  /* Internal 2MHz RC Oscillator Ready bit mask. */
    3922 #define OSC_RC2MRDY_bp  0  /* Internal 2MHz RC Oscillator Ready bit position. */
     4055/* Internal 32kHz RC Oscillator Ready bit mask. */
     4056#define OSC_RC32KRDY_bm  0x04
     4057/* Internal 32kHz RC Oscillator Ready bit position. */
     4058#define OSC_RC32KRDY_bp  2 
     4059
     4060/* Internal 32MHz RC Oscillator Ready bit mask. */
     4061#define OSC_RC32MRDY_bm  0x02
     4062/* Internal 32MHz RC Oscillator Ready bit position. */
     4063#define OSC_RC32MRDY_bp  1 
     4064
     4065/* Internal 2MHz RC Oscillator Ready bit mask. */
     4066#define OSC_RC2MRDY_bm  0x01 
     4067/* Internal 2MHz RC Oscillator Ready bit position. */
     4068#define OSC_RC2MRDY_bp  0 
    39234069
    39244070
     
    39344080#define OSC_X32KLPM_bp  5  /* 32kHz XTAL OSC Low-power Mode bit position. */
    39354081
    3936 #define OSC_XOSCSEL_gm  0x0F  /* External Oscillator Selection and Startup Time group mask. */
    3937 #define OSC_XOSCSEL_gp  0  /* External Oscillator Selection and Startup Time group position. */
    3938 #define OSC_XOSCSEL0_bm  (1<<0)  /* External Oscillator Selection and Startup Time bit 0 mask. */
    3939 #define OSC_XOSCSEL0_bp  0  /* External Oscillator Selection and Startup Time bit 0 position. */
    3940 #define OSC_XOSCSEL1_bm  (1<<1)  /* External Oscillator Selection and Startup Time bit 1 mask. */
    3941 #define OSC_XOSCSEL1_bp  1  /* External Oscillator Selection and Startup Time bit 1 position. */
    3942 #define OSC_XOSCSEL2_bm  (1<<2)  /* External Oscillator Selection and Startup Time bit 2 mask. */
    3943 #define OSC_XOSCSEL2_bp  2  /* External Oscillator Selection and Startup Time bit 2 position. */
    3944 #define OSC_XOSCSEL3_bm  (1<<3)  /* External Oscillator Selection and Startup Time bit 3 mask. */
    3945 #define OSC_XOSCSEL3_bp  3  /* External Oscillator Selection and Startup Time bit 3 position. */
     4082/* External Oscillator Selection and Startup Time group mask. */
     4083#define OSC_XOSCSEL_gm  0x0F 
     4084/* External Oscillator Selection and Startup Time group position. */
     4085#define OSC_XOSCSEL_gp  0
     4086/* External Oscillator Selection and Startup Time bit 0 mask. */
     4087#define OSC_XOSCSEL0_bm  (1<<0)
     4088/* External Oscillator Selection and Startup Time bit 0 position. */
     4089#define OSC_XOSCSEL0_bp  0 
     4090/* External Oscillator Selection and Startup Time bit 1 mask. */
     4091#define OSC_XOSCSEL1_bm  (1<<1) 
     4092/* External Oscillator Selection and Startup Time bit 1 position. */
     4093#define OSC_XOSCSEL1_bp  1
     4094/* External Oscillator Selection and Startup Time bit 2 mask. */
     4095#define OSC_XOSCSEL2_bm  (1<<2) 
     4096/* External Oscillator Selection and Startup Time bit 2 position. */
     4097#define OSC_XOSCSEL2_bp  2 
     4098/* External Oscillator Selection and Startup Time bit 3 mask. */
     4099#define OSC_XOSCSEL3_bm  (1<<3) 
     4100/* External Oscillator Selection and Startup Time bit 3 position. */
     4101#define OSC_XOSCSEL3_bp  3 
    39464102
    39474103
    39484104/* OSC.XOSCFAIL  bit masks and bit positions */
    3949 #define OSC_XOSCFDIF_bm  0x02  /* Failure Detection Interrupt Flag bit mask. */
    3950 #define OSC_XOSCFDIF_bp  1  /* Failure Detection Interrupt Flag bit position. */
     4105/* Failure Detection Interrupt Flag bit mask. */
     4106#define OSC_XOSCFDIF_bm  0x02 
     4107/* Failure Detection Interrupt Flag bit position. */
     4108#define OSC_XOSCFDIF_bp  1 
    39514109
    39524110#define OSC_XOSCFDEN_bm  0x01  /* Failure Detection Enable bit mask. */
     
    40344192#define RST_SRF_bp  5  /* Software Reset Flag bit position. */
    40354193
    4036 #define RST_PDIRF_bm  0x10  /* Programming and Debug Interface Interface Reset Flag bit mask. */
    4037 #define RST_PDIRF_bp  4  /* Programming and Debug Interface Interface Reset Flag bit position. */
     4194/* Programming and Debug Interface Interface Reset Flag bit mask. */
     4195#define RST_PDIRF_bm  0x10 
     4196/* Programming and Debug Interface Interface Reset Flag bit position. */
     4197#define RST_PDIRF_bp  4 
    40384198
    40394199#define RST_WDRF_bm  0x08  /* Watchdog Reset Flag bit mask. */
     
    41294289#define PMIC_HILVLEX_bp  2  /* High Level Interrupt Executing bit position. */
    41304290
    4131 #define PMIC_MEDLVLEX_bm  0x02  /* Medium Level Interrupt Executing bit mask. */
    4132 #define PMIC_MEDLVLEX_bp  1  /* Medium Level Interrupt Executing bit position. */
     4291/* Medium Level Interrupt Executing bit mask. */
     4292#define PMIC_MEDLVLEX_bm  0x02 
     4293/* Medium Level Interrupt Executing bit position. */
     4294#define PMIC_MEDLVLEX_bp  1
    41334295
    41344296#define PMIC_LOLVLEX_bm  0x01  /* Low Level Interrupt Executing bit mask. */
     
    41674329#define DMA_CH_TRFREQ_bp  4  /* Channel Transfer Request bit position. */
    41684330
    4169 #define DMA_CH_SINGLE_bm  0x04  /* Channel Single Shot Data Transfer bit mask. */
    4170 #define DMA_CH_SINGLE_bp  2  /* Channel Single Shot Data Transfer bit position. */
     4331/* Channel Single Shot Data Transfer bit mask. */
     4332#define DMA_CH_SINGLE_bm  0x04 
     4333/* Channel Single Shot Data Transfer bit position. */
     4334#define DMA_CH_SINGLE_bp  2 
    41714335
    41724336#define DMA_CH_BURSTLEN_gm  0x03  /* Channel Transfer Mode group mask. */
     
    41854349#define DMA_CH_CHPEND_bp  6  /* Block Transfer Pending bit position. */
    41864350
    4187 #define DMA_CH_ERRIF_bm  0x20  /* Block Transfer Error Interrupt Flag bit mask. */
    4188 #define DMA_CH_ERRIF_bp  5  /* Block Transfer Error Interrupt Flag bit position. */
    4189 
    4190 #define DMA_CH_TRNIF_bm  0x10  /* Transaction Complete Interrup Flag bit mask. */
    4191 #define DMA_CH_TRNIF_bp  4  /* Transaction Complete Interrup Flag bit position. */
    4192 
    4193 #define DMA_CH_ERRINTLVL_gm  0x0C  /* Transfer Error Interrupt Level group mask. */
    4194 #define DMA_CH_ERRINTLVL_gp  2  /* Transfer Error Interrupt Level group position. */
    4195 #define DMA_CH_ERRINTLVL0_bm  (1<<2)  /* Transfer Error Interrupt Level bit 0 mask. */
    4196 #define DMA_CH_ERRINTLVL0_bp  2  /* Transfer Error Interrupt Level bit 0 position. */
    4197 #define DMA_CH_ERRINTLVL1_bm  (1<<3)  /* Transfer Error Interrupt Level bit 1 mask. */
    4198 #define DMA_CH_ERRINTLVL1_bp  3  /* Transfer Error Interrupt Level bit 1 position. */
    4199 
    4200 #define DMA_CH_TRNINTLVL_gm  0x03  /* Transaction Complete Interrupt Level group mask. */
    4201 #define DMA_CH_TRNINTLVL_gp  0  /* Transaction Complete Interrupt Level group position. */
    4202 #define DMA_CH_TRNINTLVL0_bm  (1<<0)  /* Transaction Complete Interrupt Level bit 0 mask. */
    4203 #define DMA_CH_TRNINTLVL0_bp  0  /* Transaction Complete Interrupt Level bit 0 position. */
    4204 #define DMA_CH_TRNINTLVL1_bm  (1<<1)  /* Transaction Complete Interrupt Level bit 1 mask. */
    4205 #define DMA_CH_TRNINTLVL1_bp  1  /* Transaction Complete Interrupt Level bit 1 position. */
     4351/* Block Transfer Error Interrupt Flag bit mask. */
     4352#define DMA_CH_ERRIF_bm  0x20 
     4353/* Block Transfer Error Interrupt Flag bit position. */
     4354#define DMA_CH_ERRIF_bp  5 
     4355
     4356/* Transaction Complete Interrup Flag bit mask. */
     4357#define DMA_CH_TRNIF_bm  0x10 
     4358/* Transaction Complete Interrup Flag bit position. */
     4359#define DMA_CH_TRNIF_bp  4 
     4360
     4361/* Transfer Error Interrupt Level group mask. */
     4362#define DMA_CH_ERRINTLVL_gm  0x0C 
     4363/* Transfer Error Interrupt Level group position. */
     4364#define DMA_CH_ERRINTLVL_gp  2 
     4365/* Transfer Error Interrupt Level bit 0 mask. */
     4366#define DMA_CH_ERRINTLVL0_bm  (1<<2) 
     4367/* Transfer Error Interrupt Level bit 0 position. */
     4368#define DMA_CH_ERRINTLVL0_bp  2 
     4369/* Transfer Error Interrupt Level bit 1 mask. */
     4370#define DMA_CH_ERRINTLVL1_bm  (1<<3) 
     4371 /* Transfer Error Interrupt Level bit 1 position. */
     4372#define DMA_CH_ERRINTLVL1_bp  3
     4373
     4374/* Transaction Complete Interrupt Level group mask. */
     4375#define DMA_CH_TRNINTLVL_gm  0x03 
     4376/* Transaction Complete Interrupt Level group position. */
     4377#define DMA_CH_TRNINTLVL_gp  0 
     4378/* Transaction Complete Interrupt Level bit 0 mask. */
     4379#define DMA_CH_TRNINTLVL0_bm  (1<<0) 
     4380/* Transaction Complete Interrupt Level bit 0 position. */
     4381#define DMA_CH_TRNINTLVL0_bp  0 
     4382/* Transaction Complete Interrupt Level bit 1 mask. */
     4383#define DMA_CH_TRNINTLVL1_bm  (1<<1) 
     4384/* Transaction Complete Interrupt Level bit 1 position. */
     4385#define DMA_CH_TRNINTLVL1_bp  1 
    42064386
    42074387
    42084388/* DMA_CH.ADDRCTRL  bit masks and bit positions */
    4209 #define DMA_CH_SRCRELOAD_gm  0xC0  /* Channel Source Address Reload group mask. */
    4210 #define DMA_CH_SRCRELOAD_gp  6  /* Channel Source Address Reload group position. */
    4211 #define DMA_CH_SRCRELOAD0_bm  (1<<6)  /* Channel Source Address Reload bit 0 mask. */
    4212 #define DMA_CH_SRCRELOAD0_bp  6  /* Channel Source Address Reload bit 0 position. */
    4213 #define DMA_CH_SRCRELOAD1_bm  (1<<7)  /* Channel Source Address Reload bit 1 mask. */
    4214 #define DMA_CH_SRCRELOAD1_bp  7  /* Channel Source Address Reload bit 1 position. */
     4389/* Channel Source Address Reload group mask. */
     4390#define DMA_CH_SRCRELOAD_gm  0xC0 
     4391/* Channel Source Address Reload group position. */
     4392#define DMA_CH_SRCRELOAD_gp  6 
     4393/* Channel Source Address Reload bit 0 mask. */
     4394#define DMA_CH_SRCRELOAD0_bm  (1<<6) 
     4395/* Channel Source Address Reload bit 0 position. */
     4396#define DMA_CH_SRCRELOAD0_bp  6 
     4397/* Channel Source Address Reload bit 1 mask. */
     4398#define DMA_CH_SRCRELOAD1_bm  (1<<7) 
     4399/* Channel Source Address Reload bit 1 position. */
     4400#define DMA_CH_SRCRELOAD1_bp  7 
    42154401
    42164402#define DMA_CH_SRCDIR_gm  0x30  /* Channel Source Address Mode group mask. */
    42174403#define DMA_CH_SRCDIR_gp  4  /* Channel Source Address Mode group position. */
    4218 #define DMA_CH_SRCDIR0_bm  (1<<4)  /* Channel Source Address Mode bit 0 mask. */
    4219 #define DMA_CH_SRCDIR0_bp  4  /* Channel Source Address Mode bit 0 position. */
    4220 #define DMA_CH_SRCDIR1_bm  (1<<5)  /* Channel Source Address Mode bit 1 mask. */
    4221 #define DMA_CH_SRCDIR1_bp  5  /* Channel Source Address Mode bit 1 position. */
    4222 
    4223 #define DMA_CH_DESTRELOAD_gm  0x0C  /* Channel Destination Address Reload group mask. */
    4224 #define DMA_CH_DESTRELOAD_gp  2  /* Channel Destination Address Reload group position. */
    4225 #define DMA_CH_DESTRELOAD0_bm  (1<<2)  /* Channel Destination Address Reload bit 0 mask. */
    4226 #define DMA_CH_DESTRELOAD0_bp  2  /* Channel Destination Address Reload bit 0 position. */
    4227 #define DMA_CH_DESTRELOAD1_bm  (1<<3)  /* Channel Destination Address Reload bit 1 mask. */
    4228 #define DMA_CH_DESTRELOAD1_bp  3  /* Channel Destination Address Reload bit 1 position. */
    4229 
    4230 #define DMA_CH_DESTDIR_gm  0x03  /* Channel Destination Address Mode group mask. */
    4231 #define DMA_CH_DESTDIR_gp  0  /* Channel Destination Address Mode group position. */
    4232 #define DMA_CH_DESTDIR0_bm  (1<<0)  /* Channel Destination Address Mode bit 0 mask. */
    4233 #define DMA_CH_DESTDIR0_bp  0  /* Channel Destination Address Mode bit 0 position. */
    4234 #define DMA_CH_DESTDIR1_bm  (1<<1)  /* Channel Destination Address Mode bit 1 mask. */
    4235 #define DMA_CH_DESTDIR1_bp  1  /* Channel Destination Address Mode bit 1 position. */
     4404/* Channel Source Address Mode bit 0 mask. */
     4405#define DMA_CH_SRCDIR0_bm  (1<<4) 
     4406/* Channel Source Address Mode bit 0 position. */
     4407#define DMA_CH_SRCDIR0_bp  4 
     4408/* Channel Source Address Mode bit 1 mask. */
     4409#define DMA_CH_SRCDIR1_bm  (1<<5) 
     4410/* Channel Source Address Mode bit 1 position. */
     4411#define DMA_CH_SRCDIR1_bp  5 
     4412
     4413/* Channel Destination Address Reload group mask. */
     4414#define DMA_CH_DESTRELOAD_gm  0x0C 
     4415/* Channel Destination Address Reload group position. */
     4416#define DMA_CH_DESTRELOAD_gp  2 
     4417/* Channel Destination Address Reload bit 0 mask. */
     4418#define DMA_CH_DESTRELOAD0_bm  (1<<2) 
     4419/* Channel Destination Address Reload bit 0 position. */
     4420#define DMA_CH_DESTRELOAD0_bp  2 
     4421/* Channel Destination Address Reload bit 1 mask. */
     4422#define DMA_CH_DESTRELOAD1_bm  (1<<3) 
     4423/* Channel Destination Address Reload bit 1 position. */
     4424#define DMA_CH_DESTRELOAD1_bp  3 
     4425
     4426/* Channel Destination Address Mode group mask. */
     4427#define DMA_CH_DESTDIR_gm  0x03 
     4428/* Channel Destination Address Mode group position. */
     4429#define DMA_CH_DESTDIR_gp  0 
     4430/* Channel Destination Address Mode bit 0 mask. */
     4431#define DMA_CH_DESTDIR0_bm  (1<<0) 
     4432/* Channel Destination Address Mode bit 0 position. */
     4433#define DMA_CH_DESTDIR0_bp  0 
     4434/* Channel Destination Address Mode bit 1 mask. */
     4435#define DMA_CH_DESTDIR1_bm  (1<<1) 
     4436/* Channel Destination Address Mode bit 1 position. */
     4437#define DMA_CH_DESTDIR1_bp  1 
    42364438
    42374439
     
    42804482
    42814483/* DMA.INTFLAGS  bit masks and bit positions */
    4282 #define DMA_CH3ERRIF_bm  0x80  /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */
    4283 #define DMA_CH3ERRIF_bp  7  /* Channel 3 Block Transfer Error Interrupt Flag bit position. */
    4284 
    4285 #define DMA_CH2ERRIF_bm  0x40  /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */
    4286 #define DMA_CH2ERRIF_bp  6  /* Channel 2 Block Transfer Error Interrupt Flag bit position. */
    4287 
    4288 #define DMA_CH1ERRIF_bm  0x20  /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */
    4289 #define DMA_CH1ERRIF_bp  5  /* Channel 1 Block Transfer Error Interrupt Flag bit position. */
    4290 
    4291 #define DMA_CH0ERRIF_bm  0x10  /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */
    4292 #define DMA_CH0ERRIF_bp  4  /* Channel 0 Block Transfer Error Interrupt Flag bit position. */
    4293 
    4294 #define DMA_CH3TRNIF_bm  0x08  /* Channel 3 Transaction Complete Interrupt Flag bit mask. */
    4295 #define DMA_CH3TRNIF_bp  3  /* Channel 3 Transaction Complete Interrupt Flag bit position. */
    4296 
    4297 #define DMA_CH2TRNIF_bm  0x04  /* Channel 2 Transaction Complete Interrupt Flag bit mask. */
    4298 #define DMA_CH2TRNIF_bp  2  /* Channel 2 Transaction Complete Interrupt Flag bit position. */
    4299 
    4300 #define DMA_CH1TRNIF_bm  0x02  /* Channel 1 Transaction Complete Interrupt Flag bit mask. */
    4301 #define DMA_CH1TRNIF_bp  1  /* Channel 1 Transaction Complete Interrupt Flag bit position. */
    4302 
    4303 #define DMA_CH0TRNIF_bm  0x01  /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
    4304 #define DMA_CH0TRNIF_bp  0  /* Channel 0 Transaction Complete Interrupt Flag bit position. */
     4484/* Channel 3 Block Transfer Error Interrupt Flag bit mask. */
     4485#define DMA_CH3ERRIF_bm  0x80 
     4486/* Channel 3 Block Transfer Error Interrupt Flag bit position. */
     4487#define DMA_CH3ERRIF_bp  7 
     4488
     4489/* Channel 2 Block Transfer Error Interrupt Flag bit mask. */
     4490#define DMA_CH2ERRIF_bm  0x40 
     4491/* Channel 2 Block Transfer Error Interrupt Flag bit position. */
     4492#define DMA_CH2ERRIF_bp  6 
     4493
     4494/* Channel 1 Block Transfer Error Interrupt Flag bit mask. */
     4495#define DMA_CH1ERRIF_bm  0x20 
     4496/* Channel 1 Block Transfer Error Interrupt Flag bit position. */
     4497#define DMA_CH1ERRIF_bp  5 
     4498
     4499/* Channel 0 Block Transfer Error Interrupt Flag bit mask. */
     4500#define DMA_CH0ERRIF_bm  0x10 
     4501/* Channel 0 Block Transfer Error Interrupt Flag bit position. */
     4502#define DMA_CH0ERRIF_bp  4 
     4503
     4504/* Channel 3 Transaction Complete Interrupt Flag bit mask. */
     4505#define DMA_CH3TRNIF_bm  0x08 
     4506/* Channel 3 Transaction Complete Interrupt Flag bit position. */
     4507#define DMA_CH3TRNIF_bp  3 
     4508
     4509/* Channel 2 Transaction Complete Interrupt Flag bit mask. */
     4510#define DMA_CH2TRNIF_bm  0x04 
     4511/* Channel 2 Transaction Complete Interrupt Flag bit position. */
     4512#define DMA_CH2TRNIF_bp  2 
     4513
     4514/* Channel 1 Transaction Complete Interrupt Flag bit mask. */
     4515#define DMA_CH1TRNIF_bm  0x02 
     4516/* Channel 1 Transaction Complete Interrupt Flag bit position. */
     4517#define DMA_CH1TRNIF_bp  1
     4518
     4519/* Channel 0 Transaction Complete Interrupt Flag bit mask. */
     4520#define DMA_CH0TRNIF_bm  0x01 
     4521/* Channel 0 Transaction Complete Interrupt Flag bit position. */
     4522#define DMA_CH0TRNIF_bp  0 
    43054523
    43064524
     
    43194537
    43204538#define DMA_CH3PEND_bm  0x08  /* Channel 3 Block Transfer Pending bit mask. */
    4321 #define DMA_CH3PEND_bp  3  /* Channel 3 Block Transfer Pending bit position. */
     4539/* Channel 3 Block Transfer Pending bit position. */
     4540#define DMA_CH3PEND_bp  3 
    43224541
    43234542#define DMA_CH2PEND_bm  0x04  /* Channel 2 Block Transfer Pending bit mask. */
    4324 #define DMA_CH2PEND_bp  2  /* Channel 2 Block Transfer Pending bit position. */
     4543/* Channel 2 Block Transfer Pending bit position. */
     4544#define DMA_CH2PEND_bp  2 
    43254545
    43264546#define DMA_CH1PEND_bm  0x02  /* Channel 1 Block Transfer Pending bit mask. */
    4327 #define DMA_CH1PEND_bp  1  /* Channel 1 Block Transfer Pending bit position. */
     4547/* Channel 1 Block Transfer Pending bit position. */
     4548#define DMA_CH1PEND_bp  1 
    43284549
    43294550#define DMA_CH0PEND_bm  0x01  /* Channel 0 Block Transfer Pending bit mask. */
    4330 #define DMA_CH0PEND_bp  0  /* Channel 0 Block Transfer Pending bit position. */
     4551/* Channel 0 Block Transfer Pending bit position. */
     4552#define DMA_CH0PEND_bp  0 
    43314553
    43324554
     
    45014723
    45024724/* EVSYS.CH0CTRL  bit masks and bit positions */
    4503 #define EVSYS_QDIRM_gm  0x60  /* Quadrature Decoder Index Recognition Mode group mask. */
    4504 #define EVSYS_QDIRM_gp  5  /* Quadrature Decoder Index Recognition Mode group position. */
    4505 #define EVSYS_QDIRM0_bm  (1<<5)  /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
    4506 #define EVSYS_QDIRM0_bp  5  /* Quadrature Decoder Index Recognition Mode bit 0 position. */
    4507 #define EVSYS_QDIRM1_bm  (1<<6)  /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
    4508 #define EVSYS_QDIRM1_bp  6  /* Quadrature Decoder Index Recognition Mode bit 1 position. */
     4725/* Quadrature Decoder Index Recognition Mode group mask. */
     4726#define EVSYS_QDIRM_gm  0x60 
     4727/* Quadrature Decoder Index Recognition Mode group position. */
     4728#define EVSYS_QDIRM_gp  5 
     4729/* Quadrature Decoder Index Recognition Mode bit 0 mask. */
     4730#define EVSYS_QDIRM0_bm  (1<<5) 
     4731/* Quadrature Decoder Index Recognition Mode bit 0 position. */
     4732#define EVSYS_QDIRM0_bp  5 
     4733/* Quadrature Decoder Index Recognition Mode bit 1 mask. */
     4734#define EVSYS_QDIRM1_bm  (1<<6) 
     4735/* Quadrature Decoder Index Recognition Mode bit 1 position. */
     4736#define EVSYS_QDIRM1_bp  6 
    45094737
    45104738#define EVSYS_QDIEN_bm  0x10  /* Quadrature Decoder Index Enable bit mask. */
     
    46924920
    46934921#define NVM_EELOAD_bm  0x02  /* EEPROM Page Buffer Active Loading bit mask. */
    4694 #define NVM_EELOAD_bp  1  /* EEPROM Page Buffer Active Loading bit position. */
     4922/* EEPROM Page Buffer Active Loading bit position. */
     4923#define NVM_EELOAD_bp  1 
    46954924
    46964925#define NVM_FLOAD_bm  0x01  /* Flash Page Buffer Active Loading bit mask. */
     
    47064935#define NVM_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
    47074936
    4708 #define NVM_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
    4709 #define NVM_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
    4710 #define NVM_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
    4711 #define NVM_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
    4712 #define NVM_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
    4713 #define NVM_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
    4714 
    4715 #define NVM_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
    4716 #define NVM_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
    4717 #define NVM_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
    4718 #define NVM_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
    4719 #define NVM_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
    4720 #define NVM_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
     4937/* Boot Lock Bits - Application Section group mask. */
     4938#define NVM_BLBA_gm  0x30 
     4939/* Boot Lock Bits - Application Section group position. */
     4940#define NVM_BLBA_gp  4 
     4941 /* Boot Lock Bits - Application Section bit 0 mask. */
     4942#define NVM_BLBA0_bm  (1<<4)
     4943/* Boot Lock Bits - Application Section bit 0 position. */
     4944#define NVM_BLBA0_bp  4 
     4945/* Boot Lock Bits - Application Section bit 1 mask. */
     4946#define NVM_BLBA1_bm  (1<<5) 
     4947/* Boot Lock Bits - Application Section bit 1 position. */
     4948#define NVM_BLBA1_bp  5 
     4949
     4950/* Boot Lock Bits - Application Table group mask. */
     4951#define NVM_BLBAT_gm  0x0C 
     4952/* Boot Lock Bits - Application Table group position. */
     4953#define NVM_BLBAT_gp  2 
     4954/* Boot Lock Bits - Application Table bit 0 mask. */
     4955#define NVM_BLBAT0_bm  (1<<2) 
     4956/* Boot Lock Bits - Application Table bit 0 position. */
     4957#define NVM_BLBAT0_bp  2 
     4958/* Boot Lock Bits - Application Table bit 1 mask. */
     4959#define NVM_BLBAT1_bm  (1<<3) 
     4960/* Boot Lock Bits - Application Table bit 1 position. */
     4961#define NVM_BLBAT1_bp  3 
    47214962
    47224963#define NVM_LB_gm  0x03  /* Lock Bits group mask. */
     
    47294970
    47304971/* NVM_LOCKBITS.LOCKBITS  bit masks and bit positions */
    4731 #define NVM_LOCKBITS_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
    4732 #define NVM_LOCKBITS_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
    4733 #define NVM_LOCKBITS_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
    4734 #define NVM_LOCKBITS_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
    4735 #define NVM_LOCKBITS_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
    4736 #define NVM_LOCKBITS_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
    4737 
    4738 #define NVM_LOCKBITS_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
    4739 #define NVM_LOCKBITS_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
    4740 #define NVM_LOCKBITS_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
    4741 #define NVM_LOCKBITS_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
    4742 #define NVM_LOCKBITS_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
    4743 #define NVM_LOCKBITS_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
    4744 
    4745 #define NVM_LOCKBITS_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
    4746 #define NVM_LOCKBITS_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
    4747 #define NVM_LOCKBITS_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
    4748 #define NVM_LOCKBITS_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
    4749 #define NVM_LOCKBITS_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
    4750 #define NVM_LOCKBITS_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
     4972/* Boot Lock Bits - Boot Section group mask. */
     4973#define NVM_LOCKBITS_BLBB_gm  0xC0 
     4974/* Boot Lock Bits - Boot Section group position. */
     4975#define NVM_LOCKBITS_BLBB_gp  6 
     4976/* Boot Lock Bits - Boot Section bit 0 mask. */
     4977#define NVM_LOCKBITS_BLBB0_bm  (1<<6) 
     4978 /* Boot Lock Bits - Boot Section bit 0 position. */
     4979#define NVM_LOCKBITS_BLBB0_bp  6
     4980/* Boot Lock Bits - Boot Section bit 1 mask. */
     4981#define NVM_LOCKBITS_BLBB1_bm  (1<<7) 
     4982/* Boot Lock Bits - Boot Section bit 1 position. */
     4983#define NVM_LOCKBITS_BLBB1_bp  7 
     4984
     4985/* Boot Lock Bits - Application Section group mask. */
     4986#define NVM_LOCKBITS_BLBA_gm  0x30 
     4987/* Boot Lock Bits - Application Section group position. */
     4988#define NVM_LOCKBITS_BLBA_gp  4 
     4989/* Boot Lock Bits - Application Section bit 0 mask. */
     4990#define NVM_LOCKBITS_BLBA0_bm  (1<<4) 
     4991/* Boot Lock Bits - Application Section bit 0 position. */
     4992#define NVM_LOCKBITS_BLBA0_bp  4 
     4993/* Boot Lock Bits - Application Section bit 1 mask. */
     4994#define NVM_LOCKBITS_BLBA1_bm  (1<<5) 
     4995/* Boot Lock Bits - Application Section bit 1 position. */
     4996#define NVM_LOCKBITS_BLBA1_bp  5 
     4997
     4998/* Boot Lock Bits - Application Table group mask. */
     4999#define NVM_LOCKBITS_BLBAT_gm  0x0C 
     5000/* Boot Lock Bits - Application Table group position. */
     5001#define NVM_LOCKBITS_BLBAT_gp  2 
     5002/* Boot Lock Bits - Application Table bit 0 mask. */
     5003#define NVM_LOCKBITS_BLBAT0_bm  (1<<2) 
     5004/* Boot Lock Bits - Application Table bit 0 position. */
     5005#define NVM_LOCKBITS_BLBAT0_bp  2 
     5006/* Boot Lock Bits - Application Table bit 1 mask. */
     5007#define NVM_LOCKBITS_BLBAT1_bm  (1<<3) 
     5008/* Boot Lock Bits - Application Table bit 1 position. */
     5009#define NVM_LOCKBITS_BLBAT1_bp  3 
    47515010
    47525011#define NVM_LOCKBITS_LB_gm  0x03  /* Lock Bits group mask. */
     
    47805039
    47815040/* NVM_FUSES.FUSEBYTE1  bit masks and bit positions */
    4782 #define NVM_FUSES_WDWP_gm  0xF0  /* Watchdog Window Timeout Period group mask. */
    4783 #define NVM_FUSES_WDWP_gp  4  /* Watchdog Window Timeout Period group position. */
    4784 #define NVM_FUSES_WDWP0_bm  (1<<4)  /* Watchdog Window Timeout Period bit 0 mask. */
    4785 #define NVM_FUSES_WDWP0_bp  4  /* Watchdog Window Timeout Period bit 0 position. */
    4786 #define NVM_FUSES_WDWP1_bm  (1<<5)  /* Watchdog Window Timeout Period bit 1 mask. */
    4787 #define NVM_FUSES_WDWP1_bp  5  /* Watchdog Window Timeout Period bit 1 position. */
    4788 #define NVM_FUSES_WDWP2_bm  (1<<6)  /* Watchdog Window Timeout Period bit 2 mask. */
    4789 #define NVM_FUSES_WDWP2_bp  6  /* Watchdog Window Timeout Period bit 2 position. */
    4790 #define NVM_FUSES_WDWP3_bm  (1<<7)  /* Watchdog Window Timeout Period bit 3 mask. */
    4791 #define NVM_FUSES_WDWP3_bp  7  /* Watchdog Window Timeout Period bit 3 position. */
     5041/* Watchdog Window Timeout Period group mask. */
     5042#define NVM_FUSES_WDWP_gm  0xF0 
     5043/* Watchdog Window Timeout Period group position. */
     5044#define NVM_FUSES_WDWP_gp  4 
     5045/* Watchdog Window Timeout Period bit 0 mask. */
     5046#define NVM_FUSES_WDWP0_bm  (1<<4) 
     5047/* Watchdog Window Timeout Period bit 0 position. */
     5048#define NVM_FUSES_WDWP0_bp  4 
     5049/* Watchdog Window Timeout Period bit 1 mask. */
     5050#define NVM_FUSES_WDWP1_bm  (1<<5) 
     5051/* Watchdog Window Timeout Period bit 1 position. */
     5052#define NVM_FUSES_WDWP1_bp  5 
     5053/* Watchdog Window Timeout Period bit 2 mask. */
     5054#define NVM_FUSES_WDWP2_bm  (1<<6) 
     5055/* Watchdog Window Timeout Period bit 2 position. */
     5056#define NVM_FUSES_WDWP2_bp  6 
     5057/* Watchdog Window Timeout Period bit 3 mask. */
     5058#define NVM_FUSES_WDWP3_bm  (1<<7) 
     5059/* Watchdog Window Timeout Period bit 3 position. */
     5060#define NVM_FUSES_WDWP3_bp  7 
    47925061
    47935062#define NVM_FUSES_WDP_gm  0x0F  /* Watchdog Timeout Period group mask. */
     
    48075076#define NVM_FUSES_DVSDON_bp  7  /* Spike Detector Enable bit position. */
    48085077
    4809 #define NVM_FUSES_BOOTRST_bm  0x40  /* Boot Loader Section Reset Vector bit mask. */
    4810 #define NVM_FUSES_BOOTRST_bp  6  /* Boot Loader Section Reset Vector bit position. */
    4811 
    4812 #define NVM_FUSES_BODACT_gm  0x0C  /* BOD Operation in Active Mode group mask. */
    4813 #define NVM_FUSES_BODACT_gp  2  /* BOD Operation in Active Mode group position. */
    4814 #define NVM_FUSES_BODACT0_bm  (1<<2)  /* BOD Operation in Active Mode bit 0 mask. */
    4815 #define NVM_FUSES_BODACT0_bp  2  /* BOD Operation in Active Mode bit 0 position. */
    4816 #define NVM_FUSES_BODACT1_bm  (1<<3)  /* BOD Operation in Active Mode bit 1 mask. */
    4817 #define NVM_FUSES_BODACT1_bp  3  /* BOD Operation in Active Mode bit 1 position. */
    4818 
    4819 #define NVM_FUSES_BODPD_gm  0x03  /* BOD Operation in Power-Down Mode group mask. */
    4820 #define NVM_FUSES_BODPD_gp  0  /* BOD Operation in Power-Down Mode group position. */
    4821 #define NVM_FUSES_BODPD0_bm  (1<<0)  /* BOD Operation in Power-Down Mode bit 0 mask. */
    4822 #define NVM_FUSES_BODPD0_bp  0  /* BOD Operation in Power-Down Mode bit 0 position. */
    4823 #define NVM_FUSES_BODPD1_bm  (1<<1)  /* BOD Operation in Power-Down Mode bit 1 mask. */
    4824 #define NVM_FUSES_BODPD1_bp  1  /* BOD Operation in Power-Down Mode bit 1 position. */
     5078/* Boot Loader Section Reset Vector bit mask. */
     5079#define NVM_FUSES_BOOTRST_bm  0x40 
     5080/* Boot Loader Section Reset Vector bit position. */
     5081#define NVM_FUSES_BOOTRST_bp  6 
     5082
     5083/* BOD Operation in Active Mode group mask. */
     5084#define NVM_FUSES_BODACT_gm  0x0C 
     5085/* BOD Operation in Active Mode group position. */
     5086#define NVM_FUSES_BODACT_gp  2
     5087/* BOD Operation in Active Mode bit 0 mask. */
     5088#define NVM_FUSES_BODACT0_bm  (1<<2) 
     5089/* BOD Operation in Active Mode bit 0 position. */
     5090#define NVM_FUSES_BODACT0_bp  2 
     5091/* BOD Operation in Active Mode bit 1 mask. */
     5092#define NVM_FUSES_BODACT1_bm  (1<<3) 
     5093/* BOD Operation in Active Mode bit 1 position. */
     5094#define NVM_FUSES_BODACT1_bp  3 
     5095
     5096/* BOD Operation in Power-Down Mode group mask. */
     5097#define NVM_FUSES_BODPD_gm  0x03 
     5098/* BOD Operation in Power-Down Mode group position. */
     5099#define NVM_FUSES_BODPD_gp  0 
     5100/* BOD Operation in Power-Down Mode bit 0 mask. */
     5101#define NVM_FUSES_BODPD0_bm  (1<<0) 
     5102/* BOD Operation in Power-Down Mode bit 0 position. */
     5103#define NVM_FUSES_BODPD0_bp  0 
     5104/* BOD Operation in Power-Down Mode bit 1 mask. */
     5105#define NVM_FUSES_BODPD1_bm  (1<<1) 
     5106/* BOD Operation in Power-Down Mode bit 1 position. */
     5107#define NVM_FUSES_BODPD1_bp  1 
    48255108
    48265109
     
    48415124
    48425125/* NVM_FUSES.FUSEBYTE5  bit masks and bit positions */
    4843 #define NVM_FUSES_EESAVE_bm  0x08  /* Preserve EEPROM Through Chip Erase bit mask. */
    4844 #define NVM_FUSES_EESAVE_bp  3  /* Preserve EEPROM Through Chip Erase bit position. */
    4845 
    4846 #define NVM_FUSES_BODLVL_gm  0x07  /* Brown Out Detection Voltage Level group mask. */
    4847 #define NVM_FUSES_BODLVL_gp  0  /* Brown Out Detection Voltage Level group position. */
    4848 #define NVM_FUSES_BODLVL0_bm  (1<<0)  /* Brown Out Detection Voltage Level bit 0 mask. */
    4849 #define NVM_FUSES_BODLVL0_bp  0  /* Brown Out Detection Voltage Level bit 0 position. */
    4850 #define NVM_FUSES_BODLVL1_bm  (1<<1)  /* Brown Out Detection Voltage Level bit 1 mask. */
    4851 #define NVM_FUSES_BODLVL1_bp  1  /* Brown Out Detection Voltage Level bit 1 position. */
    4852 #define NVM_FUSES_BODLVL2_bm  (1<<2)  /* Brown Out Detection Voltage Level bit 2 mask. */
    4853 #define NVM_FUSES_BODLVL2_bp  2  /* Brown Out Detection Voltage Level bit 2 position. */
     5126/* Preserve EEPROM Through Chip Erase bit mask. */
     5127#define NVM_FUSES_EESAVE_bm  0x08 
     5128/* Preserve EEPROM Through Chip Erase bit position. */
     5129#define NVM_FUSES_EESAVE_bp  3 
     5130
     5131/* Brown Out Detection Voltage Level group mask. */
     5132#define NVM_FUSES_BODLVL_gm  0x07 
     5133/* Brown Out Detection Voltage Level group position. */
     5134#define NVM_FUSES_BODLVL_gp  0 
     5135/* Brown Out Detection Voltage Level bit 0 mask. */
     5136#define NVM_FUSES_BODLVL0_bm  (1<<0) 
     5137/* Brown Out Detection Voltage Level bit 0 position. */
     5138#define NVM_FUSES_BODLVL0_bp  0 
     5139/* Brown Out Detection Voltage Level bit 1 mask. */
     5140#define NVM_FUSES_BODLVL1_bm  (1<<1) 
     5141/* Brown Out Detection Voltage Level bit 1 position. */
     5142#define NVM_FUSES_BODLVL1_bp  1 
     5143/* Brown Out Detection Voltage Level bit 2 mask. */
     5144#define NVM_FUSES_BODLVL2_bm  (1<<2) 
     5145/* Brown Out Detection Voltage Level bit 2 position. */
     5146#define NVM_FUSES_BODLVL2_bp  2 
    48545147
    48555148
     
    53105603
    53115604/* RTC.INTCTRL  bit masks and bit positions */
    5312 #define RTC_COMPINTLVL_gm  0x0C  /* Compare Match Interrupt Level group mask. */
    5313 #define RTC_COMPINTLVL_gp  2  /* Compare Match Interrupt Level group position. */
    5314 #define RTC_COMPINTLVL0_bm  (1<<2)  /* Compare Match Interrupt Level bit 0 mask. */
    5315 #define RTC_COMPINTLVL0_bp  2  /* Compare Match Interrupt Level bit 0 position. */
    5316 #define RTC_COMPINTLVL1_bm  (1<<3)  /* Compare Match Interrupt Level bit 1 mask. */
    5317 #define RTC_COMPINTLVL1_bp  3  /* Compare Match Interrupt Level bit 1 position. */
     5605/* Compare Match Interrupt Level group mask. */
     5606#define RTC_COMPINTLVL_gm  0x0C 
     5607/* Compare Match Interrupt Level group position. */
     5608#define RTC_COMPINTLVL_gp  2 
     5609 /* Compare Match Interrupt Level bit 0 mask. */
     5610#define RTC_COMPINTLVL0_bm  (1<<2)
     5611/* Compare Match Interrupt Level bit 0 position. */
     5612#define RTC_COMPINTLVL0_bp  2 
     5613/* Compare Match Interrupt Level bit 1 mask. */
     5614#define RTC_COMPINTLVL1_bm  (1<<3) 
     5615/* Compare Match Interrupt Level bit 1 position. */
     5616#define RTC_COMPINTLVL1_bp  3 
    53185617
    53195618#define RTC_OVFINTLVL_gm  0x03  /* Overflow Interrupt Level group mask. */
     
    54605759#define EBI_WRDLY1_bp  7  /* SDRAM Write Recovery Delay bit 1 position. */
    54615760
    5462 #define EBI_ESRDLY_gm  0x38  /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */
    5463 #define EBI_ESRDLY_gp  3  /* SDRAM Exit-Self-refresh-to-Active Delay group position. */
    5464 #define EBI_ESRDLY0_bm  (1<<3)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */
    5465 #define EBI_ESRDLY0_bp  3  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */
    5466 #define EBI_ESRDLY1_bm  (1<<4)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */
    5467 #define EBI_ESRDLY1_bp  4  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */
    5468 #define EBI_ESRDLY2_bm  (1<<5)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */
    5469 #define EBI_ESRDLY2_bp  5  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */
     5761/* SDRAM Exit-Self-refresh-to-Active Delay group mask. */
     5762#define EBI_ESRDLY_gm  0x38 
     5763/* SDRAM Exit-Self-refresh-to-Active Delay group position. */
     5764#define EBI_ESRDLY_gp  3 
     5765/* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */
     5766#define EBI_ESRDLY0_bm  (1<<3) 
     5767/* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */
     5768#define EBI_ESRDLY0_bp  3 
     5769/* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */
     5770#define EBI_ESRDLY1_bm  (1<<4) 
     5771/* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */
     5772#define EBI_ESRDLY1_bp  4 
     5773/* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */
     5774#define EBI_ESRDLY2_bm  (1<<5) 
     5775/* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */
     5776#define EBI_ESRDLY2_bp  5 
    54705777
    54715778#define EBI_ROWCOLDLY_gm  0x07  /* SDRAM Row-to-Column Delay group mask. */
     
    55635870#define TWI_SLAVE_DIEN_bp  5  /* Data Interrupt Enable bit position. */
    55645871
    5565 #define TWI_SLAVE_APIEN_bm  0x10  /* Address/Stop Interrupt Enable bit mask. */
    5566 #define TWI_SLAVE_APIEN_bp  4  /* Address/Stop Interrupt Enable bit position. */
     5872/* Address/Stop Interrupt Enable bit mask. */
     5873#define TWI_SLAVE_APIEN_bm  0x10 
     5874/* Address/Stop Interrupt Enable bit position. */
     5875#define TWI_SLAVE_APIEN_bp  4 
    55675876
    55685877#define TWI_SLAVE_ENABLE_bm  0x08  /* Enable TWI Slave bit mask. */
     
    60536362
    60546363/* TC0.INTCTRLB  bit masks and bit positions */
    6055 #define TC0_CCDINTLVL_gm  0xC0  /* Compare or Capture D Interrupt Level group mask. */
    6056 #define TC0_CCDINTLVL_gp  6  /* Compare or Capture D Interrupt Level group position. */
    6057 #define TC0_CCDINTLVL0_bm  (1<<6)  /* Compare or Capture D Interrupt Level bit 0 mask. */
    6058 #define TC0_CCDINTLVL0_bp  6  /* Compare or Capture D Interrupt Level bit 0 position. */
    6059 #define TC0_CCDINTLVL1_bm  (1<<7)  /* Compare or Capture D Interrupt Level bit 1 mask. */
    6060 #define TC0_CCDINTLVL1_bp  7  /* Compare or Capture D Interrupt Level bit 1 position. */
    6061 
    6062 #define TC0_CCCINTLVL_gm  0x30  /* Compare or Capture C Interrupt Level group mask. */
    6063 #define TC0_CCCINTLVL_gp  4  /* Compare or Capture C Interrupt Level group position. */
    6064 #define TC0_CCCINTLVL0_bm  (1<<4)  /* Compare or Capture C Interrupt Level bit 0 mask. */
    6065 #define TC0_CCCINTLVL0_bp  4  /* Compare or Capture C Interrupt Level bit 0 position. */
    6066 #define TC0_CCCINTLVL1_bm  (1<<5)  /* Compare or Capture C Interrupt Level bit 1 mask. */
    6067 #define TC0_CCCINTLVL1_bp  5  /* Compare or Capture C Interrupt Level bit 1 position. */
    6068 
    6069 #define TC0_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
    6070 #define TC0_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
    6071 #define TC0_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
    6072 #define TC0_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
    6073 #define TC0_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
    6074 #define TC0_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
    6075 
    6076 #define TC0_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
    6077 #define TC0_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
    6078 #define TC0_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
    6079 #define TC0_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
    6080 #define TC0_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
    6081 #define TC0_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
     6364/* Compare or Capture D Interrupt Level group mask. */
     6365#define TC0_CCDINTLVL_gm  0xC0 
     6366/* Compare or Capture D Interrupt Level group position. */
     6367#define TC0_CCDINTLVL_gp  6 
     6368/* Compare or Capture D Interrupt Level bit 0 mask. */
     6369#define TC0_CCDINTLVL0_bm  (1<<6) 
     6370/* Compare or Capture D Interrupt Level bit 0 position. */
     6371#define TC0_CCDINTLVL0_bp  6 
     6372/* Compare or Capture D Interrupt Level bit 1 mask. */
     6373#define TC0_CCDINTLVL1_bm  (1<<7) 
     6374/* Compare or Capture D Interrupt Level bit 1 position. */
     6375#define TC0_CCDINTLVL1_bp  7 
     6376
     6377/* Compare or Capture C Interrupt Level group mask. */
     6378#define TC0_CCCINTLVL_gm  0x30 
     6379 /* Compare or Capture C Interrupt Level group position. */
     6380#define TC0_CCCINTLVL_gp  4
     6381/* Compare or Capture C Interrupt Level bit 0 mask. */
     6382#define TC0_CCCINTLVL0_bm  (1<<4) 
     6383/* Compare or Capture C Interrupt Level bit 0 position. */
     6384#define TC0_CCCINTLVL0_bp  4 
     6385 /* Compare or Capture C Interrupt Level bit 1 mask. */
     6386#define TC0_CCCINTLVL1_bm  (1<<5)
     6387/* Compare or Capture C Interrupt Level bit 1 position. */
     6388#define TC0_CCCINTLVL1_bp  5 
     6389
     6390/* Compare or Capture B Interrupt Level group mask. */
     6391#define TC0_CCBINTLVL_gm  0x0C 
     6392/* Compare or Capture B Interrupt Level group position. */
     6393#define TC0_CCBINTLVL_gp  2 
     6394/* Compare or Capture B Interrupt Level bit 0 mask. */
     6395#define TC0_CCBINTLVL0_bm  (1<<2) 
     6396 /* Compare or Capture B Interrupt Level bit 0 position. */
     6397#define TC0_CCBINTLVL0_bp  2
     6398/* Compare or Capture B Interrupt Level bit 1 mask. */
     6399#define TC0_CCBINTLVL1_bm  (1<<3) 
     6400/* Compare or Capture B Interrupt Level bit 1 position. */
     6401#define TC0_CCBINTLVL1_bp  3 
     6402
     6403/* Compare or Capture A Interrupt Level group mask. */
     6404#define TC0_CCAINTLVL_gm  0x03 
     6405/* Compare or Capture A Interrupt Level group position. */
     6406#define TC0_CCAINTLVL_gp  0 
     6407/* Compare or Capture A Interrupt Level bit 0 mask. */
     6408#define TC0_CCAINTLVL0_bm  (1<<0) 
     6409/* Compare or Capture A Interrupt Level bit 0 position. */
     6410#define TC0_CCAINTLVL0_bp  0 
     6411/* Compare or Capture A Interrupt Level bit 1 mask. */
     6412#define TC0_CCAINTLVL1_bm  (1<<1) 
     6413/* Compare or Capture A Interrupt Level bit 1 position. */
     6414#define TC0_CCAINTLVL1_bp  1 
    60826415
    60836416
     
    61476480
    61486481/* TC0.INTFLAGS  bit masks and bit positions */
    6149 #define TC0_CCDIF_bm  0x80  /* Compare or Capture D Interrupt Flag bit mask. */
    6150 #define TC0_CCDIF_bp  7  /* Compare or Capture D Interrupt Flag bit position. */
    6151 
    6152 #define TC0_CCCIF_bm  0x40  /* Compare or Capture C Interrupt Flag bit mask. */
    6153 #define TC0_CCCIF_bp  6  /* Compare or Capture C Interrupt Flag bit position. */
    6154 
    6155 #define TC0_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
    6156 #define TC0_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
    6157 
    6158 #define TC0_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
    6159 #define TC0_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
     6482/* Compare or Capture D Interrupt Flag bit mask. */
     6483#define TC0_CCDIF_bm  0x80 
     6484/* Compare or Capture D Interrupt Flag bit position. */
     6485#define TC0_CCDIF_bp  7 
     6486
     6487/* Compare or Capture C Interrupt Flag bit mask. */
     6488#define TC0_CCCIF_bm  0x40 
     6489/* Compare or Capture C Interrupt Flag bit position. */
     6490#define TC0_CCCIF_bp  6 
     6491
     6492/* Compare or Capture B Interrupt Flag bit mask. */
     6493#define TC0_CCBIF_bm  0x20 
     6494/* Compare or Capture B Interrupt Flag bit position. */
     6495#define TC0_CCBIF_bp  5 
     6496
     6497/* Compare or Capture A Interrupt Flag bit mask. */
     6498#define TC0_CCAIF_bm  0x10 
     6499/* Compare or Capture A Interrupt Flag bit position. */
     6500#define TC0_CCAIF_bp  4 
    61606501
    61616502#define TC0_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
     
    62546595
    62556596/* TC1.INTCTRLB  bit masks and bit positions */
    6256 #define TC1_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
    6257 #define TC1_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
    6258 #define TC1_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
    6259 #define TC1_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
    6260 #define TC1_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
    6261 #define TC1_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
    6262 
    6263 #define TC1_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
    6264 #define TC1_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
    6265 #define TC1_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
    6266 #define TC1_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
    6267 #define TC1_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
    6268 #define TC1_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
     6597/* Compare or Capture B Interrupt Level group mask. */
     6598#define TC1_CCBINTLVL_gm  0x0C 
     6599/* Compare or Capture B Interrupt Level group position. */
     6600#define TC1_CCBINTLVL_gp  2 
     6601/* Compare or Capture B Interrupt Level bit 0 mask. */
     6602#define TC1_CCBINTLVL0_bm  (1<<2) 
     6603 /* Compare or Capture B Interrupt Level bit 0 position. */
     6604#define TC1_CCBINTLVL0_bp  2
     6605/* Compare or Capture B Interrupt Level bit 1 mask. */
     6606#define TC1_CCBINTLVL1_bm  (1<<3) 
     6607/* Compare or Capture B Interrupt Level bit 1 position. */
     6608#define TC1_CCBINTLVL1_bp  3 
     6609
     6610/* Compare or Capture A Interrupt Level group mask. */
     6611#define TC1_CCAINTLVL_gm  0x03 
     6612/* Compare or Capture A Interrupt Level group position. */
     6613#define TC1_CCAINTLVL_gp  0 
     6614/* Compare or Capture A Interrupt Level bit 0 mask. */
     6615#define TC1_CCAINTLVL0_bm  (1<<0) 
     6616/* Compare or Capture A Interrupt Level bit 0 position. */
     6617#define TC1_CCAINTLVL0_bp  0 
     6618/* Compare or Capture A Interrupt Level bit 1 mask. */
     6619#define TC1_CCAINTLVL1_bm  (1<<1) 
     6620/* Compare or Capture A Interrupt Level bit 1 position. */
     6621#define TC1_CCAINTLVL1_bp  1 
    62696622
    62706623
     
    63226675
    63236676/* TC1.INTFLAGS  bit masks and bit positions */
    6324 #define TC1_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
    6325 #define TC1_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
    6326 
    6327 #define TC1_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
    6328 #define TC1_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
     6677
     6678/* Compare or Capture B Interrupt Flag bit mask. */
     6679#define TC1_CCBIF_bm  0x20 
     6680/* Compare or Capture B Interrupt Flag bit position. */
     6681#define TC1_CCBIF_bp  5 
     6682
     6683/* Compare or Capture A Interrupt Flag bit mask. */
     6684#define TC1_CCAIF_bm  0x10 
     6685/* Compare or Capture A Interrupt Flag bit position. */
     6686#define TC1_CCAIF_bp  4 
    63296687
    63306688#define TC1_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
     
    63426700#define AWEX_CWCM_bp  4  /* Common Waveform Channel Mode bit position. */
    63436701
    6344 #define AWEX_DTICCDEN_bm  0x08  /* Dead Time Insertion Compare Channel D Enable bit mask. */
    6345 #define AWEX_DTICCDEN_bp  3  /* Dead Time Insertion Compare Channel D Enable bit position. */
    6346 
    6347 #define AWEX_DTICCCEN_bm  0x04  /* Dead Time Insertion Compare Channel C Enable bit mask. */
    6348 #define AWEX_DTICCCEN_bp  2  /* Dead Time Insertion Compare Channel C Enable bit position. */
    6349 
    6350 #define AWEX_DTICCBEN_bm  0x02  /* Dead Time Insertion Compare Channel B Enable bit mask. */
    6351 #define AWEX_DTICCBEN_bp  1  /* Dead Time Insertion Compare Channel B Enable bit position. */
    6352 
    6353 #define AWEX_DTICCAEN_bm  0x01  /* Dead Time Insertion Compare Channel A Enable bit mask. */
    6354 #define AWEX_DTICCAEN_bp  0  /* Dead Time Insertion Compare Channel A Enable bit position. */
     6702/* Dead Time Insertion Compare Channel D Enable bit mask. */
     6703#define AWEX_DTICCDEN_bm  0x08 
     6704/* Dead Time Insertion Compare Channel D Enable bit position. */
     6705#define AWEX_DTICCDEN_bp  3 
     6706
     6707/* Dead Time Insertion Compare Channel C Enable bit mask. */
     6708#define AWEX_DTICCCEN_bm  0x04 
     6709/* Dead Time Insertion Compare Channel C Enable bit position. */
     6710#define AWEX_DTICCCEN_bp  2 
     6711
     6712/* Dead Time Insertion Compare Channel B Enable bit mask. */
     6713#define AWEX_DTICCBEN_bm  0x02 
     6714/* Dead Time Insertion Compare Channel B Enable bit position. */
     6715#define AWEX_DTICCBEN_bp  1 
     6716
     6717/* Dead Time Insertion Compare Channel A Enable bit mask. */
     6718#define AWEX_DTICCAEN_bm  0x01 
     6719/* Dead Time Insertion Compare Channel A Enable bit position. */
     6720#define AWEX_DTICCAEN_bp  0 
    63556721
    63566722
    63576723/* AWEX.FDCTRL  bit masks and bit positions */
    6358 #define AWEX_FDDBD_bm  0x10  /* Fault Detect on Disable Break Disable bit mask. */
    6359 #define AWEX_FDDBD_bp  4  /* Fault Detect on Disable Break Disable bit position. */
     6724/* Fault Detect on Disable Break Disable bit mask. */
     6725#define AWEX_FDDBD_bm  0x10 
     6726/* Fault Detect on Disable Break Disable bit position. */
     6727#define AWEX_FDDBD_bp  4 
    63606728
    63616729#define AWEX_FDMODE_bm  0x04  /* Fault Detect Mode bit mask. */
     
    63746742#define AWEX_FDF_bp  2  /* Fault Detect Flag bit position. */
    63756743
    6376 #define AWEX_DTHSBUFV_bm  0x02  /* Dead Time High Side Buffer Valid bit mask. */
    6377 #define AWEX_DTHSBUFV_bp  1  /* Dead Time High Side Buffer Valid bit position. */
    6378 
    6379 #define AWEX_DTLSBUFV_bm  0x01  /* Dead Time Low Side Buffer Valid bit mask. */
    6380 #define AWEX_DTLSBUFV_bp  0  /* Dead Time Low Side Buffer Valid bit position. */
     6744/* Dead Time High Side Buffer Valid bit mask. */
     6745#define AWEX_DTHSBUFV_bm  0x02 
     6746/* Dead Time High Side Buffer Valid bit position. */
     6747#define AWEX_DTHSBUFV_bp  1 
     6748
     6749/* Dead Time Low Side Buffer Valid bit mask. */
     6750#define AWEX_DTLSBUFV_bm  0x01 
     6751/* Dead Time Low Side Buffer Valid bit position. */
     6752#define AWEX_DTLSBUFV_bp  0 
    63816753
    63826754
     
    64246796#define USART_TXCINTLVL_gm  0x0C  /* Transmit Interrupt Level group mask. */
    64256797#define USART_TXCINTLVL_gp  2  /* Transmit Interrupt Level group position. */
    6426 #define USART_TXCINTLVL0_bm  (1<<2)  /* Transmit Interrupt Level bit 0 mask. */
     6798/* Transmit Interrupt Level bit 0 mask. */
     6799#define USART_TXCINTLVL0_bm  (1<<2) 
    64276800#define USART_TXCINTLVL0_bp  2  /* Transmit Interrupt Level bit 0 position. */
    6428 #define USART_TXCINTLVL1_bm  (1<<3)  /* Transmit Interrupt Level bit 1 mask. */
     6801/* Transmit Interrupt Level bit 1 mask. */
     6802#define USART_TXCINTLVL1_bm  (1<<3) 
    64296803#define USART_TXCINTLVL1_bp  3  /* Transmit Interrupt Level bit 1 position. */
    64306804
    6431 #define USART_DREINTLVL_gm  0x03  /* Data Register Empty Interrupt Level group mask. */
    6432 #define USART_DREINTLVL_gp  0  /* Data Register Empty Interrupt Level group position. */
    6433 #define USART_DREINTLVL0_bm  (1<<0)  /* Data Register Empty Interrupt Level bit 0 mask. */
    6434 #define USART_DREINTLVL0_bp  0  /* Data Register Empty Interrupt Level bit 0 position. */
    6435 #define USART_DREINTLVL1_bm  (1<<1)  /* Data Register Empty Interrupt Level bit 1 mask. */
    6436 #define USART_DREINTLVL1_bp  1  /* Data Register Empty Interrupt Level bit 1 position. */
     6805/* Data Register Empty Interrupt Level group mask. */
     6806#define USART_DREINTLVL_gm  0x03 
     6807/* Data Register Empty Interrupt Level group position. */
     6808#define USART_DREINTLVL_gp  0 
     6809/* Data Register Empty Interrupt Level bit 0 mask. */
     6810#define USART_DREINTLVL0_bm  (1<<0)
     6811/* Data Register Empty Interrupt Level bit 0 position. */
     6812#define USART_DREINTLVL0_bp  0 
     6813/* Data Register Empty Interrupt Level bit 1 mask. */
     6814#define USART_DREINTLVL1_bm  (1<<1) 
     6815/* Data Register Empty Interrupt Level bit 1 position. */
     6816#define USART_DREINTLVL1_bp  1 
    64376817
    64386818
     
    64476827#define USART_CLK2X_bp  2  /* Double transmission speed bit position. */
    64486828
    6449 #define USART_MPCM_bm  0x02  /* Multi-processor Communication Mode bit mask. */
    6450 #define USART_MPCM_bp  1  /* Multi-processor Communication Mode bit position. */
     6829/* Multi-processor Communication Mode bit mask. */
     6830#define USART_MPCM_bm  0x02 
     6831/* Multi-processor Communication Mode bit position. */
     6832#define USART_MPCM_bp  1 
    64516833
    64526834#define USART_TXB8_bm  0x01  /* Transmit bit 8 bit mask. */
     
    64856867#define USART_BSEL_gm  0xFF  /* Baud Rate Selection Bits [7:0] group mask. */
    64866868#define USART_BSEL_gp  0  /* Baud Rate Selection Bits [7:0] group position. */
    6487 #define USART_BSEL0_bm  (1<<0)  /* Baud Rate Selection Bits [7:0] bit 0 mask. */
    6488 #define USART_BSEL0_bp  0  /* Baud Rate Selection Bits [7:0] bit 0 position. */
    6489 #define USART_BSEL1_bm  (1<<1)  /* Baud Rate Selection Bits [7:0] bit 1 mask. */
    6490 #define USART_BSEL1_bp  1  /* Baud Rate Selection Bits [7:0] bit 1 position. */
    6491 #define USART_BSEL2_bm  (1<<2)  /* Baud Rate Selection Bits [7:0] bit 2 mask. */
    6492 #define USART_BSEL2_bp  2  /* Baud Rate Selection Bits [7:0] bit 2 position. */
    6493 #define USART_BSEL3_bm  (1<<3)  /* Baud Rate Selection Bits [7:0] bit 3 mask. */
    6494 #define USART_BSEL3_bp  3  /* Baud Rate Selection Bits [7:0] bit 3 position. */
    6495 #define USART_BSEL4_bm  (1<<4)  /* Baud Rate Selection Bits [7:0] bit 4 mask. */
    6496 #define USART_BSEL4_bp  4  /* Baud Rate Selection Bits [7:0] bit 4 position. */
    6497 #define USART_BSEL5_bm  (1<<5)  /* Baud Rate Selection Bits [7:0] bit 5 mask. */
    6498 #define USART_BSEL5_bp  5  /* Baud Rate Selection Bits [7:0] bit 5 position. */
    6499 #define USART_BSEL6_bm  (1<<6)  /* Baud Rate Selection Bits [7:0] bit 6 mask. */
    6500 #define USART_BSEL6_bp  6  /* Baud Rate Selection Bits [7:0] bit 6 position. */
    6501 #define USART_BSEL7_bm  (1<<7)  /* Baud Rate Selection Bits [7:0] bit 7 mask. */
    6502 #define USART_BSEL7_bp  7  /* Baud Rate Selection Bits [7:0] bit 7 position. */
     6869/* Baud Rate Selection Bits [7:0] bit 0 mask. */
     6870#define USART_BSEL0_bm  (1<<0) 
     6871/* Baud Rate Selection Bits [7:0] bit 0 position. */
     6872#define USART_BSEL0_bp  0 
     6873/* Baud Rate Selection Bits [7:0] bit 1 mask. */
     6874#define USART_BSEL1_bm  (1<<1) 
     6875/* Baud Rate Selection Bits [7:0] bit 1 position. */
     6876#define USART_BSEL1_bp  1 
     6877/* Baud Rate Selection Bits [7:0] bit 2 mask. */
     6878#define USART_BSEL2_bm  (1<<2) 
     6879/* Baud Rate Selection Bits [7:0] bit 2 position. */
     6880#define USART_BSEL2_bp  2 
     6881/* Baud Rate Selection Bits [7:0] bit 3 mask. */
     6882#define USART_BSEL3_bm  (1<<3) 
     6883/* Baud Rate Selection Bits [7:0] bit 3 position. */
     6884#define USART_BSEL3_bp  3 
     6885/* Baud Rate Selection Bits [7:0] bit 4 mask. */
     6886#define USART_BSEL4_bm  (1<<4) 
     6887/* Baud Rate Selection Bits [7:0] bit 4 position. */
     6888#define USART_BSEL4_bp  4 
     6889/* Baud Rate Selection Bits [7:0] bit 5 mask. */
     6890#define USART_BSEL5_bm  (1<<5) 
     6891/* Baud Rate Selection Bits [7:0] bit 5 position. */
     6892#define USART_BSEL5_bp  5 
     6893/* Baud Rate Selection Bits [7:0] bit 6 mask. */
     6894#define USART_BSEL6_bm  (1<<6) 
     6895/* Baud Rate Selection Bits [7:0] bit 6 position. */
     6896#define USART_BSEL6_bp  6 
     6897/* Baud Rate Selection Bits [7:0] bit 7 mask. */
     6898#define USART_BSEL7_bm  (1<<7) 
     6899/* Baud Rate Selection Bits [7:0] bit 7 position. */
     6900#define USART_BSEL7_bp  7
    65036901
    65046902
     
    66417039#define PIN7_bm 0x80
    66427040#define PIN7_bp 7
    6643 
    6644 
    6645 /* ========== Interrupt Vector Definitions ========== */
     7041/** @} */
     7042
     7043/**
     7044 * @name Interrupt Vector Definitions
     7045 *
     7046 * @{
     7047 */
    66467048/* Vector 0 is the reset vector */
    66477049
    66487050/* OSC interrupt vectors */
    66497051#define OSC_XOSCF_vect_num  1
    6650 #define OSC_XOSCF_vect      _VECTOR(1)  /* External Oscillator Failure Interrupt (NMI) */
     7052/* External Oscillator Failure Interrupt (NMI) */
     7053#define OSC_XOSCF_vect      _VECTOR(1)
    66517054
    66527055/* PORTC interrupt vectors */
     
    67187121#define USARTC0_DRE_vect      _VECTOR(26)  /* Data Register Empty Interrupt */
    67197122#define USARTC0_TXC_vect_num  27
    6720 #define USARTC0_TXC_vect      _VECTOR(27)  /* Transmission Complete Interrupt */
     7123/* Transmission Complete Interrupt */
     7124#define USARTC0_TXC_vect      _VECTOR(27)
    67217125
    67227126/* USARTC1 interrupt vectors */
     
    67267130#define USARTC1_DRE_vect      _VECTOR(29)  /* Data Register Empty Interrupt */
    67277131#define USARTC1_TXC_vect_num  30
    6728 #define USARTC1_TXC_vect      _VECTOR(30)  /* Transmission Complete Interrupt */
     7132 /* Transmission Complete Interrupt */
     7133#define USARTC1_TXC_vect      _VECTOR(30)
    67297134
    67307135/* AES interrupt vectors */
     
    68087213#define USARTE0_DRE_vect      _VECTOR(59)  /* Data Register Empty Interrupt */
    68097214#define USARTE0_TXC_vect_num  60
    6810 #define USARTE0_TXC_vect      _VECTOR(60)  /* Transmission Complete Interrupt */
     7215/* Transmission Complete Interrupt */
     7216#define USARTE0_TXC_vect      _VECTOR(60)
    68117217
    68127218/* USARTE1 interrupt vectors */
     
    68167222#define USARTE1_DRE_vect      _VECTOR(62)  /* Data Register Empty Interrupt */
    68177223#define USARTE1_TXC_vect_num  63
    6818 #define USARTE1_TXC_vect      _VECTOR(63)  /* Transmission Complete Interrupt */
     7224/* Transmission Complete Interrupt */
     7225#define USARTE1_TXC_vect      _VECTOR(63)
    68197226
    68207227/* PORTD interrupt vectors */
     
    68887295#define USARTD0_DRE_vect      _VECTOR(89)  /* Data Register Empty Interrupt */
    68897296#define USARTD0_TXC_vect_num  90
    6890 #define USARTD0_TXC_vect      _VECTOR(90)  /* Transmission Complete Interrupt */
     7297/* Transmission Complete Interrupt */
     7298#define USARTD0_TXC_vect      _VECTOR(90)
    68917299
    68927300/* USARTD1 interrupt vectors */
     
    68967304#define USARTD1_DRE_vect      _VECTOR(92)  /* Data Register Empty Interrupt */
    68977305#define USARTD1_TXC_vect_num  93
    6898 #define USARTD1_TXC_vect      _VECTOR(93)  /* Transmission Complete Interrupt */
     7306/* Transmission Complete Interrupt */
     7307#define USARTD1_TXC_vect      _VECTOR(93)
    68997308
    69007309/* PORTQ interrupt vectors */
     
    69667375#define USARTF0_RXC_vect      _VECTOR(119)  /* Reception Complete Interrupt */
    69677376#define USARTF0_DRE_vect_num  120
    6968 #define USARTF0_DRE_vect      _VECTOR(120)  /* Data Register Empty Interrupt */
     7377/* Data Register Empty Interrupt */
     7378#define USARTF0_DRE_vect      _VECTOR(120) 
    69697379#define USARTF0_TXC_vect_num  121
    6970 #define USARTF0_TXC_vect      _VECTOR(121)  /* Transmission Complete Interrupt */
     7380/* Transmission Complete Interrupt */
     7381#define USARTF0_TXC_vect      _VECTOR(121)
    69717382
    69727383/* USARTF1 interrupt vectors */
     
    69747385#define USARTF1_RXC_vect      _VECTOR(122)  /* Reception Complete Interrupt */
    69757386#define USARTF1_DRE_vect_num  123
    6976 #define USARTF1_DRE_vect      _VECTOR(123)  /* Data Register Empty Interrupt */
     7387/* Data Register Empty Interrupt */
     7388#define USARTF1_DRE_vect      _VECTOR(123)
    69777389#define USARTF1_TXC_vect_num  124
    6978 #define USARTF1_TXC_vect      _VECTOR(124)  /* Transmission Complete Interrupt */
     7390/* Transmission Complete Interrupt */
     7391#define USARTF1_TXC_vect      _VECTOR(124)
    69797392
    69807393
    69817394#define _VECTOR_SIZE 4 /* Size of individual vector. */
    69827395#define _VECTORS_SIZE (125 * _VECTOR_SIZE)
    6983 
    6984 
    6985 /* ========== Constants ========== */
    6986 
     7396/** @} */
     7397
     7398/**
     7399 * @name Constants
     7400 *
     7401 * @{
     7402 */
    69877403#define PROGMEM_START     (0x0000)
    69887404#define PROGMEM_SIZE      (139264)
     
    69987414#define APPTABLE_SECTION_SIZE      (8192)
    69997415#define APPTABLE_SECTION_PAGE_SIZE (512)
    7000 #define APPTABLE_SECTION_END       (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
     7416#define APPTABLE_SECTION_END       (APPTABLE_SECTION_START + \
     7417                                    APPTABLE_SECTION_SIZE - 1)
    70017418
    70027419#define BOOT_SECTION_START     (0x20000)
     
    70537470#define USER_SIGNATURES_SIZE      (512)
    70547471#define USER_SIGNATURES_PAGE_SIZE (0)
    7055 #define USER_SIGNATURES_END       (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
     7472#define USER_SIGNATURES_END       (USER_SIGNATURES_START + \
     7473                                   USER_SIGNATURES_SIZE - 1)
    70567474
    70577475#define PROD_SIGNATURES_START     (0x0000)
    70587476#define PROD_SIGNATURES_SIZE      (52)
    70597477#define PROD_SIGNATURES_PAGE_SIZE (0)
    7060 #define PROD_SIGNATURES_END       (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
     7478#define PROD_SIGNATURES_END       (PROD_SIGNATURES_START + \
     7479                                   PROD_SIGNATURES_SIZE - 1)
    70617480
    70627481#define FLASHEND     PROGMEM_END
     
    70707489#define E2END        EEPROM_END
    70717490#define E2PAGESIZE   EEPROM_PAGE_SIZE
    7072 
    7073 
    7074 /* ========== Fuses ========== */
     7491/** @} */
     7492
     7493/**
     7494 * @name Fuses
     7495 *
     7496 * @{
     7497 */
    70757498#define FUSE_MEMORY_SIZE 6
    70767499
     
    70917514#define FUSE_WDP2  (unsigned char)~_BV(2)  /* Watchdog Timeout Period Bit 2 */
    70927515#define FUSE_WDP3  (unsigned char)~_BV(3)  /* Watchdog Timeout Period Bit 3 */
    7093 #define FUSE_WDWP0  (unsigned char)~_BV(4)  /* Watchdog Window Timeout Period Bit 0 */
    7094 #define FUSE_WDWP1  (unsigned char)~_BV(5)  /* Watchdog Window Timeout Period Bit 1 */
    7095 #define FUSE_WDWP2  (unsigned char)~_BV(6)  /* Watchdog Window Timeout Period Bit 2 */
    7096 #define FUSE_WDWP3  (unsigned char)~_BV(7)  /* Watchdog Window Timeout Period Bit 3 */
     7516/* Watchdog Window Timeout Period Bit 0 */
     7517#define FUSE_WDWP0  (unsigned char)~_BV(4)
     7518/* Watchdog Window Timeout Period Bit 1 */
     7519#define FUSE_WDWP1  (unsigned char)~_BV(5)
     7520/* Watchdog Window Timeout Period Bit 2 */
     7521#define FUSE_WDWP2  (unsigned char)~_BV(6)
     7522/* Watchdog Window Timeout Period Bit 3 */
     7523#define FUSE_WDWP3  (unsigned char)~_BV(7)
    70977524#define FUSE1_DEFAULT  (0xFF)
    70987525
    70997526/* Fuse Byte 2 */
    7100 #define FUSE_BODPD0  (unsigned char)~_BV(0)  /* BOD Operation in Power-Down Mode Bit 0 */
    7101 #define FUSE_BODPD1  (unsigned char)~_BV(1)  /* BOD Operation in Power-Down Mode Bit 1 */
    7102 #define FUSE_BODACT0  (unsigned char)~_BV(2)  /* BOD Operation in Active Mode Bit 0 */
    7103 #define FUSE_BODACT1  (unsigned char)~_BV(3)  /* BOD Operation in Active Mode Bit 1 */
    7104 #define FUSE_BOOTRST  (unsigned char)~_BV(6)  /* Boot Loader Section Reset Vector */
     7527/* BOD Operation in Power-Down Mode Bit 0 */
     7528#define FUSE_BODPD0  (unsigned char)~_BV(0)
     7529/* BOD Operation in Power-Down Mode Bit 1 */
     7530#define FUSE_BODPD1  (unsigned char)~_BV(1)
     7531/* BOD Operation in Active Mode Bit 0 */
     7532#define FUSE_BODACT0  (unsigned char)~_BV(2)
     7533/* BOD Operation in Active Mode Bit 1 */
     7534#define FUSE_BODACT1  (unsigned char)~_BV(3)
     7535/* Boot Loader Section Reset Vector */
     7536#define FUSE_BOOTRST  (unsigned char)~_BV(6)
    71057537#define FUSE_DVSDON  (unsigned char)~_BV(7)  /* Spike Detector Enable */
    71067538#define FUSE2_DEFAULT  (0xFF)
     
    71167548
    71177549/* Fuse Byte 5 */
    7118 #define FUSE_BODLVL0  (unsigned char)~_BV(0)  /* Brown Out Detection Voltage Level Bit 0 */
    7119 #define FUSE_BODLVL1  (unsigned char)~_BV(1)  /* Brown Out Detection Voltage Level Bit 1 */
    7120 #define FUSE_BODLVL2  (unsigned char)~_BV(2)  /* Brown Out Detection Voltage Level Bit 2 */
    7121 #define FUSE_EESAVE  (unsigned char)~_BV(3)  /* Preserve EEPROM Through Chip Erase */
     7550/* Brown Out Detection Voltage Level Bit 0 */
     7551#define FUSE_BODLVL0  (unsigned char)~_BV(0)
     7552/* Brown Out Detection Voltage Level Bit 1 */
     7553#define FUSE_BODLVL1  (unsigned char)~_BV(1)
     7554/* Brown Out Detection Voltage Level Bit 2 */
     7555#define FUSE_BODLVL2  (unsigned char)~_BV(2)
     7556/* Preserve EEPROM Through Chip Erase */
     7557#define FUSE_EESAVE  (unsigned char)~_BV(3)
    71227558#define FUSE5_DEFAULT  (0xFF)
    7123 
    7124 
    7125 /* ========== Lock Bits ========== */
     7559/** @} */
     7560
     7561/**
     7562 * @name Lock Bits
     7563 *
     7564 * @{
     7565 */
    71267566#define __LOCK_BITS_EXIST
    71277567#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
    71287568#define __BOOT_LOCK_APPLICATION_BITS_EXIST
    71297569#define __BOOT_LOCK_BOOT_BITS_EXIST
    7130 
    7131 
    7132 /* ========== Signature ========== */
     7570/** @} */
     7571
     7572/**
     7573 * @name Signature
     7574 *
     7575 * @{
     7576 */
    71337577#define SIGNATURE_0 0x1E
    71347578#define SIGNATURE_1 0x97
    71357579#define SIGNATURE_2 0x4C
    7136 
     7580/** @} */
    71377581
    71387582#endif /* _AVR_ATxmega128A1_H_ */
  • cpukit/score/cpu/avr/avr/portpins.h

    r2305f97 r455bd4e  
     1/**
     2 * @file
     3 *
     4 * @brief Define Generic PORTn, DDn, and PINn Values
     5 */
     6
    17/* Copyright (c) 2003  Theodore A. Roth
    28   All rights reserved.
     
    3945#endif
    4046
    41 /* Define Generic PORTn, DDn, and PINn values. */
    42 
    4347/* Port Data Register (generic) */
    4448#define    PORT7        7
     
    7175#define    PIN0         0
    7276
    73 /* Define PORTxn an Pxn values for all possible port pins if not defined already by io.h. */
     77/* Define PORTxn an Pxn values for all possible port pins
     78 * if not defined already by io.h.
     79 */
    7480
    7581/* PORT A */
  • cpukit/score/cpu/avr/avr/signature.h

    r2305f97 r455bd4e  
     1/**
     2 * @file
     3 *
     4 * @brief Signature Support
     5 */
     6
    17/* Copyright (c) 2009, Atmel Corporation
    28   All rights reserved.
     
    3541#define _AVR_SIGNATURE_H_ 1
    3642
    37 /** \file */
    38 /** \defgroup avr_signature <avr/signature.h>: Signature Support
    39 
    40     \par Introduction
    41 
    42    The <avr/signature.h> header file allows the user to automatically
    43    and easily include the device's signature data in a special section of
    44    the final linked ELF file.
    45     
    46     This value can then be used by programming software to compare the on-device
    47     signature with the signature recorded in the ELF file to look for a match
    48    before programming the device.
    49   
    50     \par API Usage Example
    51 
    52    Usage is very simple; just include the header file:
    53     
    54     \code
    55    #include <avr/signature.h>
    56     \endcode
    57     
    58    This will declare a constant unsigned char array and it is initialized with
    59    the three signature bytes, MSB first, that are defined in the device I/O
    60    header file. This array is then placed in the .signature section in the
    61    resulting linked ELF file.
    62   
    63    The three signature bytes that are used to initialize the array are
    64    these defined macros in the device I/O header file, from MSB to LSB:
    65    SIGNATURE_2, SIGNATURE_1, SIGNATURE_0.
    66   
    67    This header file should only be included once in an application.
    68 */
     43/**
     44 * @defgroup avr_signature Signature Support
     45 *
     46 * @par Introduction
     47 *
     48 * The <avr/signature.h> header file allows the user to automatically
     49 * and easily include the device's signature data in a special section of
     50 * the final linked ELF file.
     51 *
     52 * This value can then be used by programming software to compare the
     53 * on-device signature with the signature recorded in the ELF file
     54 * to look for a match before programming the device.
     55 *
     56 * @par API Usage Example
     57 *
     58 * Usage is very simple; just include the header file:
     59 *
     60 * @code{.c}
     61 * #include <avr/signature.h>
     62 * @endcode
     63 *
     64 * This will declare a constant unsigned char array and it is initialized with
     65 * the three signature bytes, MSB first, that are defined in the device I/O
     66 * header file. This array is then placed in the .signature section in the
     67 * resulting linked ELF file.
     68 *
     69 * The three signature bytes that are used to initialize the array are
     70 * these defined macros in the device I/O header file, from MSB to LSB:
     71 * SIGNATURE_2, SIGNATURE_1, SIGNATURE_0.
     72 *
     73 * This header file should only be included once in an application.
     74 */
    6975
    7076#ifndef __ASSEMBLER__
     
    7682const unsigned char __signature[3] __attribute__((section (".signature"))) =
    7783        { SIGNATURE_2, SIGNATURE_1, SIGNATURE_0 };
    78 
    79 #endif  /* defined(SIGNATURE_0) && defined(SIGNATURE_1) && defined(SIGNATURE_2) */
     84       
     85/* defined(SIGNATURE_0) && defined(SIGNATURE_1) && defined(SIGNATURE_2) */
     86#endif
    8087
    8188#endif  /* __ASSEMBLER__ */
  • cpukit/score/cpu/avr/avr/sleep.h

    r2305f97 r455bd4e  
     1/**
     2 * @file
     3 *
     4 * @brief Power Management and Sleep Modes
     5 *
     6 */
     7
    18/* Copyright (c) 2002, 2004 Theodore A. Roth
    29   Copyright (c) 2004, 2007, 2008 Eric B. Weddington
     
    3845#include <stdint.h>
    3946
    40 
    41 /** \file */
    42 
    43 /** \defgroup avr_sleep <avr/sleep.h>: Power Management and Sleep Modes
    44 
    45     \code #include <avr/sleep.h>\endcode
    46 
    47     Use of the \c SLEEP instruction can allow an application to reduce its
    48     power comsumption considerably. AVR devices can be put into different
    49     sleep modes. Refer to the datasheet for the details relating to the device
    50     you are using.
    51 
    52     There are several macros provided in this header file to actually
    53     put the device into sleep mode.  The simplest way is to optionally
    54     set the desired sleep mode using \c set_sleep_mode() (it usually
    55     defaults to idle mode where the CPU is put on sleep but all
    56     peripheral clocks are still running), and then call
    57     \c sleep_mode(). This macro automatically sets the sleep enable bit, goes
    58     to sleep, and clears the sleep enable bit.
    59    
    60     Example:
    61     \code
    62     #include <avr/sleep.h>
    63 
    64     ...
    65       set_sleep_mode(<mode>);
    66       sleep_mode();
    67     \endcode
    68    
    69     Note that unless your purpose is to completely lock the CPU (until a
    70     hardware reset), interrupts need to be enabled before going to sleep.
    71 
    72     As the \c sleep_mode() macro might cause race conditions in some
    73     situations, the individual steps of manipulating the sleep enable
    74     (SE) bit, and actually issuing the \c SLEEP instruction, are provided
    75     in the macros \c sleep_enable(), \c sleep_disable(), and
    76     \c sleep_cpu().  This also allows for test-and-sleep scenarios that
    77     take care of not missing the interrupt that will awake the device
    78     from sleep.
    79 
    80     Example:
    81     \code
    82     #include <avr/interrupt.h>
    83     #include <avr/sleep.h>
    84 
    85     ...
    86       set_sleep_mode(<mode>);
    87       cli();
    88       if (some_condition)
    89       {
    90         sleep_enable();
    91         sei();
    92         sleep_cpu();
    93         sleep_disable();
    94       }
    95       sei();
    96     \endcode
    97 
    98     This sequence ensures an atomic test of \c some_condition with
    99     interrupts being disabled.  If the condition is met, sleep mode
    100     will be prepared, and the \c SLEEP instruction will be scheduled
    101     immediately after an \c SEI instruction.  As the intruction right
    102     after the \c SEI is guaranteed to be executed before an interrupt
    103     could trigger, it is sure the device will really be put to sleep.
    104 
    105     Some devices have the ability to disable the Brown Out Detector (BOD) before
    106     going to sleep. This will also reduce power while sleeping. If the
    107     specific AVR device has this ability then an additional macro is defined:
    108     \c sleep_bod_disable(). This macro generates inlined assembly code
    109     that will correctly implement the timed sequence for disabling the BOD
    110     before sleeping. However, there is a limited number of cycles after the
    111     BOD has been disabled that the device can be put into sleep mode, otherwise
    112     the BOD will not truly be disabled. Recommended practice is to disable
    113     the BOD (\c sleep_bod_disable()), set the interrupts (\c sei()), and then
    114     put the device to sleep (\c sleep_cpu()), like so:
    115 
    116     \code
    117     #include <avr/interrupt.h>
    118     #include <avr/sleep.h>
    119 
    120     ...
    121       set_sleep_mode(<mode>);
    122       cli();
    123       if (some_condition)
    124       {
    125         sleep_enable();
    126         sleep_bod_disable();
    127         sei();
    128         sleep_cpu();
    129         sleep_disable();
    130       }
    131       sei();
    132     \endcode
    133 */
    134 
    135 
    136 /* Define an internal sleep control register and an internal sleep enable bit mask. */
     47/**
     48 * @defgroup avr_sleep Power Management and Sleep Modes
     49 *
     50 * Use of the @c SLEEP instruction can allow an application to reduce its
     51 * power comsumption considerably. AVR devices can be put into different
     52 * sleep modes. Refer to the datasheet for the details relating to the device
     53 * you are using.
     54 *
     55 * There are several macros provided in this header file to actually
     56 * put the device into sleep mode.  The simplest way is to optionally
     57 * set the desired sleep mode using @c set_sleep_mode() (it usually
     58 * defaults to idle mode where the CPU is put on sleep but all
     59 * peripheral clocks are still running), and then call
     60 * @c sleep_mode(). This macro automatically sets the sleep enable bit, goes
     61 * to sleep, and clears the sleep enable bit.
     62 *   
     63 * Example:
     64 * @code{.c}
     65 * #include <avr/sleep.h>
     66 *
     67 * ...
     68 *   set_sleep_mode(<mode>);
     69 *   sleep_mode();
     70 * @endcode
     71 *   
     72 * Note that unless your purpose is to completely lock the CPU (until a
     73 * hardware reset), interrupts need to be enabled before going to sleep.
     74 *
     75 * As the @c sleep_mode() macro might cause race conditions in some
     76 * situations, the individual steps of manipulating the sleep enable
     77 * (SE) bit, and actually issuing the @c SLEEP instruction, are provided
     78 * in the macros @c sleep_enable(), @c sleep_disable(), and
     79 * @c sleep_cpu().  This also allows for test-and-sleep scenarios that
     80 * take care of not missing the interrupt that will awake the device
     81 * from sleep.
     82 *
     83 * Example:
     84 * @code{.c}
     85 * #include <avr/interrupt.h>
     86 * #include <avr/sleep.h>*
     87 *
     88 * ...
     89 *   set_sleep_mode(<mode>);
     90 *   cli();
     91 *   if (some_condition)
     92 *   {
     93 *     sleep_enable();
     94 *     sei();
     95 *     sleep_cpu();
     96 *     sleep_disable();
     97 *   }
     98 *   sei();
     99 * @endcode
     100 *
     101 * This sequence ensures an atomic test of @c some_condition with
     102 * interrupts being disabled.  If the condition is met, sleep mode
     103 * will be prepared, and the @c SLEEP instruction will be scheduled
     104 * immediately after an @c SEI instruction.  As the intruction right
     105 * after the @c SEI is guaranteed to be executed before an interrupt
     106 * could trigger, it is sure the device will really be put to sleep.
     107 *
     108 * Some devices have the ability to disable the Brown Out Detector (BOD)
     109 * before going to sleep. This will also reduce power while sleeping. If the
     110 * specific AVR device has this ability then an additional macro is defined:
     111 * @c sleep_bod_disable(). This macro generates inlined assembly code
     112 * that will correctly implement the timed sequence for disabling the BOD
     113 * before sleeping. However, there is a limited number of cycles after the
     114 * BOD has been disabled that the device can be put into sleep mode, otherwise
     115 * the BOD will not truly be disabled. Recommended practice is to disable
     116 * the BOD (@c sleep_bod_disable()), set the interrupts (@c sei()), and then
     117 * put the device to sleep (@c sleep_cpu()), like so:
     118 *
     119 * @code{.c}
     120 * #include <avr/interrupt.h>
     121 * #include <avr/sleep.h>*
     122 *
     123 * ...
     124 *   set_sleep_mode(<mode>);
     125 *   cli();
     126 *   if (some_condition)
     127 *   {
     128 *     sleep_enable();
     129 *     sleep_bod_disable();
     130 *     sei();
     131 *     sleep_cpu();
     132 *     sleep_disable();
     133 *  }
     134 *   sei();
     135 * @endcode
     136 *
     137 * @{
     138 */
     139
     140
     141/*
     142 * Define an internal sleep control register and
     143 * an internal sleep enable bit mask.
     144 */
    137145#if defined(SLEEP_CTRL)
    138146
     
    168176    #define set_sleep_mode(mode) \
    169177    do { \
    170         MCUCR = ((MCUCR & ~_BV(SM1)) | ((mode) == SLEEP_MODE_PWR_DOWN || (mode) == SLEEP_MODE_PWR_SAVE ? _BV(SM1) : 0)); \
    171         EMCUCR = ((EMCUCR & ~_BV(SM0)) | ((mode) == SLEEP_MODE_PWR_SAVE ? _BV(SM0) : 0)); \
     178        MCUCR = ((MCUCR & ~_BV(SM1)) | \
     179        ((mode) == SLEEP_MODE_PWR_DOWN || \
     180        (mode) == SLEEP_MODE_PWR_SAVE ? _BV(SM1) : 0)); \
     181        EMCUCR = ((EMCUCR & ~_BV(SM0)) | \
     182        ((mode) == SLEEP_MODE_PWR_SAVE ? _BV(SM0) : 0)); \
    172183    } while(0)
    173184
     
    185196    #define set_sleep_mode(mode) \
    186197    do { \
    187         MCUCR = ((MCUCR & ~_BV(SM1)) | ((mode) == SLEEP_MODE_IDLE ? 0 : _BV(SM1))); \
    188         MCUCSR = ((MCUCSR & ~_BV(SM2)) | ((mode) == SLEEP_MODE_STANDBY  || (mode) == SLEEP_MODE_EXT_STANDBY ? _BV(SM2) : 0)); \
    189         EMCUCR = ((EMCUCR & ~_BV(SM0)) | ((mode) == SLEEP_MODE_PWR_SAVE || (mode) == SLEEP_MODE_EXT_STANDBY ? _BV(SM0) : 0)); \
     198        MCUCR = ((MCUCR & ~_BV(SM1)) | \
     199        ((mode) == SLEEP_MODE_IDLE ? 0 : _BV(SM1))); \
     200        MCUCSR = ((MCUCSR & ~_BV(SM2)) | ((mode) == SLEEP_MODE_STANDBY  || \
     201        (mode) == SLEEP_MODE_EXT_STANDBY ? _BV(SM2) : 0)); \
     202        EMCUCR = ((EMCUCR & ~_BV(SM0)) | ((mode) == SLEEP_MODE_PWR_SAVE || \
     203        (mode) == SLEEP_MODE_EXT_STANDBY ? _BV(SM0) : 0)); \
    190204    } while(0)
    191205
     
    218232    #define set_sleep_mode(mode) \
    219233    do { \
    220         _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
     234        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG &  \
     235        ~(_BV(SM0) | _BV(SM1))) | (mode)); \
    221236    } while(0)
    222237
     
    254269    #define set_sleep_mode(mode) \
    255270    do { \
    256         _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
     271        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
     272        ~(_BV(SM0) | _BV(SM1))) | (mode)); \
    257273    } while(0)
    258274
     
    267283    #define set_sleep_mode(mode) \
    268284    do { \
    269         _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
     285        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
     286        ~(_BV(SM0) | _BV(SM1))) | (mode)); \
    270287    } while(0)
    271288
     
    278295    #define set_sleep_mode(mode) \
    279296    do { \
    280         _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
     297        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
     298        ~(_BV(SM0) | _BV(SM1))) | (mode)); \
    281299    } while(0)
    282300
     
    291309    #define set_sleep_mode(mode) \
    292310    do { \
    293         _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
     311        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
     312        ~(_BV(SM0) | _BV(SM1))) | (mode)); \
    294313    } while(0)
    295314
     
    305324    #define set_sleep_mode(mode) \
    306325    do { \
    307         _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
     326        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
     327        ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
    308328    } while(0)
    309329
     
    416436    #define set_sleep_mode(mode) \
    417437    do { \
    418         _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
     438        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
     439        ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
    419440    } while(0)
    420441
     
    439460    #define SLEEP_MODE_PWR_SAVE     (SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)
    440461    #define SLEEP_MODE_STANDBY      (SLEEP_SMODE2_bm | SLEEP_SMODE1_bm)
    441     #define SLEEP_MODE_EXT_STANDBY  (SLEEP_SMODE2_bm | SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)
    442 
    443     #define set_sleep_mode(mode) \
    444     do { \
    445         _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(SLEEP_SMODE2_bm | SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)) | (mode)); \
     462    #define SLEEP_MODE_EXT_STANDBY  (SLEEP_SMODE2_bm | SLEEP_SMODE1_bm | \
     463                                     SLEEP_SMODE0_bm)
     464
     465    #define set_sleep_mode(mode) \
     466    do { \
     467        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
     468        ~(SLEEP_SMODE2_bm | SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)) | (mode)); \
    446469    } while(0)
    447470
     
    456479    #define set_sleep_mode(mode) \
    457480    do { \
    458         _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
     481        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
     482        ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
    459483    } while(0)
    460484
     
    467491    #define set_sleep_mode(mode) \
    468492    do { \
    469         _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
     493        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
     494        ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
    470495    } while(0)
    471496
     
    478503
    479504
    480 /** \ingroup avr_sleep
    481 
    482     Put the device in sleep mode. How the device is brought out of sleep mode
    483     depends on the specific mode selected with the set_sleep_mode() function.
    484     See the data sheet for your device for more details. */
     505/**
     506 * Put the device in sleep mode. How the device is brought out of sleep mode
     507 * depends on the specific mode selected with the set_sleep_mode() function.
     508 * See the data sheet for your device for more details.
     509 */
    485510
    486511
    487512#if defined(__DOXYGEN__)
    488513
    489 /** \ingroup avr_sleep
    490 
    491     Set the SE (sleep enable) bit.
     514/**
     515 * Set the SE (sleep enable) bit.
    492516*/
    493517extern void sleep_enable (void);
     
    505529#if defined(__DOXYGEN__)
    506530
    507 /** \ingroup avr_sleep
    508 
    509     Clear the SE (sleep enable) bit.
    510 */
     531/**
     532 * Clear the SE (sleep enable) bit.
     533 */
    511534extern void sleep_disable (void);
    512535
     
    521544
    522545
    523 /** \ingroup avr_sleep
    524 
    525     Put the device into sleep mode.  The SE bit must be set
    526     beforehand, and it is recommended to clear it afterwards.
    527 */
     546/**
     547 * Put the device into sleep mode.  The SE bit must be set
     548 * beforehand, and it is recommended to clear it afterwards.
     549 */
    528550#if defined(__DOXYGEN__)
    529551
     
    583605
    584606
    585 /*@}*/
     607/** @} */
    586608
    587609#endif /* _AVR_SLEEP_H_ */
  • cpukit/score/cpu/avr/avr/wdt.h

    r2305f97 r455bd4e  
     1/**
     2 * @file
     3 *
     4 * @brief Watchdog Timer Handling
     5 */
    16/* Copyright (c) 2002, 2004 Marek Michalkiewicz
    27   Copyright (c) 2005, 2006, 2007 Eric B. Weddington
     
    4146#include <stdint.h>
    4247
    43 /** \file */
    44 /** \defgroup avr_watchdog <avr/wdt.h>: Watchdog timer handling
    45     \code #include <avr/wdt.h> \endcode
    46 
    47     This header file declares the interface to some inline macros
    48     handling the watchdog timer present in many AVR devices.  In order
    49     to prevent the watchdog timer configuration from being
    50     accidentally altered by a crashing application, a special timed
    51     sequence is required in order to change it.  The macros within
    52     this header file handle the required sequence automatically
    53     before changing any value.  Interrupts will be disabled during
    54     the manipulation.
    55 
    56     \note Depending on the fuse configuration of the particular
    57     device, further restrictions might apply, in particular it might
    58     be disallowed to turn off the watchdog timer.
    59 
    60     Note that for newer devices (ATmega88 and newer, effectively any
    61     AVR that has the option to also generate interrupts), the watchdog
    62     timer remains active even after a system reset (except a power-on
    63     condition), using the fastest prescaler value (approximately 15
    64     ms).  It is therefore required to turn off the watchdog early
    65     during program startup, the datasheet recommends a sequence like
    66     the following:
    67 
    68     \code
    69     #include <stdint.h>
    70     #include <avr/wdt.h>
    71 
    72     uint8_t mcusr_mirror __attribute__ ((section (".noinit")));
    73 
    74     void get_mcusr(void) \
    75       __attribute__((naked)) \
    76       __attribute__((section(".init3")));
    77     void get_mcusr(void)
    78     {
    79       mcusr_mirror = MCUSR;
    80       MCUSR = 0;
    81       wdt_disable();
    82     }
    83     \endcode
    84 
    85     Saving the value of MCUSR in \c mcusr_mirror is only needed if the
    86     application later wants to examine the reset source, but in particular,
    87     clearing the watchdog reset flag before disabling the
    88     watchdog is required, according to the datasheet.
    89 */
    90 
    91 /**
    92    \ingroup avr_watchdog
    93    Reset the watchdog timer.  When the watchdog timer is enabled,
    94    a call to this instruction is required before the timer expires,
    95    otherwise a watchdog-initiated device reset will occur.
     48/**
     49 * @defgroup avr_watchdog Watchdog Timer Handling
     50 *
     51 * This header file declares the interface to some inline macros
     52 * handling the watchdog timer present in many AVR devices.  In order
     53 * to prevent the watchdog timer configuration from being
     54 * accidentally altered by a crashing application, a special timed
     55 * equence is required in order to change it.  The macros within
     56 * this header file handle the required sequence automatically
     57 * before changing any value.  Interrupts will be disabled during
     58 * the manipulation.
     59 *
     60 * Note: Depending on the fuse configuration of the particular
     61 * device, further restrictions might apply, in particular it might
     62 * be disallowed to turn off the watchdog timer.
     63 *
     64 * Note that for newer devices (ATmega88 and newer, effectively any
     65 * AVR that has the option to also generate interrupts), the watchdog
     66 * timer remains active even after a system reset (except a power-on
     67 * condition), using the fastest prescaler value (approximately 15
     68 * ms).  It is therefore required to turn off the watchdog early
     69 * during program startup, the datasheet recommends a sequence like
     70 * the following:
     71 *
     72 * @code{.c}
     73 * #include <stdint.h>
     74 * #include <avr/wdt.h>
     75 *
     76 * uint8_t mcusr_mirror __attribute__ ((section (".noinit")));
     77 *
     78 * void get_mcusr(void) \
     79 *   __attribute__((naked)) \
     80 *   __attribute__((section(".init3")));
     81 * void get_mcusr(void)
     82 * {
     83 *   mcusr_mirror = MCUSR;
     84 *   MCUSR = 0;
     85 *   wdt_disable();
     86 * }
     87 * @endcode
     88 *
     89 * Saving the value of MCUSR in @c mcusr_mirror is only needed if the
     90 * application later wants to examine the reset source, but in particular,
     91 * clearing the watchdog reset flag before disabling the
     92 * watchdog is required, according to the datasheet.
     93 * @{
     94*/
     95
     96/**
     97 * @brief Watchdog Timer Reset
     98 *
     99 * Reset the watchdog timer.  When the watchdog timer is enabled,
     100 * a call to this instruction is required before the timer expires,
     101 * otherwise a watchdog-initiated device reset will occur.
    96102*/
    97103
     
    119125
    120126/**
    121    \ingroup avr_watchdog
    122    Enable the watchdog timer, configuring it for expiry after
    123    \c timeout (which is a combination of the \c WDP0 through
    124    \c WDP2 bits to write into the \c WDTCR register; For those devices
    125    that have a \c WDTCSR register, it uses the combination of the \c WDP0
    126    through \c WDP3 bits).
    127 
    128    See also the symbolic constants \c WDTO_15MS et al.
     127 * Enable the watchdog timer, configuring it for expiry after
     128 * @c timeout (which is a combination of the @c WDP0 through
     129 * @c WDP2 bits to write into the @c WDTCR register; For those devices
     130 * that have a @c WDTCSR register, it uses the combination of the @c WDP0
     131 * through @c WDP3 bits).
     132 *
     133 * See also the symbolic constants @c WDTO_15MS et al.
    129134*/
    130135
     
    318323
    319324/**
    320    \ingroup avr_watchdog
    321    Disable the watchdog timer, if possible.  This attempts to turn off the
    322    Enable bit in the watchdog control register. See the datasheet for
    323    details.
     325 *  Disable the watchdog timer, if possible.  This attempts to turn off the
     326 *  Enable bit in the watchdog control register. See the datasheet for
     327 *  details.
    324328*/
    325329#define wdt_disable() \
     
    341345
    342346/**
    343    \ingroup avr_watchdog
    344    Symbolic constants for the watchdog timeout.  Since the watchdog
    345    timer is based on a free-running RC oscillator, the times are
    346    approximate only and apply to a supply voltage of 5 V.  At lower
    347    supply voltages, the times will increase.  For older devices, the
    348    times will be as large as three times when operating at Vcc = 3 V,
    349    while the newer devices (e. g. ATmega128, ATmega8) only experience
    350    a negligible change.
    351 
    352    Possible timeout values are: 15 ms, 30 ms, 60 ms, 120 ms, 250 ms,
    353    500 ms, 1 s, 2 s.  (Some devices also allow for 4 s and 8 s.)
    354    Symbolic constants are formed by the prefix
    355    \c WDTO_, followed by the time.
    356 
    357    Example that would select a watchdog timer expiry of approximately
    358    500 ms:
    359    \code
    360    wdt_enable(WDTO_500MS);
    361    \endcode
     347 *  Symbolic constants for the watchdog timeout.  Since the watchdog
     348 *  timer is based on a free-running RC oscillator, the times are
     349 *  approximate only and apply to a supply voltage of 5 V.  At lower
     350 *  supply voltages, the times will increase.  For older devices, the
     351 *  times will be as large as three times when operating at Vcc = 3 V,
     352 *  while the newer devices (e. g. ATmega128, ATmega8) only experience
     353 *  a negligible change.
     354 *
     355 *  Possible timeout values are: 15 ms, 30 ms, 60 ms, 120 ms, 250 ms,
     356 *  500 ms, 1 s, 2 s.  (Some devices also allow for 4 s and 8 s.)
     357 *  Symbolic constants are formed by the prefix
     358 *  @c WDTO_, followed by the time.
     359 *
     360 *  Example that would select a watchdog timer expiry of approximately
     361 *  500 ms:
     362 *
     363 *  @code{.c}
     364 *  wdt_enable(WDTO_500MS);
     365 *  @endcode
    362366*/
    363367#define WDTO_15MS   0
    364368
    365 /** \ingroup avr_watchdog
    366     See \c WDT0_15MS */
     369/** @see WDT0_15MS */
    367370#define WDTO_30MS   1
    368371
    369 /** \ingroup avr_watchdog See
    370     \c WDT0_15MS */
     372/** @see WDT0_15MS */
    371373#define WDTO_60MS   2
    372374
    373 /** \ingroup avr_watchdog
    374     See \c WDT0_15MS */
     375/** @see WDT0_15MS */
    375376#define WDTO_120MS  3
    376377
    377 /** \ingroup avr_watchdog
    378     See \c WDT0_15MS */
     378/** @see WDT0_15MS */
    379379#define WDTO_250MS  4
    380380
    381 /** \ingroup avr_watchdog
    382     See \c WDT0_15MS */
     381/** @see WDT0_15MS */
    383382#define WDTO_500MS  5
    384383
    385 /** \ingroup avr_watchdog
    386     See \c WDT0_15MS */
     384/** @see WDT0_15MS */
    387385#define WDTO_1S     6
    388386
    389 /** \ingroup avr_watchdog
    390     See \c WDT0_15MS */
     387/** @see WDT0_15MS */
    391388#define WDTO_2S     7
    392389
    393390#if defined(__DOXYGEN__) || defined(WDP3)
    394391
    395 /** \ingroup avr_watchdog
    396     See \c WDT0_15MS
    397     Note: This is only available on the
    398     ATtiny2313,
    399     ATtiny24, ATtiny44, ATtiny84,
    400     ATtiny25, ATtiny45, ATtiny85,
    401     ATtiny261, ATtiny461, ATtiny861,
    402     ATmega48, ATmega88, ATmega168,
    403     ATmega48P, ATmega88P, ATmega168P, ATmega328P,
    404     ATmega164P, ATmega324P, ATmega644P, ATmega644,
    405     ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561,
    406     ATmega8HVA, ATmega16HVA, ATmega32HVB,
    407     ATmega406, ATmega1284P,
    408     AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316,
    409     AT90PWM81,
    410     AT90USB82, AT90USB162,
    411     AT90USB646, AT90USB647, AT90USB1286, AT90USB1287,
    412     ATtiny48, ATtiny88.
    413     */
     392/**
     393 * @see WDT0_15MS
     394 *
     395 * Note: This is only available on:
     396 * ATtiny2313,
     397 * ATtiny24, ATtiny44, ATtiny84,
     398 * ATtiny25, ATtiny45, ATtiny85,
     399 * ATtiny261, ATtiny461, ATtiny861,
     400 * ATmega48, ATmega88, ATmega168,
     401 * ATmega48P, ATmega88P, ATmega168P, ATmega328P,
     402 * ATmega164P, ATmega324P, ATmega644P, ATmega644,
     403 * ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561,
     404 * ATmega8HVA, ATmega16HVA, ATmega32HVB,
     405 * ATmega406, ATmega1284P,
     406 * AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316,
     407 * AT90PWM81,
     408 * AT90USB82, AT90USB162,
     409 * AT90USB646, AT90USB647, AT90USB1286, AT90USB1287,
     410 * ATtiny48, ATtiny88.
     411 */
    414412#define WDTO_4S     8
    415413
    416 /** \ingroup avr_watchdog
    417     See \c WDT0_15MS
    418     Note: This is only available on the
    419     ATtiny2313,
    420     ATtiny24, ATtiny44, ATtiny84,
    421     ATtiny25, ATtiny45, ATtiny85,
    422     ATtiny261, ATtiny461, ATtiny861,
    423     ATmega48, ATmega88, ATmega168,
    424     ATmega48P, ATmega88P, ATmega168P, ATmega328P,
    425     ATmega164P, ATmega324P, ATmega644P, ATmega644,
    426     ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561,
    427     ATmega8HVA, ATmega16HVA, ATmega32HVB,
    428     ATmega406, ATmega1284P,
    429     AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316,
    430     AT90PWM81,
    431     AT90USB82, AT90USB162,
    432     AT90USB646, AT90USB647, AT90USB1286, AT90USB1287,
    433     ATtiny48, ATtiny88.
    434     */
     414/** @see WDTO_4S */
    435415#define WDTO_8S     9
    436416
    437417#endif  /* defined(__DOXYGEN__) || defined(WDP3) */
    438    
     418/** @} */   
    439419
    440420#endif /* _AVR_WDT_H_ */
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