Changeset 44fbca3 in rtems


Ignore:
Timestamp:
Jun 4, 2014, 9:21:43 AM (7 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, 5, master
Children:
66a2409d
Parents:
d0a8f513
git-author:
Sebastian Huber <sebastian.huber@…> (06/04/14 09:21:43)
git-committer:
Sebastian Huber <sebastian.huber@…> (06/05/14 12:55:16)
Message:

bsps/arm: Simplify L1 caches support

Delete superfluous/incorrect interrupt disable/enable.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h

    rd0a8f513 r44fbca3  
    123123static inline void arm_cache_l1_flush_entire_data( void )
    124124{
    125   uint32_t              l1LineSize, l1Associativity, l1NumSets;
    126   uint32_t              s, w;
    127   uint32_t              set_way_param;
    128   rtems_interrupt_level level;
    129 
     125  uint32_t l1LineSize, l1Associativity, l1NumSets;
     126  uint32_t s, w;
     127  uint32_t set_way_param;
    130128
    131129  /* ensure ordering with previous memory accesses */
    132130  _ARM_Data_memory_barrier();
    133 
    134   /* make cssr&csidr read atomic */
    135   rtems_interrupt_disable( level );
    136131
    137132  /* Get the L1 cache properties */
    138133  arm_cache_l1_properties( &l1LineSize, &l1Associativity,
    139134                                     &l1NumSets );
    140   rtems_interrupt_enable( level );
    141135
    142136  for ( w = 0; w < l1Associativity; ++w ) {
     
    159153static inline void arm_cache_l1_invalidate_entire_data( void )
    160154{
    161   uint32_t              l1LineSize, l1Associativity, l1NumSets;
    162   uint32_t              s, w;
    163   uint32_t              set_way_param;
    164   rtems_interrupt_level level;
    165 
     155  uint32_t l1LineSize, l1Associativity, l1NumSets;
     156  uint32_t s, w;
     157  uint32_t set_way_param;
    166158
    167159  /* ensure ordering with previous memory accesses */
    168160  _ARM_Data_memory_barrier();
    169 
    170   /* make cssr&csidr read atomic */
    171   rtems_interrupt_disable( level );
    172161
    173162  /* Get the L1 cache properties */
    174163  arm_cache_l1_properties( &l1LineSize, &l1Associativity,
    175164                                     &l1NumSets );
    176   rtems_interrupt_enable( level );
    177165
    178166  for ( w = 0; w < l1Associativity; ++w ) {
     
    195183static inline void arm_cache_l1_clean_and_invalidate_entire_data( void )
    196184{
    197   uint32_t              l1LineSize, l1Associativity, l1NumSets;
    198   uint32_t              s, w;
    199   uint32_t              set_way_param;
    200   rtems_interrupt_level level;
    201 
     185  uint32_t l1LineSize, l1Associativity, l1NumSets;
     186  uint32_t s, w;
     187  uint32_t set_way_param;
    202188
    203189  /* ensure ordering with previous memory accesses */
    204190  _ARM_Data_memory_barrier();
    205191
    206   /* make cssr&csidr read atomic */
    207   rtems_interrupt_disable( level );
    208192
    209193  /* Get the L1 cache properties */
    210194  arm_cache_l1_properties( &l1LineSize, &l1Associativity,
    211195                                     &l1NumSets );
    212   rtems_interrupt_enable( level );
    213196
    214197  for ( w = 0; w < l1Associativity; ++w ) {
     
    372355static inline void arm_cache_l1_enable_data( void )
    373356{
    374   rtems_interrupt_level level;
    375   uint32_t              ctrl;
    376 
     357  uint32_t ctrl;
    377358
    378359  arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_DATA );
     
    380361  assert( ARM_CACHE_L1_CPU_DATA_ALIGNMENT == arm_cp15_get_data_cache_line_size() );
    381362
    382   rtems_interrupt_disable( level );
    383363  ctrl = arm_cp15_get_control();
    384   rtems_interrupt_enable( level );
    385364
    386365  /* Only enable the cache if it is disabled */
     
    392371    ctrl |= ARM_CP15_CTRL_C;
    393372
    394     rtems_interrupt_disable( level );
    395373    arm_cp15_set_control( ctrl );
    396     rtems_interrupt_enable( level );
    397374  }
    398375}
     
    400377static inline void arm_cache_l1_disable_data( void )
    401378{
    402   rtems_interrupt_level level;
    403 
    404 
    405379  /* Clean and invalidate the Data cache */
    406380  arm_cache_l1_flush_entire_data();
    407381
    408   rtems_interrupt_disable( level );
    409 
    410382  /* Disable the Data cache */
    411383  arm_cp15_set_control( arm_cp15_get_control() & ~ARM_CP15_CTRL_C );
    412 
    413   rtems_interrupt_enable( level );
    414384}
    415385
    416386static inline void arm_cache_l1_disable_instruction( void )
    417387{
    418   rtems_interrupt_level level;
    419 
    420 
    421   rtems_interrupt_disable( level );
    422 
    423388  /* Synchronize the processor */
    424389  _ARM_Data_synchronization_barrier();
     
    429394  /* Disable the Instruction cache */
    430395  arm_cp15_set_control( arm_cp15_get_control() & ~ARM_CP15_CTRL_I );
    431 
    432   rtems_interrupt_enable( level );
    433396}
    434397
    435398static inline void arm_cache_l1_enable_instruction( void )
    436399{
    437   rtems_interrupt_level level;
    438   uint32_t              ctrl;
    439 
     400  uint32_t ctrl;
    440401
    441402  arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_INSTRUCTION );
     
    443404  assert( ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT
    444405          == arm_cp15_get_data_cache_line_size() );
    445 
    446   rtems_interrupt_disable( level );
    447406
    448407  /* Enable Instruction cache only if it is disabled */
     
    458417    arm_cp15_set_control( ctrl );
    459418  }
    460 
    461   rtems_interrupt_enable( level );
    462419
    463420  arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_DATA );
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