Changeset 44c2d393 in rtems


Ignore:
Timestamp:
Jul 27, 2018, 1:04:38 PM (13 months ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
334e1d2
Parents:
cfc9573
git-author:
Sebastian Huber <sebastian.huber@…> (07/27/18 13:04:38)
git-committer:
Sebastian Huber <sebastian.huber@…> (07/27/18 13:06:55)
Message:

bsp/riscv: Fix inter-processor interrupts

The previous version worked only on a patched Qemu. Writes to mip are
illegal according to the The RISC-V Instruction Set Manual, Volume II:
Privileged Architecture, Privileged Architecture Version 1.10.

Update #3433.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • bsps/riscv/riscv/irq/irq.c

    rcfc9573 r44c2d393  
    9191  } else if (mcause == (RISCV_INTERRUPT_SOFTWARE_MACHINE << 1)) {
    9292#ifdef RTEMS_SMP
    93     clear_csr(mip, MIP_MSIP);
     93    /*
     94     * Clear the software interrupt on this processor.  Synchronization of
     95     * inter-processor interrupts is done via Per_CPU_Control::message in
     96     * _SMP_Inter_processor_interrupt_handler().
     97     */
     98    *cpu_self->cpu_per_cpu.clint_msip = 0;
     99
    94100    _SMP_Inter_processor_interrupt_handler(cpu_self);
    95101#else
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