Changeset 44b06ca in rtems


Ignore:
Timestamp:
Nov 29, 2009, 3:33:28 PM (9 years ago)
Author:
Ralf Corsepius <ralf.corsepius@…>
Branches:
4.10, 4.11, master
Children:
b1274bd9
Parents:
efdfd48
Message:

Whitespace removal.

Location:
c/src/lib/libbsp/sparc
Files:
69 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/sparc/erc32/clock/ckinit.c

    refdfd48 r44b06ca  
    5353  clicks = ERC32_MEC.Real_Time_Clock_Counter;
    5454
    55   return (uint32_t) 
     55  return (uint32_t)
    5656    (rtems_configuration_get_microseconds_per_tick() - clicks) * 1000;
    5757}
  • c/src/lib/libbsp/sparc/erc32/startup/spurious.c

    refdfd48 r44b06ca  
    6464      break;
    6565    case 0x09:
    66       printk("data access exception at 0x%08x\n", 
     66      printk("data access exception at 0x%08x\n",
    6767        ERC32_MEC.First_Failing_Address );
    6868      break;
  • c/src/lib/libbsp/sparc/leon2/cchip/cchip.c

    refdfd48 r44b06ca  
    5353        unsigned int bar3;
    5454        unsigned int bar4;/* 0x10 */
    55        
     55
    5656        unsigned int unused[4*3-1];
    57        
     57
    5858        unsigned int ambabars[1]; /* 0x40 */
    5959} amba_bridge_regs;
     
    6666        unsigned int bar3;
    6767        unsigned int bar4; /* 0x10 */
    68        
     68
    6969        unsigned int ilevel;
    7070        unsigned int ipend;
     
    7878        pci_bridge_regs  *pcib;
    7979        amba_bridge_regs *ambab;
    80        
     80
    8181        /* AT697 PCI */
    8282        unsigned int bars[5];
    8383        int bus, dev, fun;
    84        
     84
    8585        /* AMBA bus */
    8686        amba_confarea_type amba_bus;
    8787        struct amba_mmap amba_maps[2];
    88        
     88
    8989        /* FT AHB SRAM */
    9090        int ftsram_size; /* kb */
    9191        unsigned int ftsram_start;
    9292        unsigned int ftsram_end;
    93        
     93
    9494} cchip1;
    9595
     
    103103        int amba_master_cnt;
    104104        amba_confarea_type *abus;
    105  
     105
    106106  if ( BSP_pciFindDevice(0x1AC8, 0x0701, 0, &bus, &dev, &fun) == 0 ) {
    107107    ;
     
    112112    return -1;
    113113  }
    114  
     114
    115115  /* found Companionship PCI board, Set it up: */
    116  
     116
    117117        pci_read_config_dword(bus, dev, fun, 0x10, &cc1.bars[0]);
    118118        pci_read_config_dword(bus, dev, fun, 0x14, &cc1.bars[1]);
     
    120120        pci_read_config_dword(bus, dev, fun, 0x1c, &cc1.bars[3]);
    121121        pci_read_config_dword(bus, dev, fun, 0x20, &cc1.bars[4]);
    122                        
     122
    123123#ifdef DEBUG
    124124        for(i=0; i<5; i++){
     
    139139        cc1.amba_maps[0].cpu_adr = cc1.bars[1];
    140140        cc1.amba_maps[0].remote_amba_adr = 0xfc000000;
    141                
     141
    142142        /* Mark end of table */
    143143        cc1.amba_maps[1].size=0;
     
    150150        pci_write_config_dword(bus, dev, fun, 0x4, com1);
    151151        pci_read_config_dword(bus, dev, fun, 0x4, &com1);
    152                
     152
    153153        /* Set up AMBA Masters ==> PCI */
    154154        ambab = (void *)(cc1.bars[1]+0x400);
     
    158158        printk("AMBA: PCIBAR[%d]: 0x%x, 0x%x\n\r",2,ambab->bar2,pcib->bar2);
    159159#endif
    160         ambab->ambabars[0] = 0x40000000; /* 0xe0000000(AMBA) ==> 0x40000000(PCI) ==> 0x40000000(AT697 AMBA) */         
    161        
     160        ambab->ambabars[0] = 0x40000000; /* 0xe0000000(AMBA) ==> 0x40000000(PCI) ==> 0x40000000(AT697 AMBA) */
     161
    162162        /* Scan bus for AMBA devices */
    163163        abus = &cc1.amba_bus;
    164164        memset(abus,0,sizeof(amba_confarea_type));
    165165        amba_scan(abus,cc1.bars[1]+0x3f00000,&cc1.amba_maps[0]);
    166        
     166
    167167        /* Get number of amba masters */
    168168        amba_master_cnt = abus->ahbmst.devnr;
    169 #ifdef BOARD_INFO               
     169#ifdef BOARD_INFO
    170170        printk("Found %d AMBA masters\n\r",amba_master_cnt);
    171171#endif
     
    173173                ambab->ambabars[i] = 0x40000000;
    174174        }
    175        
     175
    176176        /* Enable PCI Master */
    177177   pci_read_config_dword(bus, dev, fun, 0x4, &com1);
    178178   com1 |= 0x4;
    179179   pci_write_config_dword(bus, dev, fun, 0x4, com1);
    180    pci_read_config_dword(bus, dev, fun, 0x4, &com1);           
    181        
     180   pci_read_config_dword(bus, dev, fun, 0x4, &com1);
     181
    182182        cc1.pcib  = pcib;
    183183        cc1.ambab = ambab;
     
    185185        cc1.dev = dev;
    186186        cc1.fun = fun;
    187        
     187
    188188        return 0;
    189189}
     
    196196        amba_apb_device apb;
    197197        unsigned int conf, size;
    198        
    199         /* Find SRAM controller 
     198
     199        /* Find SRAM controller
    200200         * 1. AHB slave interface
    201201         * 2. APB slave interface
     
    205205                return -1;
    206206        }
    207        
     207
    208208        if ( amba_find_ahbslv(&cc1.amba_bus,VENDOR_GAISLER,GAISLER_FTAHBRAM,&ahb) != 1 ){
    209209                printk("On Board FT SRAM not found (AHB)\n");
    210210                return -1;
    211211        }
    212        
     212
    213213        /* We have found the controller.
    214214         * Get it going.
    215215         *
    216          * Get size of SRAM 
     216         * Get size of SRAM
    217217         */
    218218        conf = *(unsigned int *)apb.start;
    219219        size = (conf >>10) & 0x7;
    220        
     220
    221221        /* 2^x kb */
    222222        cc1.ftsram_size = 1<<size;
     
    230230
    231231int cchip1_register(void){
    232        
     232
    233233        /* Init AT697 PCI Controller */
    234234        init_pci();
    235        
     235
    236236        /* Find & init CChip board .
    237237         * Also scan AMBA Plug&Play info for us.
     
    244244        /* Set interrupt common board stuff */
    245245        cchip1_irq_init();
    246        
     246
    247247        /* Find on board SRAM */
    248248        if ( init_onboard_sram() ){
     
    250250                return -1;
    251251        }
    252        
     252
    253253        /* Register interrupt install functions */
    254254        b1553brm_pci_int_reg = cchip1_set_isr;
     
    256256        grspw_pci_int_reg = cchip1_set_isr;
    257257        apbuart_pci_int_reg = cchip1_set_isr;
    258        
     258
    259259        /* register the BRM PCI driver, use 16k FTSRAM... */
    260260        if ( b1553brm_pci_register(&cc1.amba_bus,0,0,3,cc1.ftsram_start,0xffa00000) ){
     
    262262                return -1;
    263263        }
    264        
     264
    265265        /* register the BRM PCI driver, no DMA memory... */
    266266        if ( occan_pci_register(&cc1.amba_bus) ){
     
    268268                return -1;
    269269        }
    270        
     270
    271271        /* register the GRSPW PCI driver, use malloc... */
    272272        if ( grspw_pci_register(&cc1.amba_bus,0,0xe0000000) ){
     
    274274                return -1;
    275275        }
    276        
     276
    277277        /* register the APBUART PCI driver, no DMA memory */
    278278        if ( apbuart_pci_register(&cc1.amba_bus) ){
     
    280280                return -1;
    281281        }
    282        
     282
    283283        return 0;
    284284}
     
    299299  regs->PIO_Direction &= ~(1<<7);
    300300  regs->PIO_Interrupt  = 0x87;          /* level sensitive */
    301        
     301
    302302  /* Set up irq controller (mask all IRQs) */
    303303        cc1.pcib->imask = 0x0000;
     
    308308
    309309        memset(int_handlers,0,sizeof(int_handlers));
    310        
     310
    311311        /* Reset spurious counter */
    312312        cchip1_spurious_cnt = 0;
    313        
     313
    314314        /* Register interrupt handler */
    315315        set_vector(cchip1_interrupt_dispatcher,LEON_TRAP_TYPE(CCHIP_IRQ),1);
     
    324324        cc1.pcib->imask |= 1<<irqno; /* Enable the registered IRQ */
    325325}
    326        
    327 static rtems_isr cchip1_interrupt_dispatcher(rtems_vector_number v){   
     326
     327static rtems_isr cchip1_interrupt_dispatcher(rtems_vector_number v){
    328328        unsigned int pending = READ_REG(&cc1.pcib->ipend);
    329329        unsigned int (*handler)(int irqno, void *arg);
    330         unsigned int clr = pending;     
     330        unsigned int clr = pending;
    331331        int irq=1;
    332332
     
    344344        irq=1;
    345345        pending = pending>>1;
    346        
     346
    347347        while ( pending ){
    348348                if ( (pending & 1) && (handler=int_handlers[irq].handler) ){
     
    354354
    355355        cc1.pcib->iclear = clr;
    356        
     356
    357357        /*LEON_Clear_interrupt( brd->irq );*/
    358358}
  • c/src/lib/libbsp/sparc/leon2/clock/ckinit.c

    refdfd48 r44b06ca  
    6767
    6868  /* Down counter */
    69   return (uint32_t) 
     69  return (uint32_t)
    7070     (rtems_configuration_get_microseconds_per_tick() - clicks) * 1000;
    7171}
  • c/src/lib/libbsp/sparc/leon2/console/console.c

    refdfd48 r44b06ca  
    2222/*
    2323 *  Should we use a polled or interrupt drived console?
    24  * 
     24 *
    2525 *  NOTE: This is defined in the custom/leon.cfg file.
    2626 *
     
    3030 *            This did not allow enough time for the program to put more
    3131 *            characters in the buffer.  So every character resulted in
    32  *            "priming" the transmitter.   This effectively results in 
     32 *            "priming" the transmitter.   This effectively results in
    3333 *            in a polled console with a useless interrupt per character
    3434 *            on output.  It is reasonable to assume that input does not
     
    5151
    5252/*
    53  *  console_inbyte_nonblocking 
     53 *  console_inbyte_nonblocking
    5454 *
    5555 *  This routine polls for a character.
     
    7171
    7272#include <ringbuf.h>
    73  
     73
    7474Ring_buffer_t  TX_Buffer[ 2 ];
    7575bool           Is_TX_active[ 2 ];
    76  
     76
    7777void *console_termios_data[ 2 ];
    7878
     
    8383 *
    8484 *  Input parameters:
    85  *    vector - vector number 
     85 *    vector - vector number
    8686 *
    8787 *  Output parameters: NONE
     
    9393  rtems_vector_number vector
    9494)
    95 { 
     95{
    9696  char ch;
    9797  int UStat;
    98  
     98
    9999  if ( (UStat = LEON_REG.UART_Status_1) & LEON_REG_UART_STATUS_DR ) {
    100100    if (UStat & LEON_REG_UART_STATUS_ERR) {
     
    105105    rtems_termios_enqueue_raw_characters( console_termios_data[ 0 ], &ch, 1 );
    106106  }
    107  
     107
    108108  if ( LEON_REG.UART_Status_1 & LEON_REG_UART_STATUS_THE ) {
    109109    if ( !Ring_buffer_Is_empty( &TX_Buffer[ 0 ] ) ) {
     
    113113     Is_TX_active[ 0 ] = false;
    114114  }
    115  
     115
    116116  LEON_Clear_interrupt( LEON_INTERRUPT_UART_1_RX_TX );
    117117}
     
    123123 *
    124124 *  Input parameters:
    125  *    vector - vector number 
     125 *    vector - vector number
    126126 *
    127127 *  Output parameters: NONE
     
    129129 *  Return values:     NONE
    130130 */
    131  
     131
    132132rtems_isr console_isr_b(
    133133  rtems_vector_number vector
     
    194194   *  should be empty.
    195195   */
    196  
    197   while ( (LEON_REG.UART_Status_1 & LEON_REG_UART_STATUS_THE) != 
     196
     197  while ( (LEON_REG.UART_Status_1 & LEON_REG_UART_STATUS_THE) !=
    198198          LEON_REG_UART_STATUS_THE );
    199199
    200   while ( (LEON_REG.UART_Status_2 & LEON_REG_UART_STATUS_THE) != 
     200  while ( (LEON_REG.UART_Status_2 & LEON_REG_UART_STATUS_THE) !=
    201201          LEON_REG_UART_STATUS_THE );
    202202
     
    262262 *  Return values:      NONE
    263263 */
    264  
     264
    265265void console_outbyte_interrupt(
    266266  int   port,
     
    309309 *
    310310 */
    311  
     311
    312312rtems_device_driver console_initialize(
    313313  rtems_device_major_number  major,
     
    335335   *  Initialize Hardware
    336336   */
    337  
     337
    338338  LEON_REG.UART_Control_1 |= LEON_REG_UART_CTRL_RE | LEON_REG_UART_CTRL_TE;
    339339  LEON_REG.UART_Control_2 |= LEON_REG_UART_CTRL_RE | LEON_REG_UART_CTRL_TE |
     
    383383  if ( minor > 2 )
    384384    return RTEMS_INVALID_NUMBER;
    385  
     385
    386386#if (CONSOLE_USE_INTERRUPTS)
    387387  sc = rtems_termios_open (major, minor, arg, &intrCallbacks);
     
    394394  return RTEMS_SUCCESSFUL;
    395395}
    396  
     396
    397397rtems_device_driver console_close(
    398398  rtems_device_major_number major,
     
    403403  return rtems_termios_close (arg);
    404404}
    405  
     405
    406406rtems_device_driver console_read(
    407407  rtems_device_major_number major,
     
    412412  return rtems_termios_read (arg);
    413413}
    414  
     414
    415415rtems_device_driver console_write(
    416416  rtems_device_major_number major,
     
    421421  return rtems_termios_write (arg);
    422422}
    423  
     423
    424424rtems_device_driver console_control(
    425425  rtems_device_major_number major,
  • c/src/lib/libbsp/sparc/leon2/console/debugputs.c

    refdfd48 r44b06ca  
    4141
    4242/*
    43  *  console_inbyte_nonblocking 
     43 *  console_inbyte_nonblocking
    4444 *
    4545 *  This routine polls for a character.
  • c/src/lib/libbsp/sparc/leon2/include/bsp.h

    refdfd48 r44b06ca  
    1111 *
    1212 *  Ported to ERC32 implementation of the SPARC by On-Line Applications
    13  *  Research Corporation (OAR) under contract to the European Space 
     13 *  Research Corporation (OAR) under contract to the European Space
    1414 *  Agency (ESA).
    1515 *
    16  *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. 
     16 *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
    1717 *  European Space Agency.
    1818 *
     
    3636/* SPARC CPU variant: LEON2 */
    3737#define LEON2 1
    38  
     38
    3939/*
    4040 *  BSP provides its own Idle thread body
     
    8282extern int   RAM_END;
    8383extern int   RAM_SIZE;
    84  
     84
    8585extern int   PROM_START;
    8686extern int   PROM_END;
     
    8888
    8989extern int   CLOCK_SPEED;
    90  
     90
    9191extern int   end;        /* last address in the program */
    9292
  • c/src/lib/libbsp/sparc/leon2/include/leon.h

    refdfd48 r44b06ca  
    66 *  was developed by the European Space Agency to target space applications.
    77 *
    8  *  NOTE:  Other than where absolutely required, this version currently 
    9  *         supports only the peripherals and bits used by the basic board 
    10  *         support package. This includes at least significant pieces of 
     8 *  NOTE:  Other than where absolutely required, this version currently
     9 *         supports only the peripherals and bits used by the basic board
     10 *         support package. This includes at least significant pieces of
    1111 *         the following items:
    1212 *
     
    2424 *
    2525 *  Ported to LEON implementation of the SPARC by On-Line Applications
    26  *  Research Corporation (OAR) under contract to the European Space 
     26 *  Research Corporation (OAR) under contract to the European Space
    2727 *  Agency (ESA).
    2828 *
    29  *  LEON modifications of respective RTEMS file: COPYRIGHT (c) 1995. 
     29 *  LEON modifications of respective RTEMS file: COPYRIGHT (c) 1995.
    3030 *  European Space Agency.
    3131 *
    3232 *  $Id$
    3333 */
    34  
     34
    3535#ifndef _INCLUDE_LEON_h
    3636#define _INCLUDE_LEON_h
    3737
    3838#include <rtems/score/sparc.h>
    39  
     39
    4040#ifdef __cplusplus
    4141extern "C" {
     
    4545 *  Interrupt Sources
    4646 *
    47  *  The interrupt source numbers directly map to the trap type and to 
     47 *  The interrupt source numbers directly map to the trap type and to
    4848 *  the bits used in the Interrupt Clear, Interrupt Force, Interrupt Mask,
    4949 *  and the Interrupt Pending Registers.
     
    7373 *  Source: Table 8 - Interrupt Trap Type and Default Priority Assignments
    7474 *
    75  *  NOTE: The priority level for each source corresponds to the least 
     75 *  NOTE: The priority level for each source corresponds to the least
    7676 *        significant nibble of the trap type.
    7777 */
     
    8686
    8787/*
    88  *  Structure for LEON memory mapped registers. 
     88 *  Structure for LEON memory mapped registers.
    8989 *
    9090 *  Source: Section 6.1 - On-chip registers
    9191 *
    92  *  NOTE:  There is only one of these structures per CPU, its base address 
    93  *         is 0x80000000, and the variable LEON_REG is placed there by the 
     92 *  NOTE:  There is only one of these structures per CPU, its base address
     93 *         is 0x80000000, and the variable LEON_REG is placed there by the
    9494 *         linkcmds file.
    9595 */
     
    108108        volatile unsigned int dummy2;
    109109        volatile unsigned int dummy3;
    110         volatile unsigned int dummy4;   
     110        volatile unsigned int dummy4;
    111111        volatile unsigned int dummy5;
    112112        volatile unsigned int dummy6;
     
    214214#define LEON_MEMORY_CONFIGURATION_RAM_SIZE_MASK  0x00001E00
    215215
    216  
     216
    217217/*
    218218 *  The following defines the bits in the Timer Control Register.
     
    231231 */
    232232
    233 #define LEON_REG_UART_CONTROL_RTD  0x000000FF /* RX/TX data */ 
    234  
     233#define LEON_REG_UART_CONTROL_RTD  0x000000FF /* RX/TX data */
     234
    235235/*
    236236 *  The following defines the bits in the LEON UART Status Registers.
     
    247247#define LEON_REG_UART_STATUS_ERR  0x00000078 /* Error Mask */
    248248
    249  
     249
    250250/*
    251251 *  The following defines the bits in the LEON UART Status Registers.
     
    271271
    272272extern LEON_Register_Map LEON_REG;
    273  
     273
    274274/*
    275275 *  Macros to manipulate the Interrupt Clear, Interrupt Force, Interrupt Mask,
     
    291291    LEON_REG.Interrupt_Force = (1 << (_source)); \
    292292  } while (0)
    293  
     293
    294294#define LEON_Is_interrupt_pending( _source ) \
    295295  (LEON_REG.Interrupt_Pending & (1 << (_source)))
    296  
     296
    297297#define LEON_Is_interrupt_masked( _source ) \
    298298  (LEON_REG.Interrupt_Masked & (1 << (_source)))
    299  
     299
    300300#define LEON_Mask_interrupt( _source ) \
    301301  do { \
     
    306306    sparc_enable_interrupts( _level ); \
    307307  } while (0)
    308  
     308
    309309#define LEON_Unmask_interrupt( _source ) \
    310310  do { \
     
    327327    (_previous) &= _mask; \
    328328  } while (0)
    329  
     329
    330330#define LEON_Restore_interrupt( _source, _previous ) \
    331331  do { \
     
    351351 *
    352352 *    D2 - Counter Load
    353  *          1 = load counter with preset value 
     353 *          1 = load counter with preset value
    354354 *          0 = no function
    355355 *
     
    375375}
    376376#endif
    377  
     377
    378378#endif /* !_INCLUDE_LEON_h */
    379379
  • c/src/lib/libbsp/sparc/leon2/include/rasta.h

    refdfd48 r44b06ca  
    4545 *
    4646 */
    47 #define LEON_REG_UART_CONTROL_RTD  0x000000FF /* RX/TX data */ 
    48  
     47#define LEON_REG_UART_CONTROL_RTD  0x000000FF /* RX/TX data */
     48
    4949/*
    5050 *  The following defines the bits in the LEON UART Status Registers.
     
    5959#define LEON_REG_UART_STATUS_ERR  0x00000078 /* Error Mask */
    6060
    61  
     61
    6262/*
    6363 *  The following defines the bits in the LEON UART Status Registers.
  • c/src/lib/libbsp/sparc/leon2/leon_open_eth/leon_open_eth.c

    refdfd48 r44b06ca  
    2929
    3030open_eth_configuration_t leon_open_eth_configuration = {
    31   OPEN_ETH_BASE_ADDRESS,        /* base address */ 
    32   OPEN_ETH_VECTOR,              /* vector number */ 
     31  OPEN_ETH_BASE_ADDRESS,        /* base address */
     32  OPEN_ETH_VECTOR,              /* vector number */
    3333  TDA_COUNT,                 /* number of transmit descriptors */
    3434  RDA_COUNT,                 /* number of receive descriptors */
  • c/src/lib/libbsp/sparc/leon2/leon_smc91111/leon_smc91111.c

    refdfd48 r44b06ca  
    3131
    3232scmv91111_configuration_t leon_scmv91111_configuration = {
    33   SMC91111_BASE_ADDR, /* base address */ 
    34   SMC91111_BASE_IRQ,  /* vector number */ 
    35   SMC91111_BASE_PIO,  /* PIO */ 
     33  SMC91111_BASE_ADDR, /* base address */
     34  SMC91111_BASE_IRQ,  /* vector number */
     35  SMC91111_BASE_PIO,  /* PIO */
    3636  100,                /* 100b */
    3737  1,                  /* fulldx */
     
    5757    (0xe0 | leon_scmv91111_configuration.pio)
    5858      << (8 * ((leon_scmv91111_configuration.vector & 0x0f) - 4));
    59  
     59
    6060  return _rtems_smc91111_driver_attach(config,&leon_scmv91111_configuration);
    6161
  • c/src/lib/libbsp/sparc/leon2/pci/pci.c

    refdfd48 r44b06ca  
    1919 *   - separated bridge detection code out of this file
    2020 *
    21  *  Adapted to LEON2 AT697 PCI 
     21 *  Adapted to LEON2 AT697 PCI
    2222 *  Copyright (C) 2006 Gaisler Research
    2323 *
     
    2929
    3030/* Define PCI_INFO to get a listing of configured devices at boot time */
    31 #define PCI_INFO 1 
     31#define PCI_INFO 1
    3232
    3333/* #define DEBUG 1 */
     
    3636#define DBG(x...) printk(x)
    3737#else
    38 #define DBG(x...) 
     38#define DBG(x...)
    3939#endif
    4040
     
    5656 * Bit encode for PCI_CONFIG_HEADER_TYPE register
    5757 */
    58 unsigned char ucMaxPCIBus; 
     58unsigned char ucMaxPCIBus;
    5959
    6060typedef struct {
     
    6666    volatile unsigned int mbar2;         /* 0x80000114 - Memory Base Address Register 2               */
    6767    volatile unsigned int iobar3;        /* 0x80000118 - IO Base Address Register 3                   */
    68     volatile unsigned int dummy1[4];     /* 0x8000011c - 0x80000128                                   */ 
     68    volatile unsigned int dummy1[4];     /* 0x8000011c - 0x80000128                                   */
    6969    volatile unsigned int pcisid;        /* 0x8000012c - Subsystem identification register            */
    7070    volatile unsigned int dummy2;        /* 0x80000130                                                */
     
    7979    volatile unsigned int pciis;         /* 0x80000154 - PCI Initiator Status Register                */
    8080    volatile unsigned int pciic;         /* 0x80000158 - PCI Initiator Configuration                  */
    81     volatile unsigned int pcitpa;        /* 0x8000015c - PCI Target Page Address Register             */   
     81    volatile unsigned int pcitpa;        /* 0x8000015c - PCI Target Page Address Register             */
    8282    volatile unsigned int pcitsc;        /* 0x80000160 - PCI Target Status-Command Register           */
    8383    volatile unsigned int pciite;        /* 0x80000164 - PCI Interrupt Enable Register                */
    8484    volatile unsigned int pciitp;        /* 0x80000168 - PCI Interrupt Pending Register               */
    8585    volatile unsigned int pciitf;        /* 0x8000016c - PCI Interrupt Force Register                 */
    86     volatile unsigned int pcid;          /* 0x80000170 - PCI Data Register                            */   
     86    volatile unsigned int pcid;          /* 0x80000170 - PCI Data Register                            */
    8787    volatile unsigned int pcibe;         /* 0x80000174 - PCI Burst End Register                       */
    8888    volatile unsigned int pcidmaa;       /* 0x80000178 - PCI DMA Address Register                     */
     
    105105 *  AT697 pci controller to be able access all slots
    106106 */
    107  
     107
    108108static int
    109109BSP_pci_read_config_dword(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned int *val) {
     
    113113    if (offset & 3) return PCIBIOS_BAD_REGISTER_NUMBER;
    114114
    115     pcic->pciitp = 0xff; /* clear interrupts */ 
     115    pcic->pciitp = 0xff; /* clear interrupts */
    116116
    117117    pcic->pcisa = (  1<<(11+slot) ) | ((function & 7)<<8) |  (offset&0x3f);
     
    121121    while (pcic->pciitp == 0)
    122122        ;
    123    
    124     pcic->pciitp = 0xff; /* clear interrupts */ 
     123
     124    pcic->pciitp = 0xff; /* clear interrupts */
    125125
    126126    if (pcic->pcisc & 0x20000000)  { /* Master Abort */
     
    131131        *val = data;
    132132
    133     DBG("pci_read - bus: %d, dev: %d, fn: %d, off: %d => addr: %x, val: %x\n", bus, slot, function, offset,  (1<<(11+slot) ) | ((function & 7)<<8) |  (offset&0x3f), *val); 
     133    DBG("pci_read - bus: %d, dev: %d, fn: %d, off: %d => addr: %x, val: %x\n", bus, slot, function, offset,  (1<<(11+slot) ) | ((function & 7)<<8) |  (offset&0x3f), *val);
    134134
    135135    return PCIBIOS_SUCCESSFUL;
     
    137137
    138138
    139 static int 
     139static int
    140140BSP_pci_read_config_word(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned short *val) {
    141141    unsigned int v;
     
    150150
    151151
    152 static int 
     152static int
    153153BSP_pci_read_config_byte(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned char *val) {
    154154    unsigned int v;
     
    168168
    169169    pcic->pciitp = 0xff; /* clear interrupts */
    170  
     170
    171171    pcic->pcisa = (  1<<(11+slot) ) | ((function & 7)<<8) |  (offset&0x3f);
    172172    pcic->pcidma = 0xb01;
     
    188188
    189189
    190 static int 
     190static int
    191191BSP_pci_write_config_word(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned short val) {
    192192    unsigned int v;
     
    202202
    203203
    204 static int 
     204static int
    205205BSP_pci_write_config_byte(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned char val) {
    206206    unsigned int v;
     
    209209
    210210    v = (v & ~(0xff << (8*(offset&3)))) | ((0xff&val) << (8*(offset&3)));
    211    
     211
    212212    return pci_write_config_dword(bus, slot, function, offset&~3, v);
    213213}
     
    263263    }
    264264
    265     pcic->pciitp = 0xff; /* clear interrupts */ 
     265    pcic->pciitp = 0xff; /* clear interrupts */
    266266
    267267    pcic->pcisa = paddr;
     
    272272        ;
    273273
    274     if (pcic->pciitp & 0x7F) { 
     274    if (pcic->pciitp & 0x7F) {
    275275        retval = -1;
    276276    }
    277277
    278     pcic->pciitp = 0xff; /* clear interrupts */ 
     278    pcic->pciitp = 0xff; /* clear interrupts */
    279279
    280280    if (pcic->pcisc & 0x20000000)  { /* Master Abort */
     
    282282        retval = -1;
    283283    }
    284    
     284
    285285    return retval;
    286286}
     
    293293    if (addr & 3) return -1;
    294294
    295     pcic->pciitp = 0xff; /* clear interrupts */ 
     295    pcic->pciitp = 0xff; /* clear interrupts */
    296296
    297297    pcic->pcisa = paddr;
     
    301301    while (pcic->pciitp == 0)
    302302        ;
    303    
     303
    304304    if (pcic->pciitp & 0x7F) retval = -1;
    305305
    306     pcic->pciitp = 0xff; /* clear interrupts */ 
     306    pcic->pciitp = 0xff; /* clear interrupts */
    307307
    308308    if (pcic->pcisc & 0x20000000)  { /* Master Abort */
     
    316316/* Transfer len number of words from addr to paddr */
    317317int dma_to_pci(unsigned int addr, unsigned int paddr, unsigned int len) {
    318    
     318
    319319    int tmp_len;
    320320
     
    330330    paddr += tmp_len;
    331331    len -= tmp_len/4;
    332    
     332
    333333    /* Transfer all 1k blocks */
    334334    while (len >= 128) {
    335335
    336         if (dma_to_pci_1k(addr, paddr, 128) < 0) 
     336        if (dma_to_pci_1k(addr, paddr, 128) < 0)
    337337            return -1;
    338338
     
    365365    paddr += tmp_len;
    366366    len -= tmp_len/4;
    367    
     367
    368368    /* Transfer all 1k blocks */
    369369    while (len >= 128) {
     
    387387
    388388    pci_read_config_dword(0, slot, function, PCI_COMMAND, &data);
    389     pci_write_config_dword(0, slot, function, PCI_COMMAND, data | PCI_COMMAND_MEMORY); 
     389    pci_write_config_dword(0, slot, function, PCI_COMMAND, data | PCI_COMMAND_MEMORY);
    390390
    391391}
     
    395395
    396396    pci_read_config_dword(0, slot, function, PCI_COMMAND, &data);
    397     pci_write_config_dword(0, slot, function, PCI_COMMAND, data | PCI_COMMAND_MASTER); 
     397    pci_write_config_dword(0, slot, function, PCI_COMMAND, data | PCI_COMMAND_MASTER);
    398398
    399399}
     
    414414 *
    415415 * NOTE that it only allocates PCI memory space devices. IO spaces are not enabled.
    416  * Also, it does not handle pci-pci bridges. They are left disabled. 
     416 * Also, it does not handle pci-pci bridges. They are left disabled.
    417417 *
    418418 *
     
    427427
    428428    for (i = 0; i < 32*8*6; i++) {
    429         res[i] = (struct pci_res *) malloc(sizeof(struct pci_res));     
     429        res[i] = (struct pci_res *) malloc(sizeof(struct pci_res));
    430430        res[i]->size = 0;
    431431        res[i]->devfn = i;
     
    444444
    445445        pci_read_config_byte(0, slot, 0, PCI_HEADER_TYPE, &header);
    446      
     446
    447447        if(header & PCI_MULTI_FUNCTION) {
    448448            numfuncs = PCI_MAX_FUNCTIONS;
     
    464464                continue;
    465465            }
    466            
     466
    467467            for (pos = 0; pos < 6; pos++) {
    468468                pci_write_config_dword(0, slot, func, PCI_BASE_ADDRESS_0 + (pos<<2), 0xffffffff);
     
    486486
    487487
    488     /* Sort the resources in descending order */ 
     488    /* Sort the resources in descending order */
    489489
    490490    swapped = 1;
     
    512512            goto done;
    513513        }
    514    
     514
    515515        dev = res[i]->devfn >> 3;
    516516        fn  = res[i]->devfn & 7;
    517    
     517
    518518        DBG("Assigning PCI addr %x to device %d, function %d, bar %d\n", addr, dev, fn, res[i]->bar);
    519519        pci_write_config_dword(0, dev, fn, PCI_BASE_ADDRESS_0+res[i]->bar*4, addr);
     
    521521
    522522        /* Set latency timer to 64 */
    523         pci_read_config_dword(0, dev, fn, 0xC, &tmp);   
     523        pci_read_config_dword(0, dev, fn, 0xC, &tmp);
    524524        pci_write_config_dword(0, dev, fn, 0xC, tmp|0x4000);
    525525
    526         pci_mem_enable(0, dev, fn); 
    527 
    528     } 
    529 
    530 
    531    
     526        pci_mem_enable(0, dev, fn);
     527
     528    }
     529
     530
     531
    532532done:
    533533
     
    535535    printk("\nPCI devices found and configured:\n");
    536536    for (slot = 0; slot < PCI_MAX_DEVICES; slot++) {
    537        
    538         pci_read_config_byte(0, slot, 0, PCI_HEADER_TYPE, &header); 
    539        
     537
     538        pci_read_config_byte(0, slot, 0, PCI_HEADER_TYPE, &header);
     539
    540540        if(header & PCI_MULTI_FUNCTION) {
    541541            numfuncs = PCI_MAX_FUNCTIONS;
     
    546546
    547547        for (func = 0; func < numfuncs; func++) {
    548            
     548
    549549            pci_read_config_dword(0, slot, func, PCI_COMMAND, &tmp);
    550550
    551             if (tmp & PCI_COMMAND_MEMORY) { 
    552                
     551            if (tmp & PCI_COMMAND_MEMORY) {
     552
    553553                pci_read_config_dword(0, slot, func, PCI_VENDOR_ID,  &id);
    554554
    555555                if (id == PCI_INVALID_VENDORDEVICEID || id == 0) continue;
    556                
     556
    557557                printk("\nSlot %d function: %d\nVendor id: 0x%x, device id: 0x%x\n", slot, func, id & 0xffff, id>>16);
    558558
     
    564564                        printk("\tBAR %d: %x\n", pos, tmp);
    565565                    }
    566                
     566
    567567                }
    568568                printk("\n");
    569569
    570             } 
     570            }
    571571
    572572        }
     
    574574    printk("\n");
    575575#endif
    576    
     576
    577577    for (i = 0; i < 1536; i++) {
    578578        free(res[i]);
     
    595595    unsigned char ucHeader;
    596596    unsigned char ucMaxSubordinate;
    597     unsigned int  ulClass, ulDeviceID; 
     597    unsigned int  ulClass, ulDeviceID;
    598598
    599599    init_at697_pci();
  • c/src/lib/libbsp/sparc/leon2/rasta/rasta.c

    refdfd48 r44b06ca  
    3535#define DBG(x...) printk(x)
    3636#else
    37 #define DBG(x...) 
     37#define DBG(x...)
    3838#endif
    3939
     
    7373
    7474/*     if (*pci_int & 0x20) { */
    75        
     75
    7676/*         *pci_int = 0x20; */
    7777
     
    100100{
    101101    unsigned int status;
    102  
     102
    103103    status = irq->ipend;
    104104
     
    106106      grcan_int_handler(GRCAN_IRQNO,grcan_int_arg);
    107107    }
    108    
     108
    109109    if (status & SPW_IRQ) {
    110110      if ( (status & SPW0_IRQ) && spw0_int_handler ){
     
    115115        spw1_int_handler(SPW1_IRQNO,spw1_int_arg);
    116116      }
    117      
     117
    118118      if ( (status & SPW2_IRQ) && spw2_int_handler ){
    119119        spw2_int_handler(SPW2_IRQNO,spw2_int_arg);
    120120      }
    121121    }
    122     if ((status & BRM_IRQ) && brm_int_handler ){ 
     122    if ((status & BRM_IRQ) && brm_int_handler ){
    123123        brm_int_handler(BRM_IRQNO,brm_int_arg);
    124124    }
     
    129129      uart1_int_handler(UART1_IRQNO,uart1_int_arg);
    130130    }
    131    
     131
    132132    DBG("RASTA-IRQ: 0x%x\n",status);
    133133    irq->iclear = status;
    134  
     134
    135135}
    136136
     
    142142    uart0_int_handler = handler;
    143143    uart0_int_arg = arg;
    144    
     144
    145145    /* unmask interrupt source */
    146146    irq->iclear = UART0_IRQ;
    147147    irq->mask[0] |= UART0_IRQ;
    148148  }
    149  
     149
    150150  if ( irqno == UART1_IRQNO ){
    151151    DBG("RASTA: Registering uart1 handler: 0x%x, arg: 0x%x\n",handler,arg);
    152152    uart1_int_handler = handler;
    153153    uart1_int_arg = arg;
    154    
     154
    155155    /* unmask interrupt source */
    156156    irq->iclear = UART1_IRQ;
    157157    irq->mask[0] |= UART1_IRQ;
    158158  }
    159  
     159
    160160  if ( irqno == SPW0_IRQNO ){
    161161    DBG("RASTA: Registering spw0 handler: 0x%x, arg: 0x%x\n",handler,arg);
    162162    spw0_int_handler = handler;
    163163    spw0_int_arg = arg;
    164    
     164
    165165    /* unmask interrupt source */
    166166    irq->iclear = SPW0_IRQ;
     
    172172    spw1_int_handler = handler;
    173173    spw1_int_arg = arg;
    174    
     174
    175175    /* unmask interrupt source */
    176176    irq->iclear = SPW1_IRQ;
    177177    irq->mask[0] |= SPW1_IRQ;
    178178  }
    179  
     179
    180180  if ( irqno == SPW2_IRQNO ){
    181181    DBG("RASTA: Registering spw2 handler: 0x%x, arg: 0x%x\n",handler,arg);
    182182    spw2_int_handler = handler;
    183183    spw2_int_arg = arg;
    184    
     184
    185185    /* unmask interrupt source */
    186186    irq->iclear = SPW2_IRQ;
    187187    irq->mask[0] |= SPW2_IRQ;
    188188  }
    189  
     189
    190190  if ( irqno == GRCAN_IRQNO ){
    191191    DBG("RASTA: Registering GRCAN handler: 0x%x, arg: 0x%x\n",handler,arg);
    192192    grcan_int_handler = handler;
    193193    grcan_int_arg = arg;
    194    
     194
    195195    /* unmask interrupt source */
    196196    irq->iclear = GRCAN_IRQ;
    197197    irq->mask[0] |= GRCAN_IRQ;
    198198  }
    199  
     199
    200200  if ( irqno == BRM_IRQNO ){
    201201    DBG("RASTA: Registering BRM handler: 0x%x, arg: 0x%x\n",handler,arg);
    202202    brm_int_handler = handler;
    203203    brm_int_arg = arg;
    204    
     204
    205205    /* unmask interrupt source */
    206206    irq->iclear = BRM_IRQ;
    207207    irq->mask[0] |= BRM_IRQ;
    208   } 
     208  }
    209209}
    210210
     
    214214  amba_apb_device dev;
    215215  int cores;
    216  
    217   if ( !abus ) 
     216
     217  if ( !abus )
    218218    return -1;
    219  
     219
    220220  /* Scan PnP info for GPIO port number 'index' */
    221221  cores = amba_find_next_apbslv(abus,VENDOR_GAISLER,GAISLER_PIOPORT,&dev,index);
    222222  if ( cores < 1 )
    223223    return -1;
    224  
     224
    225225  if ( regs )
    226226    *regs = (struct gpio_reg *)dev.start;
    227  
     227
    228228  if ( irq )
    229229    *irq = dev.irq;
    230  
     230
    231231  return 0;
    232232}
     
    236236static struct amba_mmap amba_maps[3];
    237237
    238 int rasta_register(void) 
     238int rasta_register(void)
    239239{
    240240    unsigned int bar0, bar1, data;
     
    243243    unsigned int *apb_base = NULL;
    244244    int found=0;
    245    
     245
    246246
    247247    DBG("Searching for RASTA board ...");
    248    
     248
    249249    /* Search PCI vendor/device id. */
    250250    if (BSP_pciFindDevice(0x1AC8, 0x0010, 0, &bus, &dev, &fun) == 0) {
    251251      found = 1;
    252252    }
    253    
     253
    254254    /* Search old PCI vendor/device id. */
    255255    if ( (!found) && (BSP_pciFindDevice(0x16E3, 0x0210, 0, &bus, &dev, &fun) == 0) ) {
    256256      found = 1;
    257257    }
    258    
     258
    259259    /* Did we find a RASTA board? */
    260260    if ( !found )
    261261      return -1;
    262    
     262
    263263    DBG(" found it (dev/fun: %d/%d).\n", dev, fun);
    264264
     
    266266    pci_read_config_dword(bus, dev, fun, 0x14, &bar1);
    267267
    268     page0 = (unsigned int *)(bar0 + 0x400000); 
     268    page0 = (unsigned int *)(bar0 + 0x400000);
    269269    *page0 = 0x80000000;                  /* Point PAGE0 to start of APB       */
    270270
     
    280280    apb_base[1] = 0x00001260;
    281281    apb_base[2] = 0x000e8000;
    282 #else 
     282#else
    283283    apb_base[0] = 0x000002ff;
    284284    apb_base[1] = 0x82206000;
     
    286286#endif
    287287    /* Set up rasta irq controller */
    288     irq = (LEON3_IrqCtrl_Regs_Map *) (bar0+IRQ_OFFSET); 
     288    irq = (LEON3_IrqCtrl_Regs_Map *) (bar0+IRQ_OFFSET);
    289289    irq->iclear = 0xffff;
    290290    irq->ilevel = 0;
     
    298298    apb_base[0x104] =  0x40000000;        /* 0xA0000000;  Point PAGE1 to RAM */
    299299
    300    
     300
    301301    /* set parity error response */
    302302    pci_read_config_dword(bus, dev, fun, 0x4, &data);
    303303    pci_write_config_dword(bus, dev, fun, 0x4, data|0x40);
    304304
    305      
     305
    306306    pci_master_enable(bus, dev, fun);
    307307
     
    309309    /*    set_vector(pci_interrupt_handler,14+0x10, 1); */
    310310
    311      
     311
    312312    /* install interrupt vector */
    313313    set_vector(rasta_interrupt_handler, RASTA_IRQ+0x10, 1);
    314314
    315315    /* Scan AMBA Plug&Play */
    316        
     316
    317317    /* AMBA MAP bar0 (in CPU) ==> 0x80000000(remote amba address) */
    318318    amba_maps[0].size = 0x10000000;
     
    329329    amba_maps[2].cpu_adr = 0;
    330330    amba_maps[2].remote_amba_adr = 0;
    331        
     331
    332332    memset(&abus,0,sizeof(abus));
    333        
     333
    334334    /* Start AMBA PnP scan at first AHB bus */
    335335    amba_scan(&abus,bar0+(AHB1_IOAREA_BASE_ADDR&~0xf0000000),&amba_maps[0]);
    336        
     336
    337337    printk("Registering RASTA GRCAN driver\n\r");
    338    
     338
    339339    /*grhcan_register(bar0 + GRHCAN_OFFSET, bar1);*/
    340340    grcan_rasta_int_reg=rasta_interrrupt_register;
     
    353353      return -1;
    354354    }
    355        
     355
    356356    /* provide the spacewire driver with AMBA Plug&Play
    357357     * info so that it can find the GRSPW cores.
     
    377377      return -1;
    378378    }
    379        
     379
    380380    /* Find GPIO1 address */
    381381    if ( rasta_get_gpio(&abus,1,&gpio1,NULL) ){
     
    383383      return -1;
    384384    }
    385    
     385
    386386    /* Successfully registered the RASTA board */
    387387    return 0;
  • c/src/lib/libbsp/sparc/leon2/startup/bspidle.c

    refdfd48 r44b06ca  
    1010 *
    1111 *  Ported to LEON implementation of the SPARC by On-Line Applications
    12  *  Research Corporation (OAR) under contract to the European Space 
     12 *  Research Corporation (OAR) under contract to the European Space
    1313 *  Agency (ESA).
    1414 *
    15  *  LEON modifications of respective RTEMS file: COPYRIGHT (c) 1995. 
     15 *  LEON modifications of respective RTEMS file: COPYRIGHT (c) 1995.
    1616 *  European Space Agency.
    1717 *
  • c/src/lib/libbsp/sparc/leon2/startup/bspstart.c

    refdfd48 r44b06ca  
    2525/*
    2626 * Tells us if data cache snooping is available
    27  */ 
     27 */
    2828int CPU_SPARC_HAS_SNOOPING;
    2929
    3030/*
    3131 * set_snooping
    32  * 
     32 *
    3333 * Read the data cache configuration register to determine if
    3434 * bus snooping is available. This is needed for some drivers so
    35  * that they can select the most efficient copy routines. 
     35 * that they can select the most efficient copy routines.
    3636 */
    37 static inline int set_snooping(void) 
     37static inline int set_snooping(void)
    3838{
    3939  unsigned int tmp = *(unsigned int *)0x80000014; /* Cache control register */
  • c/src/lib/libbsp/sparc/leon2/startup/setvec.c

    refdfd48 r44b06ca  
    2222 *
    2323 *  Ported to LEON implementation of the SPARC by On-Line Applications
    24  *  Research Corporation (OAR) under contract to the European Space 
     24 *  Research Corporation (OAR) under contract to the European Space
    2525 *  Agency (ESA).
    2626 *
    27  *  LEON modifications of respective RTEMS file: COPYRIGHT (c) 1995. 
     27 *  LEON modifications of respective RTEMS file: COPYRIGHT (c) 1995.
    2828 *  European Space Agency.
    2929 *
     
    4545  if ( type )
    4646    rtems_interrupt_catch( handler, vector, &previous_isr );
    47   else 
     47  else
    4848    _CPU_ISR_install_raw_handler( vector, handler, (void *)&previous_isr );
    4949
     
    5151
    5252  if ( LEON_INT_TRAP( real_trap ) ) {
    53    
     53
    5454    source = LEON_TRAP_SOURCE( real_trap );
    5555
  • c/src/lib/libbsp/sparc/leon2/startup/spurious.c

    refdfd48 r44b06ca  
    22 *  LEON Spurious Trap Handler
    33 *
    4  *  This is just enough of a trap handler to let us know what 
     4 *  This is just enough of a trap handler to let us know what
    55 *  the likely source of the trap was.
    66 *
    7  *  Developed as part of the port of RTEMS to the LEON implementation 
    8  *  of the SPARC by On-Line Applications Research Corporation (OAR) 
     7 *  Developed as part of the port of RTEMS to the LEON implementation
     8 *  of the SPARC by On-Line Applications Research Corporation (OAR)
    99 *  under contract to the European Space Agency (ESA).
    1010 *
     
    4242     */
    4343
    44     case 0x00: 
     44    case 0x00:
    4545      printk( "reset\n" );
    4646      break;
    47     case 0x01: 
     47    case 0x01:
    4848      printk( "instruction access exception\n" );
    4949      break;
    50     case 0x02: 
     50    case 0x02:
    5151      printk( "illegal instruction\n" );
    5252      break;
    53     case 0x03: 
     53    case 0x03:
    5454      printk( "privileged instruction\n" );
    5555      break;
    56     case 0x04: 
     56    case 0x04:
    5757      printk( "fp disabled\n" );
    5858      break;
    59     case 0x07: 
     59    case 0x07:
    6060      printk( "memory address not aligned\n" );
    6161      break;
    62     case 0x08: 
     62    case 0x08:
    6363      printk( "fp exception\n" );
    6464      break;
    65     case 0x09: 
     65    case 0x09:
    6666      printk("data access exception at 0x%08x\n", LEON_REG.Failed_Address );
    6767      break;
    68     case 0x0A: 
     68    case 0x0A:
    6969      printk( "tag overflow\n" );
    7070      break;
     
    140140
    141141    if (( trap == 5 || trap == 6 ) ||
    142         (( trap >= 0x11 ) && ( trap <= 0x1f )) || 
     142        (( trap >= 0x11 ) && ( trap <= 0x1f )) ||
    143143        (( trap >= 0x70 ) && ( trap <= 0x83 )))
    144144      continue;
  • c/src/lib/libbsp/sparc/leon2/timer/timer.c

    refdfd48 r44b06ca  
    1111 *
    1212 *  Ported to LEON implementation of the SPARC by On-Line Applications
    13  *  Research Corporation (OAR) under contract to the European Space 
     13 *  Research Corporation (OAR) under contract to the European Space
    1414 *  Agency (ESA).
    1515 *
    16  *  LEON modifications of respective RTEMS file: COPYRIGHT (c) 1995. 
     16 *  LEON modifications of respective RTEMS file: COPYRIGHT (c) 1995.
    1717 *  European Space Agency.
    1818 *
     
    4343  }
    4444
    45   LEON_REG.Timer_Control_2 = ( 
    46     LEON_REG_TIMER_COUNTER_ENABLE_COUNTING | 
     45  LEON_REG.Timer_Control_2 = (
     46    LEON_REG_TIMER_COUNTER_ENABLE_COUNTING |
    4747      LEON_REG_TIMER_COUNTER_LOAD_COUNTER
    4848  );
  • c/src/lib/libbsp/sparc/leon3/amba/amba.c

    refdfd48 r44b06ca  
    2828 *
    2929 *  BSP predriver hook.  Called just before drivers are initialized.
    30  *  Used to scan system bus. Probes for AHB masters, AHB slaves and 
     30 *  Used to scan system bus. Probes for AHB masters, AHB slaves and
    3131 *  APB slaves. Addresses to configuration areas of the AHB masters,
    32  *  AHB slaves, APB slaves and APB master are storeds in 
     32 *  AHB slaves, APB slaves and APB master are storeds in
    3333 *  amba_ahb_masters, amba_ahb_slaves and amba.
    3434 */
     
    6565#endif
    6666  }
    67  
     67
    6868  /* find GP Timer */
    6969  i = amba_find_apbslv(&amba_conf,VENDOR_GAISLER,GAISLER_GPTIMER,&dev);
  • c/src/lib/libbsp/sparc/leon3/clock/ckinit.c

    refdfd48 r44b06ca  
    3737#else
    3838  #define LEON3_CLOCK_INDEX 0
    39 #endif 
     39#endif
    4040
    4141
  • c/src/lib/libbsp/sparc/leon3/console/console.c

    refdfd48 r44b06ca  
    2727/*
    2828 *  Should we use a polled or interrupt drived console?
    29  * 
     29 *
    3030 *  NOTE: This is defined in the custom/leon.cfg file.
    3131 */
     
    4545
    4646/*
    47  *  console_inbyte_nonblocking 
     47 *  console_inbyte_nonblocking
    4848 *
    4949 *  This routine polls for a character.
     
    8787    i = 0;
    8888    uarts = 0;
    89    
     89
    9090    uarts = amba_find_apbslvs(
    9191      &amba_conf, VENDOR_GAISLER, GAISLER_APBUART, apbuarts, LEON3_APBUARTS);
     
    114114
    115115  /* default to zero and override if multiprocessing */
    116   uart0 = 0; 
     116  uart0 = 0;
    117117  #if defined(RTEMS_MULTIPROCESSING)
    118118    if (rtems_configuration_get_user_multiprocessing_table() != NULL)
     
    121121
    122122  /*  Register Device Names */
    123  
    124   if (uarts && (uart0 < uarts)) 
    125   { 
     123
     124  if (uarts && (uart0 < uarts))
     125  {
    126126    status = rtems_io_register_name( "/dev/console", major, 0 );
    127127    if (status != RTEMS_SUCCESSFUL)
     
    140140   *  Initialize Hardware if ONLY CPU or first CPU in MP system
    141141   */
    142  
     142
    143143  #if defined(RTEMS_MULTIPROCESSING)
    144144    if (rtems_configuration_get_user_multiprocessing_table()->node == 1)
     
    149149      LEON3_Console_Uart[i]->ctrl |=
    150150        LEON_REG_UART_CTRL_RE | LEON_REG_UART_CTRL_TE;
    151       LEON3_Console_Uart[i]->status = 0; 
     151      LEON3_Console_Uart[i]->status = 0;
    152152    }
    153153  }
     
    179179  if ( minor > LEON3_APBUARTS )
    180180    return RTEMS_INVALID_NUMBER;
    181  
     181
    182182  sc = rtems_termios_open (major, minor, arg, &pollCallbacks);
    183183
     
    185185  return RTEMS_SUCCESSFUL;
    186186}
    187  
     187
    188188rtems_device_driver console_close(
    189189  rtems_device_major_number major,
     
    194194  return rtems_termios_close (arg);
    195195}
    196  
     196
    197197rtems_device_driver console_read(
    198198  rtems_device_major_number major,
     
    203203  return rtems_termios_read (arg);
    204204}
    205  
     205
    206206rtems_device_driver console_write(
    207207  rtems_device_major_number major,
     
    212212  return rtems_termios_write (arg);
    213213}
    214  
     214
    215215rtems_device_driver console_control(
    216216  rtems_device_major_number major,
  • c/src/lib/libbsp/sparc/leon3/console/debugputs.c

    refdfd48 r44b06ca  
    4646
    4747/*
    48  *  console_inbyte_nonblocking 
     48 *  console_inbyte_nonblocking
    4949 *
    5050 *  This routine polls for a character.
  • c/src/lib/libbsp/sparc/leon3/include/bsp.h

    refdfd48 r44b06ca  
    1111 *
    1212 *  Ported to ERC32 implementation of the SPARC by On-Line Applications
    13  *  Research Corporation (OAR) under contract to the European Space 
     13 *  Research Corporation (OAR) under contract to the European Space
    1414 *  Agency (ESA).
    1515 *
    16  *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. 
     16 *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
    1717 *  European Space Agency.
    1818 *
     
    9292extern int   RAM_END;
    9393extern int   RAM_SIZE;
    94  
     94
    9595extern int   PROM_START;
    9696extern int   PROM_END;
     
    9898
    9999extern int   CLOCK_SPEED;
    100  
     100
    101101extern int   end;        /* last address in the program */
    102102
  • c/src/lib/libbsp/sparc/leon3/include/leon.h

    refdfd48 r44b06ca  
    1616 *  $Id$
    1717 */
    18  
     18
    1919#ifndef _INCLUDE_LEON_h
    2020#define _INCLUDE_LEON_h
     
    3535 *  Source: Table 8 - Interrupt Trap Type and Default Priority Assignments
    3636 *
    37  *  NOTE: The priority level for each source corresponds to the least 
     37 *  NOTE: The priority level for each source corresponds to the least
    3838 *        significant nibble of the trap type.
    3939 */
     
    4646  ( (_trap) >= 0x11 && \
    4747    (_trap) <= 0x1F )
    48    
    49 /*
    50  *  Structure for LEON memory mapped registers. 
     48
     49/*
     50 *  Structure for LEON memory mapped registers.
    5151 *
    5252 *  Source: Section 6.1 - On-chip registers
    5353 *
    54  *  NOTE:  There is only one of these structures per CPU, its base address 
    55  *         is 0x80000000, and the variable LEON_REG is placed there by the 
     54 *  NOTE:  There is only one of these structures per CPU, its base address
     55 *         is 0x80000000, and the variable LEON_REG is placed there by the
    5656 *         linkcmds file.
    5757 */
     
    7474        volatile unsigned int dummy2;
    7575        volatile unsigned int dummy3;
    76         volatile unsigned int dummy4;   
     76        volatile unsigned int dummy4;
    7777        volatile unsigned int dummy5;
    7878        volatile unsigned int dummy6;
     
    147147/* LEON_Register_Map is obsolete */
    148148/* extern LEON_Register_Map LEON_REG; */
    149  
     149
    150150#endif
    151151
     
    162162#define LEON_MEMORY_CONFIGURATION_RAM_SIZE_MASK  0x00001E00
    163163
    164  
     164
    165165/*
    166166 *  The following defines the bits in the Timer Control Register.
     
    179179 */
    180180
    181 #define LEON_REG_UART_CONTROL_RTD  0x000000FF /* RX/TX data */ 
    182  
     181#define LEON_REG_UART_CONTROL_RTD  0x000000FF /* RX/TX data */
     182
    183183/*
    184184 *  The following defines the bits in the LEON UART Status Registers.
     
    194194#define LEON_REG_UART_STATUS_ERR  0x00000078 /* Error Mask */
    195195
    196  
     196
    197197/*
    198198 *  The following defines the bits in the LEON UART Status Registers.
     
    244244    LEON3_IrqCtrl_Regs->iforce = (1 << (_source)); \
    245245  } while (0)
    246  
     246
    247247#define LEON_Is_interrupt_pending( _source ) \
    248248  (LEON3_IrqCtrl_Regs.ipend & (1 << (_source)))
    249  
     249
    250250#define LEON_Is_interrupt_masked( _source ) \
    251251  do {\
     
    253253   } while (0)
    254254
    255  
     255
    256256#define LEON_Mask_interrupt( _source ) \
    257257  do { \
     
    261261    sparc_enable_interrupts( _level ); \
    262262  } while (0)
    263  
     263
    264264#define LEON_Unmask_interrupt( _source ) \
    265265  do { \
     
    280280    (_previous) &= _mask; \
    281281  } while (0)
    282  
     282
    283283#define LEON_Restore_interrupt( _source, _previous ) \
    284284  do { \
     
    304304 *
    305305 *    D2 - Counter Load
    306  *          1 = load counter with preset value 
     306 *          1 = load counter with preset value
    307307 *          0 = no function
    308308 *
  • c/src/lib/libbsp/sparc/leon3/leon_greth/leon_greth.c

    refdfd48 r44b06ca  
    2525#define TDA_COUNT     32
    2626
    27 greth_configuration_t leon_greth_configuration; 
     27greth_configuration_t leon_greth_configuration;
    2828
    2929int rtems_leon_greth_driver_attach(
     
    3939  /* Scan for MAC AHB slave interface */
    4040        device_found = amba_find_apbslv(&amba_conf,VENDOR_GAISLER,GAISLER_ETHMAC,&apbgreth);
    41   if (device_found == 1) 
     41  if (device_found == 1)
    4242  {
    4343                base_addr = apbgreth.start;
    4444                eth_irq = apbgreth.irq + 0x10;
    45                
     45
    4646    /* clear control register and reset NIC */
    4747    *(volatile int *) base_addr = 0;
     
    5555      LEON_Clear_interrupt(leon_greth_configuration.vector);
    5656      LEON_Unmask_interrupt(leon_greth_configuration.vector);
    57     } 
     57    }
    5858  }
    5959  return 0;
  • c/src/lib/libbsp/sparc/leon3/leon_open_eth/leon_open_eth.c

    refdfd48 r44b06ca  
    2525#define TDA_COUNT     16
    2626
    27 open_eth_configuration_t leon_open_eth_configuration; 
     27open_eth_configuration_t leon_open_eth_configuration;
    2828
    2929int rtems_leon_open_eth_driver_attach(
     
    5555
    5656
    57   if (device_found) 
     57  if (device_found)
    5858  {
    5959    /* clear control register and reset NIC */
     
    7070      LEON_Clear_interrupt(leon_open_eth_configuration.vector);
    7171      LEON_Unmask_interrupt(leon_open_eth_configuration.vector);
    72     } 
     72    }
    7373  }
    7474  return 0;
  • c/src/lib/libbsp/sparc/leon3/leon_smc91111/leon_smc91111.c

    refdfd48 r44b06ca  
    1313
    1414scmv91111_configuration_t leon_scmv91111_configuration = {
    15   SMC91111_BASE_ADDR,                 /* base address */ 
     15  SMC91111_BASE_ADDR,                 /* base address */
    1616    LEON_TRAP_TYPE (SMC91111_BASE_IRQ), /* vector number */
    17   SMC91111_BASE_PIO,                  /* PIO */ 
     17  SMC91111_BASE_PIO,                  /* PIO */
    1818    100,                        /* 100b */
    1919  1,                                  /* fulldx */
     
    3636  amba_apb_device apbpio;
    3737  amba_ahb_device apbmctrl;
    38  
     38
    3939  if ( amba_find_apbslv(&amba_conf,VENDOR_GAISLER,GAISLER_PIOPORT,&apbpio) != 1 ){
    4040    printk("SMC9111_leon3: didn't find PIO\n");
    4141    return 0;
    4242  }
    43  
     43
    4444  /* Find LEON2 memory controller */
    4545  if ( amba_find_ahbslv(&amba_conf,VENDOR_ESA,ESA_MCTRL,&apbmctrl) != 1 ){
     
    5050    }
    5151  }
    52  
     52
    5353  /* Get  controller address */
    5454  addr_mctrl = (unsigned long) apbmctrl.start;
    5555  io = (LEON3_IOPORT_Regs_Map *) apbpio.start;
    56  
     56
    5757  printk(
    5858        "Activating Leon3 io port for smsc_lan91cxx (pio:%x mctrl:%x)\n",
    5959        (unsigned int)io,
    6060        (unsigned int)addr_mctrl);
    61  
     61
    6262  /* Setup PIO IRQ */
    6363  io->irqmask |= (1 << leon_scmv91111_configuration.pio);
  • c/src/lib/libbsp/sparc/leon3/pci/pci.c

    refdfd48 r44b06ca  
    2020 *
    2121 *
    22  *  Adapted to GRPCI 
     22 *  Adapted to GRPCI
    2323 *  Copyright (C) 2006 Gaisler Research
    2424 *
     
    4040
    4141/* Define PCI_INFO to get a listing of configured devices at boot time */
    42 #define PCI_INFO 1 
    43 
    44 #define DEBUG 1 
     42#define PCI_INFO 1
     43
     44#define DEBUG 1
    4545
    4646#ifdef DEBUG
    4747#define DBG(x...) printk(x)
    4848#else
    49 #define DBG(x...) 
     49#define DBG(x...)
    5050#endif
    5151
     
    6767 * Bit encode for PCI_CONFIG_HEADER_TYPE register
    6868 */
    69 unsigned char ucMaxPCIBus; 
     69unsigned char ucMaxPCIBus;
    7070typedef struct {
    7171        volatile unsigned int cfg_stat;
     
    9696 *  AT697 pci controller to be able access all slots
    9797 */
    98  
     98
    9999
    100100static int
     
    110110
    111111    if (offset & 3) return PCIBIOS_BAD_REGISTER_NUMBER;
    112        
     112
    113113    if (slot > 21) {
    114114        *val = 0xffffffff;
     
    129129    }
    130130
    131    DBG("pci_read - bus: %d, dev: %d, fn: %d, off: %d => addr: %x, val: %x\n", bus, slot, function, offset,  (1<<(11+slot) ) | ((function & 7)<<8) |  (offset&0x3f), *val); 
     131   DBG("pci_read - bus: %d, dev: %d, fn: %d, off: %d => addr: %x, val: %x\n", bus, slot, function, offset,  (1<<(11+slot) ) | ((function & 7)<<8) |  (offset&0x3f), *val);
    132132
    133133    return PCIBIOS_SUCCESSFUL;
     
    135135
    136136
    137 static int 
     137static int
    138138BSP_pci_read_config_word(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned short *val) {
    139139    unsigned int v;
     
    148148
    149149
    150 static int 
     150static int
    151151BSP_pci_read_config_byte(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned char *val) {
    152152    unsigned int v;
     
    180180    *pci_conf = value;
    181181
    182     DBG("pci write - bus: %d, dev: %d, fn: %d, off: %d => addr: %x, val: %x\n", bus, slot, function, offset, (1<<(11+slot) ) | ((function & 7)<<8) |  (offset&0x3f), value); 
     182    DBG("pci write - bus: %d, dev: %d, fn: %d, off: %d => addr: %x, val: %x\n", bus, slot, function, offset, (1<<(11+slot) ) | ((function & 7)<<8) |  (offset&0x3f), value);
    183183
    184184    return PCIBIOS_SUCCESSFUL;
     
    186186
    187187
    188 static int 
     188static int
    189189BSP_pci_write_config_word(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned short val) {
    190190    unsigned int v;
     
    200200
    201201
    202 static int 
     202static int
    203203BSP_pci_write_config_byte(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned char val) {
    204204    unsigned int v;
     
    207207
    208208    v = (v & ~(0xff << (8*(offset&3)))) | ((0xff&val) << (8*(offset&3)));
    209    
     209
    210210    return pci_write_config_dword(bus, slot, function, offset&~3, v);
    211211}
     
    239239    pci_write_config_dword(0,0,0,0x10, flip_dword(0x10000000));    /* Setup bar0 to nonzero value (grpci considers BAR==0 as invalid) */
    240240    addr = (~flip_dword(addr)+1)>>1;                               /* page0 is accessed through upper half of bar0 */
    241     pcic->cfg_stat |= 0x10000000;                                  /* Setup mmap reg so we can reach bar0 */ 
     241    pcic->cfg_stat |= 0x10000000;                                  /* Setup mmap reg so we can reach bar0 */
    242242    page0[addr/4] = 0;                                             /* Disable bytetwisting ... */
    243243#endif
    244  
     244
    245245    /* set 1:1 mapping between AHB -> PCI memory */
    246246    pcic->cfg_stat = (pcic->cfg_stat & 0x0fffffff) | PCI_MEM_START;
    247    
    248     /* and map system RAM at pci address 0x40000000 */ 
     247
     248    /* and map system RAM at pci address 0x40000000 */
    249249    pci_write_config_dword(0, 0, 0, 0x14, 0x40000000);
    250250    pcic->page1 = 0x40000000;
    251    
    252      /* set as bus master and enable pci memory responses */ 
     251
     252     /* set as bus master and enable pci memory responses */
    253253    pci_read_config_dword(0, 0, 0, 0x4, &data);
    254     pci_write_config_dword(0, 0, 0, 0x4, data | 0x6); 
     254    pci_write_config_dword(0, 0, 0, 0x4, data | 0x6);
    255255
    256256    return 0;
     
    265265    pcidma[2] = pci_addr;
    266266    pcidma[3] = len;
    267     pcidma[0] = 0x83;       
     267    pcidma[0] = 0x83;
    268268
    269269    while ( (pcidma[0] & 0x4) == 0)
    270270        ;
    271271
    272     if (pcidma[0] & 0x8) { /* error */ 
     272    if (pcidma[0] & 0x8) { /* error */
    273273        ret = -1;
    274274    }
    275275
    276     pcidma[0] |= 0xC; 
     276    pcidma[0] |= 0xC;
    277277    return ret;
    278278
     
    286286    pcidma[2] = pci_addr;
    287287    pcidma[3] = len;
    288     pcidma[0] = 0x81;       
     288    pcidma[0] = 0x81;
    289289
    290290    while ( (pcidma[0] & 0x4) == 0)
    291291        ;
    292292
    293     if (pcidma[0] & 0x8) { /* error */ 
     293    if (pcidma[0] & 0x8) { /* error */
    294294        ret = -1;
    295295    }
    296296
    297     pcidma[0] |= 0xC; 
     297    pcidma[0] |= 0xC;
    298298    return ret;
    299299
    300 } 
     300}
    301301
    302302
     
    305305
    306306    pci_read_config_dword(0, slot, function, PCI_COMMAND, &data);
    307     pci_write_config_dword(0, slot, function, PCI_COMMAND, data | PCI_COMMAND_MEMORY); 
     307    pci_write_config_dword(0, slot, function, PCI_COMMAND, data | PCI_COMMAND_MEMORY);
    308308
    309309}
     
    313313
    314314    pci_read_config_dword(0, slot, function, PCI_COMMAND, &data);
    315     pci_write_config_dword(0, slot, function, PCI_COMMAND, data | PCI_COMMAND_MASTER); 
     315    pci_write_config_dword(0, slot, function, PCI_COMMAND, data | PCI_COMMAND_MASTER);
    316316
    317317}
     
    331331 * latency timers are set to 40.
    332332 *
    333  * NOTE that it only allocates PCI memory space devices (that are at least 1 KB). 
    334  * IO spaces are not enabled. Also, it does not handle pci-pci bridges. They are left disabled. 
     333 * NOTE that it only allocates PCI memory space devices (that are at least 1 KB).
     334 * IO spaces are not enabled. Also, it does not handle pci-pci bridges. They are left disabled.
    335335 *
    336336 *
     
    345345
    346346    for (i = 0; i < 32*8*6; i++) {
    347         res[i] = (struct pci_res *) malloc(sizeof(struct pci_res));     
     347        res[i] = (struct pci_res *) malloc(sizeof(struct pci_res));
    348348        res[i]->size = 0;
    349349        res[i]->devfn = i;
     
    362362
    363363        pci_read_config_byte(0, slot, 0, PCI_HEADER_TYPE, &header);
    364      
     364
    365365        if(header & PCI_MULTI_FUNCTION) {
    366366            numfuncs = PCI_MAX_FUNCTIONS;
     
    382382                continue;
    383383            }
    384            
     384
    385385            for (pos = 0; pos < 6; pos++) {
    386386                pci_write_config_dword(0, slot, func, PCI_BASE_ADDRESS_0 + (pos<<2), 0xffffffff);
     
    404404
    405405
    406     /* Sort the resources in descending order */ 
     406    /* Sort the resources in descending order */
    407407    swapped = 1;
    408408    while (swapped == 1) {
     
    428428            goto done;
    429429        }
    430    
     430
    431431        dev = res[i]->devfn >> 3;
    432432        fn  = res[i]->devfn & 7;
    433    
     433
    434434        DBG("Assigning PCI addr %x to device %d, function %d, bar %d\n", addr, dev, fn, res[i]->bar);
    435435        pci_write_config_dword(0, dev, fn, PCI_BASE_ADDRESS_0+res[i]->bar*4, addr);
     
    437437
    438438        /* Set latency timer to 64 */
    439         pci_read_config_dword(0, dev, fn, 0xC, &tmp);   
     439        pci_read_config_dword(0, dev, fn, 0xC, &tmp);
    440440        pci_write_config_dword(0, dev, fn, 0xC, tmp|0x4000);
    441441
    442         pci_mem_enable(0, dev, fn); 
    443 
    444     } 
    445 
    446 
    447    
     442        pci_mem_enable(0, dev, fn);
     443
     444    }
     445
     446
     447
    448448done:
    449449
     
    451451    printk("\nPCI devices found and configured:\n");
    452452    for (slot = 1; slot < PCI_MAX_DEVICES; slot++) {
    453        
    454         pci_read_config_byte(0, slot, 0, PCI_HEADER_TYPE, &header); 
    455        
     453
     454        pci_read_config_byte(0, slot, 0, PCI_HEADER_TYPE, &header);
     455
    456456        if(header & PCI_MULTI_FUNCTION) {
    457457            numfuncs = PCI_MAX_FUNCTIONS;
     
    462462
    463463        for (func = 0; func < numfuncs; func++) {
    464            
     464
    465465            pci_read_config_dword(0, slot, func, PCI_COMMAND, &tmp);
    466466
    467             if (tmp & PCI_COMMAND_MEMORY) { 
    468                
     467            if (tmp & PCI_COMMAND_MEMORY) {
     468
    469469                pci_read_config_dword(0, slot, func, PCI_VENDOR_ID,  &id);
    470470
    471471                if (id == PCI_INVALID_VENDORDEVICEID || id == 0) continue;
    472                
     472
    473473                printk("\nSlot %d function: %d\nVendor id: 0x%x, device id: 0x%x\n", slot, func, id & 0xffff, id>>16);
    474474
     
    480480                        printk("\tBAR %d: %x\n", pos, tmp);
    481481                    }
    482                
     482
    483483                }
    484484                printk("\n");
    485485
    486             } 
     486            }
    487487
    488488        }
     
    490490    printk("\n");
    491491#endif
    492    
     492
    493493    for (i = 0; i < 1536; i++) {
    494494        free(res[i]);
     
    504504    unsigned char ucHeader;
    505505    unsigned char ucMaxSubordinate;
    506     unsigned int  ulClass, ulDeviceID; 
     506    unsigned int  ulClass, ulDeviceID;
    507507
    508508    DBG("Initializing PCI\n");
  • c/src/lib/libbsp/sparc/leon3/shmsupp/getcfg.c

    refdfd48 r44b06ca  
    8888  int i;
    8989  unsigned int tmp;
    90  
     90
    9191  BSP_shm_cfgtbl.base         = 0x40000000;
    9292  BSP_shm_cfgtbl.length       = 0x00001000;
     
    109109  BSP_shm_cfgtbl.Intr.address =
    110110     (vol_u32) &(LEON3_IrqCtrl_Regs->force[LEON3_Cpu_Index]);
    111   BSP_shm_cfgtbl.Intr.value   = 1 << LEON3_MP_IRQ ; 
     111  BSP_shm_cfgtbl.Intr.value   = 1 << LEON3_MP_IRQ ;
    112112  BSP_shm_cfgtbl.Intr.length  = 4;
    113113
     
    117117         i < (Configuration.User_multiprocessing_table)->maximum_nodes+1; i++)
    118118      tmp |= (1 << i);
    119     LEON3_IrqCtrl_Regs->mpstat = tmp; 
     119    LEON3_IrqCtrl_Regs->mpstat = tmp;
    120120  }
    121121
  • c/src/lib/libbsp/sparc/leon3/shmsupp/lock.c

    refdfd48 r44b06ca  
    4646    ".align 4\n"
    4747"LEON3_Atomic_Swap:\n"
    48 "       retl\n" 
     48"       retl\n"
    4949"       swapa [%o1] 1, %o0\n"
    50 ); 
    51                                                                        
     50);
     51
    5252
    5353
  • c/src/lib/libbsp/sparc/leon3/startup/bspidle.S

    refdfd48 r44b06ca  
    1616
    1717
    18        
     18
    1919#include <rtems/asm.h>
    20        
     20
    2121/* LEON specific power-down function */
    2222
     
    2727          ba    pwdloop
    2828          nop
    29           retl 
     29          retl
    3030          nop
    3131
  • c/src/lib/libbsp/sparc/leon3/startup/bspstart.c

    refdfd48 r44b06ca  
    2525/*
    2626 * Tells us if data cache snooping is available
    27  */ 
     27 */
    2828int CPU_SPARC_HAS_SNOOPING;
    2929
    3030/*
    3131 * set_snooping
    32  * 
     32 *
    3333 * Read the data cache configuration register to determine if
    3434 * bus snooping is available. This is needed for some drivers so
    35  * that they can select the most efficient copy routines. 
     35 * that they can select the most efficient copy routines.
    3636 *
    3737 */
    3838
    39 static inline int set_snooping(void) 
     39static inline int set_snooping(void)
    4040{
    41   int tmp;       
     41  int tmp;
    4242  asm(" lda [%1] 2, %0 "
    4343      : "=r"(tmp)
  • c/src/lib/libbsp/sparc/leon3/startup/setvec.c

    refdfd48 r44b06ca  
    2222 *
    2323 *  Ported to LEON implementation of the SPARC by On-Line Applications
    24  *  Research Corporation (OAR) under contract to the European Space 
     24 *  Research Corporation (OAR) under contract to the European Space
    2525 *  Agency (ESA).
    2626 *
    27  *  LEON modifications of respective RTEMS file: COPYRIGHT (c) 1995. 
     27 *  LEON modifications of respective RTEMS file: COPYRIGHT (c) 1995.
    2828 *  European Space Agency.
    2929 *
     
    4545  if ( type )
    4646    rtems_interrupt_catch( handler, vector, &previous_isr );
    47   else 
     47  else
    4848    _CPU_ISR_install_raw_handler( vector, handler, (void *)&previous_isr );
    4949
     
    5151
    5252  if ( LEON_INT_TRAP( real_trap ) ) {
    53    
     53
    5454    source = LEON_TRAP_SOURCE( real_trap );
    5555
  • c/src/lib/libbsp/sparc/leon3/startup/spurious.c

    refdfd48 r44b06ca  
    22 *  LEON Spurious Trap Handler
    33 *
    4  *  This is just enough of a trap handler to let us know what 
     4 *  This is just enough of a trap handler to let us know what
    55 *  the likely source of the trap was.
    66 *
    7  *  Developed as part of the port of RTEMS to the LEON implementation 
    8  *  of the SPARC by On-Line Applications Research Corporation (OAR) 
     7 *  Developed as part of the port of RTEMS to the LEON implementation
     8 *  of the SPARC by On-Line Applications Research Corporation (OAR)
    99 *  under contract to the European Space Agency (ESA).
    1010 *
     
    4747     */
    4848
    49     case 0x00: 
     49    case 0x00:
    5050      printk( "reset\n" );
    5151      break;
    52     case 0x01: 
     52    case 0x01:
    5353      printk( "instruction access exception\n" );
    5454      break;
    55     case 0x02: 
     55    case 0x02:
    5656      printk( "illegal instruction\n" );
    5757      break;
    58     case 0x03: 
     58    case 0x03:
    5959      printk( "privileged instruction\n" );
    6060      break;
    61     case 0x04: 
     61    case 0x04:
    6262      printk( "fp disabled\n" );
    6363      break;
    64     case 0x07: 
     64    case 0x07:
    6565      printk( "memory address not aligned\n" );
    6666      break;
    67     case 0x08: 
     67    case 0x08:
    6868      printk( "fp exception\n" );
    6969      break;
    70     case 0x09: 
     70    case 0x09:
    7171      printk( "Unexpected trap (0x%2d) at address XXX\n",
    7272        real_trap
     
    7474      );
    7575      break;
    76     case 0x0A: 
     76    case 0x0A:
    7777      printk( "tag overflow\n" );
    7878      break;
     
    151151
    152152    if (( trap == 5 || trap == 6 ) ||
    153         (( trap >= 0x11 ) && ( trap <= 0x1f )) || 
     153        (( trap >= 0x11 ) && ( trap <= 0x1f )) ||
    154154        (( trap >= 0x70 ) && ( trap <= 0x83 )))
    155155      continue;
  • c/src/lib/libbsp/sparc/leon3/timer/timer.c

    refdfd48 r44b06ca  
    1111 *
    1212 *  Ported to LEON implementation of the SPARC by On-Line Applications
    13  *  Research Corporation (OAR) under contract to the European Space 
     13 *  Research Corporation (OAR) under contract to the European Space
    1414 *  Agency (ESA).
    1515 *
    16  *  LEON modifications of respective RTEMS file: COPYRIGHT (c) 1995. 
     16 *  LEON modifications of respective RTEMS file: COPYRIGHT (c) 1995.
    1717 *  European Space Agency.
    1818 *
     
    2727      ((rtems_configuration_get_user_multiprocessing_table()) ? \
    2828        (rtems_configuration_get_user_multiprocessing_table()->node) - 1 : 1)
    29 #else 
     29#else
    3030  #define LEON3_TIMER_INDEX 0
    3131#endif
     
    6464  if (LEON3_Timer_Regs) {
    6565    total = LEON3_Timer_Regs->timer[LEON3_TIMER_INDEX].value;
    66    
     66
    6767    total = 0xffffff - total;
    68    
     68
    6969    if ( benchmark_timer_find_average_overhead == true )
    7070      return total;          /* in one microsecond units */
    71    
     71
    7272    if ( total < LEAST_VALID )
    7373      return 0;            /* below timer resolution */
  • c/src/lib/libbsp/sparc/shared/1553/b1553brm.c

    refdfd48 r44b06ca  
    11/*
    2  *  BRM driver 
     2 *  BRM driver
    33 *
    44 *  COPYRIGHT (c) 2006.
     
    2222
    2323/* default name to /dev/brm */
    24 #if !defined(B1553BRM_DEVNAME) || !defined(B1553BRM_DEVNAME_NO) 
     24#if !defined(B1553BRM_DEVNAME) || !defined(B1553BRM_DEVNAME_NO)
    2525 #undef B1553BRM_DEVNAME
    2626 #undef B1553BRM_DEVNAME_NO
     
    6969/* EVENT_QUEUE_SIZE sets the size of the event queue
    7070 */
    71 #define EVENT_QUEUE_SIZE           1024 
     71#define EVENT_QUEUE_SIZE           1024
    7272
    7373
     
    7777#define DBG(x...) printk(x)
    7878#else
    79 #define DBG(x...) 
     79#define DBG(x...)
    8080#endif
    8181
     
    8383#define FUNCDBG(x...) printk(x)
    8484#else
    85 #define FUNCDBG(x...) 
     85#define FUNCDBG(x...)
    8686#endif
    8787
     
    133133};
    134134
    135 typedef struct { 
     135typedef struct {
    136136
    137137    unsigned int memarea_base;
     
    141141    struct desc_table {
    142142
    143         volatile unsigned short ctrl;       
     143        volatile unsigned short ctrl;
    144144        volatile unsigned short top;
    145145        volatile unsigned short cur;
     
    161161                                unsigned short timer;  /* timer value */
    162162                        } descs[128]; /* 2k (1024 half words) */
    163                        
     163
    164164                        /* message data */
    165165                        struct {
     
    192192                        /* TX mode code descriptors */
    193193                        struct desc_table txmodes[32];
    194                        
     194
    195195                        /* RX Sub Address messages */
    196196                        struct circ_buf rxsuba_msgs[32];
     
    201201                        /* RX Mode Code messages */
    202202                        struct circ_buf txmode_msgs[32];
    203                        
    204                        
     203
     204
    205205                        /* offset to last 64bytes of 128k: tot-used-needed */
    206206                        unsigned short unused[(64*1024-(4*32*4+4*32*9*34))-16*2];
    207                        
     207
    208208                        /* interrupt log at 64 bytes from end */
    209209                        struct irq_log_list irq_logs[16];
     
    225225                        /* TX mode code descriptors */
    226226                        struct desc_table txmodes[32];
    227                        
     227
    228228                        /* RX Sub Address messages */
    229229                        struct circ_buf_2 rxsuba_msgs[32];
     
    234234                        /* RX Mode Code messages */
    235235                        struct circ_buf_1 txmode_msgs[32];
    236                        
    237                        
     236
     237
    238238                        /* offset to last 64bytes of 16k: tot-used-needed */
    239239                        unsigned short unused[8*1024 -(4*32*4 +3*32*2*34 +1*32*1*34) -16*2];
    240                        
     240
    241241                        /* interrupt log at 64 bytes from end */
    242242                        struct irq_log_list irq_logs[16];
     
    267267                int irqno;
    268268                unsigned int mode;
    269 #ifdef DEBUG                   
     269#ifdef DEBUG
    270270                unsigned int log[EVENT_QUEUE_SIZE*4];
    271271                unsigned int log_i;
    272272#endif
    273                
     273
    274274                rtems_id event_id; /* event that may be signalled upon errors, needs to be set through ioctl command BRM_SET_EVENTID */
    275275                unsigned int status;
     
    299299        i++;
    300300        data &= (data - 1);
    301     } 
     301    }
    302302
    303303    return !(i&1);
     
    347347
    348348    FUNCDBG("brm_register:\n\r");
    349                
     349
    350350                /* save amba bus pointer */
    351351                amba_bus = bus;
     
    354354                        return 1;
    355355                }
    356                        
     356
    357357#ifdef B1553BRM_LOCAL_MEM
    358358                allbrm_memarea = B1553BRM_LOCAL_MEM_ADR;
     
    360360                allbrm_memarea = 0;
    361361#endif
    362                
     362
    363363                /* Save clksel, clkdiv and brm_freq for later use */
    364364                allbrm_cfg_clksel = clksel & CLKSEL_MASK;
    365365                allbrm_cfg_clkdiv = clkdiv & CLKDIV_MASK;
    366366                allbrm_cfg_freq = brm_freq & BRM_FREQ_MASK;
    367                
     367
    368368    if ((r = rtems_io_register_driver(0, &brm_driver, &m)) == RTEMS_SUCCESSFUL) {
    369369        DBG("BRM: driver successfully registered, major: %d\n",m);
     
    405405  if ( brm->rt_event )
    406406                free(brm->rt_event);
    407        
     407
    408408        brm->bcmem = NULL;
    409409        brm->rtmem = (void *)brm->mem;
    410410
    411411        brm->rt_event = (struct rt_msg *) malloc(EVENT_QUEUE_SIZE*sizeof(struct rt_msg));
    412  
     412
    413413        if (brm->rt_event == NULL) {
    414414                DBG("BRM driver failed to allocated memory.");
     
    427427        brm->regs->w_irqctrl = 6;
    428428        brm->regs->w_ahbaddr = (unsigned int) memarea_to_hw(brm->memarea_base);
    429                
     429
    430430        clr_int_logs(brm->irq_log);
    431431
     
    435435        }
    436436
    437         /* Init descriptor table 
    438          * 
     437        /* Init descriptor table
     438         *
    439439         * Each circular buffer has room for 8 messages with up to 34 (32 data + miw + time) words (16b) in each.
    440440         * The buffers must separated by 34 words.
    441441         */
    442442
    443  
     443
    444444        /* RX Sub-address 0 - 31 */
    445445        for (i = 0; i < 32; i++) {
     
    447447                brm->rtmem->rxsubs[i].top  = OFS(brm->rtmem->rxsuba_msgs[i]);                /* Top address */
    448448                brm->rtmem->rxsubs[i].cur  = OFS(brm->rtmem->rxsuba_msgs[i]);                /* Current address */
    449                 brm->rtmem->rxsubs[i].bot  = OFS(brm->rtmem->rxsuba_msgs[i+1]) - sizeof(struct msg)/2; /* Bottom address */     
     449                brm->rtmem->rxsubs[i].bot  = OFS(brm->rtmem->rxsuba_msgs[i+1]) - sizeof(struct msg)/2; /* Bottom address */
    450450                brm->last_read[i] = OFS(brm->rtmem->rxsuba_msgs[i]);
    451451        }
     
    466466                brm->rtmem->rxmodes[i].bot  = OFS(brm->rtmem->rxmode_msgs[i+1]) - sizeof(struct msg)/2; /* Bottom address */
    467467                brm->last_read[i+64] = OFS(brm->rtmem->rxmode_msgs[i]);
    468         }   
     468        }
    469469        /* TX mode code 0 - 31 */
    470470        for (i = 0; i < 32; i++) {
     
    475475                brm->last_read[i+96] = OFS(brm->rtmem->txmode_msgs[i]);
    476476        }
    477        
     477
    478478        brm->mode = BRM_MODE_RT;
    479479
     
    490490                free(brm->rt_event);
    491491        brm->rt_event = NULL;
    492        
     492
    493493        brm->bcmem = (void *)brm->mem;
    494494        brm->rtmem = NULL;
    495495        brm->irq_log = (struct irq_log_list *)&brm->bcmem->irq_logs[0];
    496        
     496
    497497        brm->head = brm->tail = 0;
    498498        brm->rx_blocking = brm->tx_blocking = 1;
    499        
     499
    500500        brm->regs->ctrl   = 0x0006;  /* ping pong enable and enable interrupt log */
    501501        brm->regs->oper   = 0x0800;  /* configure as BC */
     
    508508        brm->regs->w_irqctrl = 6;
    509509        brm->regs->w_ahbaddr = (unsigned int) memarea_to_hw(brm->memarea_base);
    510        
     510
    511511        clr_int_logs(brm->irq_log);
    512        
     512
    513513        brm->mode = BRM_MODE_BC;
    514        
     514
    515515        return RTEMS_SUCCESSFUL;
    516516}
     
    528528  if ( brm->bm_event )
    529529                free(brm->bm_event);
    530        
     530
    531531        brm->bcmem = NULL;
    532532        brm->rtmem = NULL;
    533        
     533
    534534        brm->bm_event    = (struct bm_msg *) malloc(EVENT_QUEUE_SIZE*sizeof(struct bm_msg));
    535  
     535
    536536        if (brm->bm_event == NULL) {
    537537                DBG("BRM driver failed to allocated memory.");
     
    554554        brm->regs->w_irqctrl = 6;
    555555        brm->regs->w_ahbaddr = (unsigned int) memarea_to_hw(brm->memarea_base);
    556        
     556
    557557        clr_int_logs(brm->irq_log);
    558        
     558
    559559        brm->mode = BRM_MODE_BM;
    560        
     560
    561561        return RTEMS_SUCCESSFUL;
    562562}
     
    571571        amba_ahb_device ambadev;
    572572        char *mem;
    573    
     573
    574574        FUNCDBG("brm_initialize\n");
    575575
    576576        brm_cores = 0;
    577577        strcpy(fs_name,B1553BRM_DEVNAME);
    578        
     578
    579579        /* Find all BRM devices */
    580580        dev_cnt = amba_get_number_ahbslv_devices(amba_bus,VENDOR_GAISLER,GAISLER_BRM);
     
    584584                return -1;
    585585        }
    586                
     586
    587587        /* allocate & zero memory for the brm devices */
    588588        brms = (brm_priv *)malloc(sizeof(*brms)*dev_cnt);
     
    591591                return -1;
    592592        }
    593         memset(brms,0,sizeof(*brms)*dev_cnt);   
    594        
    595         /* Allocate memory for all device's descriptors, 
     593        memset(brms,0,sizeof(*brms)*dev_cnt);
     594
     595        /* Allocate memory for all device's descriptors,
    596596         * they must be aligned to a XXX byte boundary.
    597597         */
     
    607607                        return -1;
    608608                }
    609        
     609
    610610                /* align memory to 128k boundary */
    611611                mem = (char *)(((unsigned int)mem+0x1ffff) & ~0x1ffff);
     
    618618        for(minor=0; minor<dev_cnt; minor++){
    619619                brm = &brms[minor];
    620                
     620
    621621                /* Get AMBA AHB device info from Plug&Play */
    622622                amba_find_next_ahbslv(amba_bus,VENDOR_GAISLER,GAISLER_BRM,&ambadev,minor);
    623                
     623
    624624                /* Copy Basic HW info */
    625625                brm->regs = (void *)ambadev.start[0];
     
    628628                brm->irq = 0;
    629629#ifdef DEBUG
    630                 brm->log_i = 0; 
     630                brm->log_i = 0;
    631631                memset(brm->log,0,sizeof(brm->log));
    632632#endif
    633                
     633
    634634                /* Set unique name */
    635635                B1553BRM_DEVNAME_NO(fs_name,minor);
    636    
     636
    637637    DBG("Registering BRM core at [0x%x] irq %d, minor %d as %s\n",brm->regs,brm->irqno,minor,fs_name);
    638                
     638
    639639                /* Bind filesystem name to device number (minor) */
    640640                status = rtems_io_register_name(fs_name, major, minor);
    641641    if (status != RTEMS_SUCCESSFUL)
    642642                        rtems_fatal_error_occurred(status);
    643        
     643
    644644                /* RX Semaphore created with count = 0 */
    645645                if ( rtems_semaphore_create(rtems_build_name('B', 'M', 'R', '0'+minor),
    646646                         0,
    647                          RTEMS_FIFO|RTEMS_SIMPLE_BINARY_SEMAPHORE|RTEMS_NO_INHERIT_PRIORITY|RTEMS_LOCAL|RTEMS_NO_PRIORITY_CEILING, 
     647                         RTEMS_FIFO|RTEMS_SIMPLE_BINARY_SEMAPHORE|RTEMS_NO_INHERIT_PRIORITY|RTEMS_LOCAL|RTEMS_NO_PRIORITY_CEILING,
    648648                         0,
    649649                         &brm->rx_sem) != RTEMS_SUCCESSFUL ){
     
    655655                if ( rtems_semaphore_create(rtems_build_name('B', 'M', 'T', '0'+minor),
    656656                         1,
    657                          RTEMS_FIFO|RTEMS_SIMPLE_BINARY_SEMAPHORE|RTEMS_NO_INHERIT_PRIORITY|RTEMS_LOCAL|RTEMS_NO_PRIORITY_CEILING, 
     657                         RTEMS_FIFO|RTEMS_SIMPLE_BINARY_SEMAPHORE|RTEMS_NO_INHERIT_PRIORITY|RTEMS_LOCAL|RTEMS_NO_PRIORITY_CEILING,
    658658                         0,
    659659                         &brm->tx_sem) != RTEMS_SUCCESSFUL ){
     
    665665                if ( rtems_semaphore_create(rtems_build_name('B', 'M', 'D', '0'+minor),
    666666                         1,
    667                          RTEMS_FIFO|RTEMS_SIMPLE_BINARY_SEMAPHORE|RTEMS_NO_INHERIT_PRIORITY|RTEMS_LOCAL|RTEMS_NO_PRIORITY_CEILING, 
     667                         RTEMS_FIFO|RTEMS_SIMPLE_BINARY_SEMAPHORE|RTEMS_NO_INHERIT_PRIORITY|RTEMS_LOCAL|RTEMS_NO_PRIORITY_CEILING,
    668668                         0,
    669669                         &brm->dev_sem) != RTEMS_SUCCESSFUL ){
     
    672672    }
    673673
    674        
     674
    675675                /* Set base address of all descriptors */
    676676                brm->memarea_base = (unsigned int)&mem[(128*1024) * minor];
     
    678678                brm->mem = (volatile unsigned short *) brm->memarea_base;
    679679          brm->irq_log  = (struct irq_log_list *)(brm->memarea_base + (0xFFE0<<1)); /* last 64byte */
    680                
     680
    681681                brm->bm_event = NULL;
    682682                brm->rt_event = NULL;
    683                
     683
    684684                /* Sel clock so that we can write to BRM's registers */
    685685                brm->regs->w_ctrl = (allbrm_cfg_clksel<<9) | (allbrm_cfg_clkdiv<<5);
    686686                /* Reset BRM core */
    687687                brm->regs->w_ctrl = 1<<10 | READ_REG(&brm->regs->w_ctrl);
    688                
     688
    689689                /* Register interrupt handler */
    690690                B1553BRM_REG_INT(B1553BRM_PREFIX(_interrupt_handler), brm->irqno, brm);
    691                
     691
    692692                rt_init(brm);
    693                
     693
    694694                DBG("BRM: LOG: 0x%lx, 0x%lx\n\r",brm->log,brm);
    695695        }
    696        
     696
    697697        /* save number of BRM cores found */
    698698        brm_cores = dev_cnt;
    699        
     699
    700700        DBG("BRM initialisation done.\n");
    701        
     701
    702702        return RTEMS_SUCCESSFUL;
    703703}
     
    705705static rtems_device_driver brm_open(rtems_device_major_number major, rtems_device_minor_number minor, void *arg) {
    706706                brm_priv *brm;
    707        
     707
    708708    FUNCDBG("brm_open\n");
    709709
     
    712712        return RTEMS_UNSATISFIED; /* ENODEV */
    713713    }
    714                
     714
    715715                brm = &brms[minor];
    716    
     716
    717717    if (rtems_semaphore_obtain(brm->dev_sem, RTEMS_NO_WAIT, RTEMS_NO_TIMEOUT) != RTEMS_SUCCESSFUL) {
    718718        DBG("brm_open: resource in use\n");
    719719        return RTEMS_RESOURCE_IN_USE; /* EBUSY */
    720720    }
    721                
     721
    722722                /* Set defaults */
    723723                brm->event_id = 0;
    724    
     724
    725725    start_operation(brm);
    726  
     726
    727727    return RTEMS_SUCCESSFUL;
    728728}
    729  
     729
    730730static rtems_device_driver brm_close(rtems_device_major_number major, rtems_device_minor_number minor, void *arg)
    731731{
     
    738738        return RTEMS_SUCCESSFUL;
    739739}
    740  
     740
    741741static int get_rt_messages(brm_priv *brm, void *buf, unsigned int msg_count) {
    742742
     
    785785                brm_priv *brm = &brms[minor];
    786786    int (*get_messages)(brm_priv *brm, void *buf, unsigned int count);
    787                
     787
    788788                if ( ! (brm->mode & (BRM_MODE_RT | BRM_MODE_BM)) ){
    789789                        return RTEMS_INVALID_NAME;
    790790                }
    791  
     791
    792792    rw_args = (rtems_libio_rw_args_t *) arg;
    793    
     793
    794794    if ( ((READ_REG(&brm->regs->oper)>>8) & 3) == 1 ) { /* RT */
    795795        get_messages = get_rt_messages;
     
    816816    rw_args->bytes_moved = count;
    817817    return RTEMS_SUCCESSFUL;
    818  
     818
    819819}
    820820
     
    826826    unsigned int count=0, current, next, descriptor, wc, suba;
    827827                brm_priv *brm = &brms[minor];
    828  
     828
    829829                if ( ! (brm->mode & BRM_MODE_RT) ){
    830830                        return RTEMS_INVALID_NAME;
    831831                }
    832        
     832
    833833    rw_args = (rtems_libio_rw_args_t *) arg;
    834834    source = (struct rt_msg *) rw_args->buffer;
    835835
    836836    FUNCDBG("brm_write [%i,%i]: buf: 0x%x len: %i\n",major, minor, (unsigned int)rw_args->buffer,rw_args->count);
    837  
     837
    838838    do {
    839839
     
    847847            return RTEMS_INVALID_NAME;
    848848
    849         current = brm->desc[descriptor].cur; 
     849        current = brm->desc[descriptor].cur;
    850850        next = brm->written[suba] + 2 + wc;
    851851
    852852        if (brm->written[suba] < current) {
    853            
     853
    854854            if (next > current) {
    855855
    856                 /* No room in transmission buffer */ 
     856                /* No room in transmission buffer */
    857857
    858858                if (brm->tx_blocking && count == 0) {
     
    863863                                                                        break;
    864864                                                                }
    865                 else { 
     865                else {
    866866                    /* Translates to posix EBUSY */
    867867                    return RTEMS_RESOURCE_IN_USE;
     
    871871
    872872        memcpy((void *)&brm->mem[brm->written[suba]], &source[count], (2+wc)*2);
    873        
     873
    874874        count++;
    875875
     
    880880
    881881    }  while (count < rw_args->count);
    882  
    883     rw_args->bytes_moved = count; 
     882
     883    rw_args->bytes_moved = count;
    884884
    885885    if (count >= 0) {
     
    891891static rtems_device_driver brm_control(rtems_device_major_number major, rtems_device_minor_number minor, void *arg)
    892892{
    893    
     893
    894894    unsigned int i=0;
    895895    unsigned short ctrl, oper, cw1, cw2;
     
    900900                rtems_device_driver ret;
    901901                int len;
    902    
     902
    903903    FUNCDBG("brm_control[%d]: [%i,%i]\n",minor,major, minor);
    904  
     904
    905905    if (!ioarg) {
    906906        DBG("brm_control: invalid argument\n");
     
    918918            ret = bc_init(brm);
    919919        }
    920         else if (data[0] == 1) { 
    921             ret = rt_init(brm);                         
    922         } 
    923         else if (data[0] == 2) { 
    924             ret = bm_init(brm);                                         
     920        else if (data[0] == 1) {
     921            ret = rt_init(brm);
     922        }
     923        else if (data[0] == 2) {
     924            ret = bm_init(brm);
    925925        }else
    926926                                        ret = RTEMS_INVALID_NAME;
     
    928928                                if ( ret != RTEMS_SUCCESSFUL)
    929929                                                        return ret;
    930                                
     930
    931931        if ( brm->mode & (BRM_MODE_RT | BRM_MODE_BM ) )
    932932                                        start_operation(brm);
     
    951951        break;
    952952
    953     case BRM_SET_RT_ADDR:   
     953    case BRM_SET_RT_ADDR:
    954954        stop_operation(brm);
    955955                                oper = READ_REG(&brm->regs->oper);
     
    960960        start_operation(brm);
    961961        break;
    962  
    963     case BRM_SET_STD:   
     962
     963    case BRM_SET_STD:
    964964        stop_operation(brm);
    965965                                ctrl = READ_REG(&brm->regs->ctrl);
     
    980980
    981981    case BRM_TX_BLOCK:
    982         brm->tx_blocking     = data[0];     
     982        brm->tx_blocking     = data[0];
    983983        break;
    984984
    985     case BRM_RX_BLOCK: 
    986         brm->rx_blocking     = data[0];   
    987         break; 
     985    case BRM_RX_BLOCK:
     986        brm->rx_blocking     = data[0];
     987        break;
    988988
    989989    case BRM_DO_LIST:
     
    10301030            brm->bcmem->descs[i].cw2 = cw2;
    10311031                                                /* data pointer:
    1032                                                  * (&brm->bcmem->msg_data[i].data[0] & 0x1ffff) / 2 
     1032                                                 * (&brm->bcmem->msg_data[i].data[0] & 0x1ffff) / 2
    10331033                                                 */
    10341034            brm->bcmem->descs[i].dptr = 1024+i*32;  /* data pointer */
     
    10391039
    10401040            memcpy((void *)&brm->bcmem->msg_data[i].data[0], &cmd_list[i].data[0], cmd_list[i].wc*2);
    1041          
     1041
    10421042            i++;
    10431043        }
     
    10451045        brm->bcmem->descs[i].ctrl = 0; /* end of list */
    10461046
    1047         start_operation(brm);       
    1048 
    1049         break; 
     1047        start_operation(brm);
     1048
     1049        break;
    10501050
    10511051    case BRM_LIST_DONE:
     
    10541054          return RTEMS_INVALID_NAME;
    10551055                                }
    1056                                
     1056
    10571057                                /* Check if we are bus controller */
    10581058        if ( ((READ_REG(&brm->regs->oper)>>8) & 3) != 0 ) {
    10591059            return RTEMS_INVALID_NAME;
    10601060        }
    1061    
     1061
    10621062        if (is_executing(brm)) {
    10631063
     
    10721072                                                        return RTEMS_RESOURCE_IN_USE;
    10731073                                                }
    1074            
    1075            
     1074
     1075
    10761076        }
    10771077        else {
     
    10841084
    10851085            if (READ_DMA(&brm->bcmem->descs[i].ctrl) & 1) {
    1086                 brm->cur_list[i].ctrl |= 0x8000; /* Set BAME */ 
    1087             } 
     1086                brm->cur_list[i].ctrl |= 0x8000; /* Set BAME */
     1087            }
    10881088            if (brm->cur_list[i].ctrl & BC_TR) {
    10891089                /* RT Transmit command, copy received data */
     
    11041104                        brm->status = 0;
    11051105                        break;
    1106                
     1106
    11071107    case BRM_GET_STATUS: /* copy status */
    11081108
    11091109                        if ( !ioarg->buffer )
    11101110                                return RTEMS_INVALID_NAME;
    1111                        
     1111
    11121112                        *(unsigned int *)ioarg->buffer = brm->status;
    11131113                        break;
    1114    
     1114
    11151115                case BRM_SET_EVENTID:
    11161116                        brm->event_id = (rtems_id)ioarg->buffer;
     
    11431143        unsigned int event_status=0;
    11441144        #define SET_ERROR_DESCRIPTOR(descriptor) (event_status = (event_status & 0x0000ffff) | descriptor<<16)
    1145                
     1145
    11461146        while( (iiw=READ_REG(&brm->irq_log[brm->irq].iiw)) != 0xffff ){
    11471147                iaw=READ_REG(&brm->irq_log[brm->irq].iaw);
    1148                
     1148
    11491149                /* indicate that the interrupt log entry has been processed */
    11501150                brm->irq_log[brm->irq].iiw = 0xffff;
     
    11541154    pending    = iiw;
    11551155    brm->irq = (brm->irq + 1) % 16;
    1156                
     1156
    11571157                /* Clear the log so that we */
    1158                
    1159        
    1160     /* Subaddress accessed irq (RT only) 
     1158
     1159
     1160    /* Subaddress accessed irq (RT only)
    11611161     *
    11621162     * Can be either a receive or transmit command
     
    11641164     */
    11651165    if (pending & BRM_SUBAD_IRQ) {
    1166                                
     1166
    11671167        /* Pointer to next free message in circular buffer */
    11681168        current = READ_DMA(&brm->desc[descriptor].cur);
     
    11781178                wc = wc ? wc : 32;
    11791179            }
    1180             /* Data transmitted */ 
     1180            /* Data transmitted */
    11811181            else if (descriptor < 64) {
    1182                 wc = wc ? wc : 32; 
     1182                wc = wc ? wc : 32;
    11831183                rtems_semaphore_release(brm->tx_sem);
    11841184            }
     
    11861186            else if (descriptor < 96) {
    11871187                wc = (wc>>4);
    1188             } 
     1188            }
    11891189            /* TX Mode code */
    11901190            else if (descriptor < 128) {
     
    11921192            }
    11931193
    1194 #ifdef DEBUG           
    1195             brm->log[brm->log_i++ % EVENT_QUEUE_SIZE] = (descriptor << 16) | wc; 
     1194#ifdef DEBUG
     1195            brm->log[brm->log_i++ % EVENT_QUEUE_SIZE] = (descriptor << 16) | wc;
    11961196            brm->log[brm->log_i++ % EVENT_QUEUE_SIZE] = current;
    11971197            brm->log[brm->log_i++ % EVENT_QUEUE_SIZE] = msgadr;
     
    12001200            /* If there is room in the event queue, copy the event there */
    12011201            if (brm->head - brm->tail != EVENT_QUEUE_SIZE) {
    1202        
     1202
    12031203                /* Copy to event queue */
    12041204                                                                brm->rt_event[INDEX(brm->head)].miw = READ_DMA(&brm->mem[msgadr]);
     
    12301230            /* Wake any blocked rx thread */
    12311231            rtems_semaphore_release(brm->rx_sem);
    1232  
    1233         }
    1234        
    1235     }
    1236 
    1237     if (pending & BRM_EOL_IRQ) { 
     1232
     1233        }
     1234
     1235    }
     1236
     1237    if (pending & BRM_EOL_IRQ) {
    12381238        rtems_semaphore_release(brm->tx_sem);
    12391239    }
     
    12471247
    12481248    /* Monitor irq */
    1249     if (pending & BRM_MBC_IRQ) { 
    1250                        
     1249    if (pending & BRM_MBC_IRQ) {
     1250
    12511251        stop_operation(brm);
    12521252        brm->regs->mbc = 1;
    12531253        start_operation(brm);
    1254        
     1254
    12551255        /* If there is room in the event queue, copy the event there */
    12561256        if (brm->head - brm->tail != EVENT_QUEUE_SIZE) {
    1257            
     1257
    12581258            /* Copy to event queue */
    1259          
     1259
    12601260            brm->bm_event[INDEX(brm->head)].miw  =  READ_DMA(&brm->mem[0]);
    12611261            brm->bm_event[INDEX(brm->head)].cw1  =  READ_DMA(&brm->mem[1]);
     
    12771277/*            memcpy((void *)brm->bm_event[INDEX(brm->head)].data, &brm->mem[0x100], 32);*/
    12781278
    1279 #ifdef DEBUG           
     1279#ifdef DEBUG
    12801280            brm->log[brm->log_i++ % EVENT_QUEUE_SIZE] = READ_REG(&brm->regs->mbc);
    12811281            brm->log[brm->log_i++ % EVENT_QUEUE_SIZE] = READ_DMA(&brm->mem[0]);
     
    12851285
    12861286            brm->head++;
    1287            
     1287
    12881288        }
    12891289        else {
     
    12911291            brm->rt_event[INDEX(brm->head)].miw |= 0x8000;
    12921292        }
    1293        
     1293
    12941294        /* Wake any blocking thread */
    12951295        rtems_semaphore_release(brm->rx_sem);
    12961296
    12971297    }
    1298                
    1299                 /* The reset of the interrupts 
     1298
     1299                /* The reset of the interrupts
    13001300                 * cause a event to be signalled
    13011301                 * so that user can handle error.
     
    13081308                        signal_event=1;
    13091309                }
    1310                
     1310
    13111311                if ( pending & BRM_ILLOP_IRQ){
    13121312                        FUNCDBG("BRM: BRM_ILLOP_IRQ\n\r");
     
    13141314                        rtems_semaphore_release(brm->tx_sem);
    13151315                        event_status |= BRM_ILLOP_IRQ;
    1316                         SET_ERROR_DESCRIPTOR(descriptor);                       
     1316                        SET_ERROR_DESCRIPTOR(descriptor);
    13171317                        signal_event=1;
    13181318                }
    1319                
     1319
    13201320                if ( pending & BRM_MERR_IRQ){
    13211321                        FUNCDBG("BRM: BRM_MERR_IRQ\n\r");
     
    13241324                        signal_event=1;
    13251325                }
    1326             /* Clear Block Accessed Bit */ 
     1326            /* Clear Block Accessed Bit */
    13271327    tmp = READ_REG(&brm->desc[descriptor].ctrl);
    13281328    brm->desc[descriptor].ctrl = tmp & ~0x10;
    1329                
     1329
    13301330        } /* While */
    1331        
     1331
    13321332        /* clear interrupt flags & handle Hardware errors */
    13331333        pending = READ_REG(&brm->regs->ipend);
    1334        
     1334
    13351335        if ( pending & BRM_DMAF_IRQ){
    13361336                FUNCDBG("BRM: BRM_DMAF_IRQ\n\r");
     
    13381338                signal_event=1;
    13391339        }
    1340        
     1340
    13411341        if ( pending & BRM_WRAPF_IRQ){
    13421342                FUNCDBG("BRM: BRM_WRAPF_IRQ\n\r");
     
    13441344                signal_event=1;
    13451345        }
    1346        
     1346
    13471347        if ( pending & BRM_TAPF_IRQ){
    13481348                FUNCDBG("BRM: BRM_TAPF_IRQ\n\r");
     
    13501350                signal_event=1;
    13511351        }
    1352        
     1352
    13531353        /* Copy current mask to status mask */
    13541354        if ( event_status ){
     
    13571357                brm->status |= event_status;
    13581358        }
    1359        
     1359
    13601360        /* signal event once */
    13611361        if ( signal_event && (brm->event_id!=0) ){
    13621362                rtems_event_send(brm->event_id, event_status);
    13631363        }
    1364    
    1365 }
     1364
     1365}
  • c/src/lib/libbsp/sparc/shared/1553/b1553brm_pci.c

    refdfd48 r44b06ca  
    2222#define B1553BRM_ADR_TO
    2323
    24 /* No custom MEMAREA=>CPU used since BRM Core work with offsets 
     24/* No custom MEMAREA=>CPU used since BRM Core work with offsets
    2525 * in it's descriptors.
    2626 */
     
    3434#define B1553BRM_PREFIX(name) b1553brmpci##name
    3535
    36 /* do nothing, assume that the interrupt handler is called 
     36/* do nothing, assume that the interrupt handler is called
    3737 * setup externally calling b1553_interrupt_handler.
    3838 */
     
    8383
    8484int b1553brm_pci_register(
    85  amba_confarea_type *bus, 
    86  unsigned int clksel, 
    87  unsigned int clkdiv, 
     85 amba_confarea_type *bus,
     86 unsigned int clksel,
     87 unsigned int clkdiv,
    8888 unsigned int brm_freq,
    8989 unsigned int memarea,
     
    9292{
    9393        /* Setup configuration */
    94        
     94
    9595        /* if zero malloc will be used */
    9696        brmpci_memarea_address = memarea;
     
    101101        brmpci_cpu_address = memarea & 0xf0000000;
    102102#endif
    103        
     103
    104104        /* Register the driver */
    105105        return B1553BRM_PREFIX(_register)(bus,clksel,clkdiv,brm_freq);
    106106}
    107107
    108 /* Call this from PCI interrupt handler 
     108/* Call this from PCI interrupt handler
    109109 * irq = the irq number of the HW device local to that IRQMP controller
    110  * 
     110 *
    111111 */
    112112static void b1553brmpci_interrupt_handler(int irq, void *arg){
  • c/src/lib/libbsp/sparc/shared/1553/b1553brm_rasta.c

    refdfd48 r44b06ca  
    2222#define B1553BRM_ADR_TO
    2323
    24 /* No custom MEMAREA=>CPU used since BRM Core work with offsets 
     24/* No custom MEMAREA=>CPU used since BRM Core work with offsets
    2525 * in it's descriptors.
    2626 */
     
    3434#define B1553BRM_PREFIX(name) b1553brmrasta##name
    3535
    36 /* do nothing, assume that the interrupt handler is called 
     36/* do nothing, assume that the interrupt handler is called
    3737 * setup externally calling b1553_interrupt_handler.
    3838 */
     
    8383
    8484int b1553brm_rasta_register(
    85  amba_confarea_type *bus, 
    86  unsigned int clksel, 
    87  unsigned int clkdiv, 
     85 amba_confarea_type *bus,
     86 unsigned int clksel,
     87 unsigned int clkdiv,
    8888 unsigned int brm_freq,
    8989 unsigned int memarea,
     
    9292{
    9393        /* Setup configuration */
    94        
     94
    9595        /* if zero the malloc will be used */
    9696        brmrasta_memarea_address = memarea;
     
    101101        brmrasta_cpu_address = memarea & 0xf0000000;
    102102#endif
    103        
     103
    104104        /* Register the driver */
    105105        return B1553BRM_PREFIX(_register)(bus,clksel,clkdiv,brm_freq);
    106106}
    107107
    108 /* Call this from RASTA interrupt handler 
     108/* Call this from RASTA interrupt handler
    109109 * irq = the irq number of the HW device local to that IRQMP controller
    110  * 
     110 *
    111111 */
    112112static void b1553brmrasta_interrupt_handler(int irq, void *arg){
  • c/src/lib/libbsp/sparc/shared/amba/ambapp.c

    refdfd48 r44b06ca  
    9292       */
    9393      custom = amba_ahb_get_custom(amba_conf->ahbslv,i,1);
    94      
     94
    9595      if ( amba_ver(conf) && amba_conf->next ){
    9696        amba_conf->next->notroot = 1;
     
    123123}
    124124
    125 void 
     125void
    126126amba_apb_print_dev(int devno, unsigned int conf, unsigned int address){
    127127        int irq = amba_irq(conf);
     
    140140        unsigned int conf, iobar, address;
    141141        unsigned int apbmst;
    142        
     142
    143143        /* print all ahb masters */
    144144        printk("--- AMBA AHB Masters ---\n");
     
    147147                amba_print_dev(i,conf);
    148148        }
    149        
     149
    150150        /* print all ahb slaves */
    151151        printk("--- AMBA AHB Slaves ---\n");
     
    168168                amba_apb_print_dev(i-base,conf,address);
    169169        }
    170        
     170
    171171}
    172172/**** APB Slaves ****/
  • c/src/lib/libbsp/sparc/shared/bspgetworkarea.c

    refdfd48 r44b06ca  
    4848   */
    4949  #ifdef BSP_GET_WORK_AREA_DEBUG
    50     { 
     50    {
    5151      void *sp = __builtin_frame_address(0);
    5252      void *end = *work_area_start + *work_area_size;
  • c/src/lib/libbsp/sparc/shared/can/grcan.c

    refdfd48 r44b06ca  
    11/*
    2  *  GRCAN driver 
     2 *  GRCAN driver
    33 *
    44 *  COPYRIGHT (c) 2007.
     
    5656
    5757#ifndef IRQ_CLEAR_PENDING
    58  #define IRQ_CLEAR_PENDING(irqno) 
     58 #define IRQ_CLEAR_PENDING(irqno)
    5959#endif
    6060
    6161#ifndef IRQ_UNMASK
    62  #define IRQ_UNMASK(irqno) 
     62 #define IRQ_UNMASK(irqno)
    6363#endif
    6464
    6565#ifndef IRQ_MASK
    66  #define IRQ_MASK(irqno) 
     66 #define IRQ_MASK(irqno)
    6767#endif
    6868
     
    117117
    118118#ifdef STATICALLY_ALLOCATED_TX_BUFFER
    119 static unsigned int tx_circbuf[GRCAN_MAX_CORES][TX_BUF_SIZE] 
     119static unsigned int tx_circbuf[GRCAN_MAX_CORES][TX_BUF_SIZE]
    120120        __attribute__ ((aligned(BUFFER_ALIGNMENT_NEEDS)));
    121121#define STATIC_TX_BUF_SIZE TX_BUF_SIZE
     
    124124
    125125#ifdef STATICALLY_ALLOCATED_RX_BUFFER
    126 static unsigned int rx_circbuf[GRCAN_MAX_CORES][RX_BUF_SIZE] 
     126static unsigned int rx_circbuf[GRCAN_MAX_CORES][RX_BUF_SIZE]
    127127        __attribute__ ((aligned(BUFFER_ALIGNMENT_NEEDS)));
    128128#define STATIC_RX_BUF_SIZE RX_BUF_SIZE
     
    130130#endif
    131131
    132 /* 
     132/*
    133133 * If USE_AT697_RAM is defined the RAM on the AT697 board will be used for DMA buffers (but rx message queue is always in AT697 ram).
    134134 * USE_AT697_DMA specifies whether the messages will be fetched using DMA or PIO.
    135135 *
    136136 * RASTA_PCI_BASE is the base address of the GRPCI AHB slave
    137  * 
     137 *
    138138 * GRCAN_BUF_SIZE must be set to the size (in bytes) of the GRCAN DMA buffers.
    139139 *
    140  * RX_QUEUE_SIZE defines the number of messages that fits in the  RX message queue. On RX interrupts the messages in the DMA buffer 
     140 * RX_QUEUE_SIZE defines the number of messages that fits in the  RX message queue. On RX interrupts the messages in the DMA buffer
    141141 * are copied into the message queue (using dma if the rx buf is not in the AT697 ram).
    142142 */
    143143
    144144/*#define USE_AT697_RAM              1      */
    145 #define USE_AT697_DMA              1     
    146 #define RASTA_PCI_BASE             0xe0000000   
    147 #define GRCAN_BUF_SIZE            4096     
    148 #define RX_QUEUE_SIZE              1024         
     145#define USE_AT697_DMA              1
     146#define RASTA_PCI_BASE             0xe0000000
     147#define GRCAN_BUF_SIZE            4096
     148#define RX_QUEUE_SIZE              1024
    149149
    150150#define INDEX(x) ( x&(RX_QUEUE_SIZE-1) )
    151151
    152 /* pa(x) 
     152/* pa(x)
    153153 *
    154154 * x: address in AT697 address space
    155  * 
     155 *
    156156 * returns the address in the RASTA address space that can be used to access x with dma.
    157  * 
     157 *
    158158*/
    159159#ifdef USE_AT697_RAM
    160160static inline unsigned int pa(unsigned int addr) {
    161     return ((addr & 0x0fffffff) | RASTA_PCI_BASE);   
     161    return ((addr & 0x0fffffff) | RASTA_PCI_BASE);
    162162}
    163163#else
    164164static inline unsigned int pa(unsigned int addr) {
    165     return ((addr & 0x0fffffff) | 0x40000000);       
     165    return ((addr & 0x0fffffff) | 0x40000000);
    166166}
    167167#endif
     
    189189  int flushing;
    190190  unsigned int corefreq_hz;
    191  
     191
    192192  /* Circular DMA buffers */
    193193  void *_rx;
     
    201201  int txcomplete, rxcomplete;
    202202  int txerror, rxerror;
    203  
     203
    204204  struct grcan_filter sfilter;
    205205  struct grcan_filter afilter;
     
    207207  struct grcan_config config;
    208208  struct grcan_stats stats;
    209  
     209
    210210  rtems_id rx_sem, tx_sem, txempty_sem, dev_sem;
    211211};
     
    239239
    240240static void grcan_hw_config(
    241   struct grcan_regs *regs, 
     241  struct grcan_regs *regs,
    242242  struct grcan_config *conf);
    243  
     243
    244244static void grcan_hw_accept(
    245245  struct grcan_regs *regs,
     
    303303  unsigned int tmp;
    304304  IRQ_GLOBAL_PREPARE(oldLevel);
    305  
     305
    306306  FUNCDBG();
    307  
     307
    308308  /* Check that memory has been allocated successfully */
    309309  if ( !pDev->tx || !pDev->rx )
    310310    return RTEMS_NO_MEMORY;
    311  
     311
    312312  /* Configure FIFO configuration register
    313313   * and Setup timing
     
    321321  pDev->regs->rx0addr = MEMAREA_TO_HW((unsigned int)pDev->rx);
    322322  pDev->regs->rx0size = pDev->rxbuf_size;
    323  
     323
    324324  /* Setup Transmitter */
    325325  pDev->regs->tx0addr = MEMAREA_TO_HW((unsigned int)pDev->tx);
    326326  pDev->regs->tx0size = pDev->txbuf_size;
    327  
     327
    328328  /* Setup acceptance filters */
    329329  grcan_hw_accept(pDev->regs,&pDev->afilter);
    330  
     330
    331331  /* Sync filters */
    332332  grcan_hw_sync(pDev->regs,&pDev->sfilter);
    333  
     333
    334334  /* Clear status bits */
    335335  tmp = READ_REG(&pDev->regs->stat);
    336336  pDev->regs->stat = 0;
    337  
     337
    338338  /* Setup IRQ handling */
    339  
    340   /* Clear all IRQs */ 
     339
     340  /* Clear all IRQs */
    341341  tmp = READ_REG(&pDev->regs->pir);
    342342  pDev->regs->picr = 0x1ffff;
    343  
     343
    344344  /* unmask TxLoss|TxErrCntr|RxErrCntr|TxAHBErr|RxAHBErr|OR|OFF|PASS */
    345345  pDev->regs->imr = 0x1601f;
    346  
     346
    347347  /* Enable routing of the IRQs */
    348348  IRQ_GLOBAL_DISABLE(oldLevel);
     
    351351  IRQ_UNMASK(pDev->irq+GRCAN_IRQ_IRQ);
    352352  IRQ_GLOBAL_ENABLE(oldLevel);
    353  
     353
    354354  /* Reset some software data */
    355355  /*pDev->txerror = 0;
     
    359359  pDev->regs->rx0ctrl = GRCAN_RXCTRL_ENABLE;
    360360  pDev->regs->tx0ctrl = GRCAN_TXCTRL_ENABLE;
    361  
     361
    362362  /* Enable HurriCANe core */
    363363  pDev->regs->ctrl = GRCAN_CTRL_ENABLE;
    364  
    365   /* Leave transmitter disabled, it is enabled when 
     364
     365  /* Leave transmitter disabled, it is enabled when
    366366   * trying to send something.
    367367   */
     
    372372{
    373373  FUNCDBG();
    374      
     374
    375375  /* Mask all IRQs */
    376376  pDev->regs->imr = 0;
     
    378378  IRQ_MASK(pDev->irq+GRCAN_IRQ_RXSYNC);
    379379  IRQ_MASK(pDev->irq+GRCAN_IRQ_IRQ);
    380  
     380
    381381  /* Disable receiver & transmitter */
    382382  pDev->regs->rx0ctrl = 0;
    383383  pDev->regs->tx0ctrl = 0;
    384  
     384
    385385  /* Reset semaphores to the initial state and wakeing
    386    * all threads waiting for an IRQ. The threads that 
     386   * all threads waiting for an IRQ. The threads that
    387387   * get woken up must check for RTEMS_UNSATISFIED in
    388388   * order to determine that they should return to
     
    395395
    396396static void grcan_hw_config(
    397   struct grcan_regs *regs, 
     397  struct grcan_regs *regs,
    398398  struct grcan_config *conf
    399399  )
    400400{
    401401  unsigned int config=0;
    402  
     402
    403403  /* Reset HurriCANe Core */
    404404  regs->ctrl = 0;
    405  
     405
    406406  if ( conf->silent )
    407407    config |= GRCAN_CFG_SILENT;
    408      
     408
    409409  if ( conf->abort )
    410410    config |= GRCAN_CFG_ABORT;
    411  
     411
    412412  if ( conf->selection.selection )
    413413    config |= GRCAN_CFG_SELECTION;
    414      
     414
    415415  if ( conf->selection.enable0 )
    416416    config |= GRCAN_CFG_ENABLE0;
    417      
     417
    418418  if ( conf->selection.enable1 )
    419419    config |= GRCAN_CFG_ENABLE1;
    420  
     420
    421421  /* Timing */
    422422  config |= (conf->timing.bpr<<GRCAN_CFG_BPR_BIT) & GRCAN_CFG_BPR;
     
    425425  config |= (conf->timing.ps2<<GRCAN_CFG_PS2_BIT) & GRCAN_CFG_PS2;
    426426  config |= (conf->timing.scaler<<GRCAN_CFG_SCALER_BIT) & GRCAN_CFG_SCALER;
    427  
     427
    428428  /* Write configuration */
    429429  regs->conf = config;
    430  
     430
    431431  /* Enable HurriCANe Core */
    432432  regs->ctrl = GRCAN_CTRL_ENABLE;
     
    440440  /* Disable Sync mask totaly (if we change scode or smask
    441441   * in an unfortunate way we may trigger a sync match)
    442    */ 
     442   */
    443443  regs->rx0mask = 0xffffffff;
    444  
     444
    445445  /* Set Sync Filter in a controlled way */
    446446  regs->rx0code = afilter->code;
     
    455455  /* Disable Sync mask totaly (if we change scode or smask
    456456   * in an unfortunate way we may trigger a sync match)
    457    */ 
     457   */
    458458  regs->smask = 0xffffffff;
    459  
     459
    460460  /* Set Sync Filter in a controlled way */
    461461  regs->scode = sfilter->code;
     
    468468  unsigned int size
    469469  )
    470 { 
     470{
    471471  if ( rp == wp ) {
    472     /* read pointer and write pointer is equal only 
     472    /* read pointer and write pointer is equal only
    473473     * when RX buffer is empty.
    474474     */
    475475    return 0;
    476476  }
    477  
     477
    478478  if ( wp > rp ) {
    479479    return (wp-rp)/GRCAN_MSG_SIZE;
     
    490490{
    491491  unsigned int left;
    492  
     492
    493493  if ( rp == wp ) {
    494     /* read pointer and write pointer is equal only 
     494    /* read pointer and write pointer is equal only
    495495     * when TX buffer is empty.
    496496     */
    497497    return size/GRCAN_MSG_SIZE-WRAP_AROUND_TX_MSGS;
    498498  }
    499  
     499
    500500  /* size - 4 - abs(read-write) */
    501501  if ( wp > rp ) {
     
    504504    left = rp-wp;
    505505  }
    506  
     506
    507507  return left/GRCAN_MSG_SIZE-WRAP_AROUND_TX_MSGS;
    508508}
     
    536536        int tseg=0, tseg1=0, tseg2=0;
    537537        int sjw = 1;
    538  
     538
    539539  /* Default to 90% */
    540540  if ( (sampl_pt < 50) || (sampl_pt>99) ){
     
    546546                return -1;
    547547        }
    548        
    549         /* find best match, return -2 if no good reg 
     548
     549        /* find best match, return -2 if no good reg
    550550         * combination is available for this frequency
    551551   */
     
    564564        {
    565565                brp = core_hz / ((1 + tseg / 2) * baud) + tseg % 2;
    566                 if ((brp <= 0) || 
     566                if ((brp <= 0) ||
    567567        ( (brp > 256*1) && (brp <= 256*2) && (brp&0x1) ) ||
    568568        ( (brp > 256*2) && (brp <= 256*4) && (brp&0x3) ) ||
     
    612612                tseg2 = best_tseg - tseg1 - 2;
    613613        }
    614  
     614
    615615  /* Get scaler and BRP from pseudo BRP */
    616616  if ( best_brp <= 256 ){
     
    627627    timing->bpr = 3;
    628628  }
    629  
     629
    630630        timing->ps1    = tseg1+1;
    631631        timing->ps2    = tseg2;
     
    638638  struct grcan_priv *pDev,
    639639  struct grcan_regs *regs,
    640   CANMsg *buffer, 
     640  CANMsg *buffer,
    641641  int max
    642642  )
     
    646646  struct grcan_msg *source,tmp;
    647647  unsigned int wp,rp,size,rxmax,addr,trunk_msg_cnt;
    648  
     648
    649649  FUNCDBG();
    650  
     650
    651651  wp = READ_REG(&regs->rx0wr);
    652652  rp = READ_REG(&regs->rx0rd);
    653  
     653
    654654  /*
    655    * Due to hardware wrap around simplification write pointer will 
     655   * Due to hardware wrap around simplification write pointer will
    656656   * never reach the read pointer, at least a gap of 8 bytes.
    657657   * The only time they are equal is when the read pointer has
     
    664664     */
    665665    size = READ_REG(&regs->rx0size);
    666    
     666
    667667    /* Get number of bytes available in RX buffer */
    668668    trunk_msg_cnt = grcan_hw_rxavail(rp,wp,size);
    669    
    670     /* truncate size if user space buffer hasn't room for 
     669
     670    /* truncate size if user space buffer hasn't room for
    671671     * all received chars.
    672672     */
    673673    if ( trunk_msg_cnt > max )
    674674      trunk_msg_cnt = max;
    675    
     675
    676676    /* Read until i is 0 */
    677677    i=trunk_msg_cnt;
    678    
     678
    679679    addr = (unsigned int)pDev->rx;
    680680    source = (struct grcan_msg *)(addr + rp);
    681681    dest = buffer;
    682682    rxmax = addr + (size-GRCAN_MSG_SIZE);
    683    
     683
    684684    /* Read as many can messages as possible */
    685685    while(i>0){
     
    698698      for(j=0; j<dest->len; j++)
    699699        dest->data[j] = READ_DMA_BYTE(&source->data[j]);
    700      
     700
    701701      /* wrap around if neccessary */
    702702      source = ( (unsigned int)source >= rxmax ) ? (struct grcan_msg *)addr : source+1;
     
    705705    }
    706706    /* Increment Hardware READ pointer (mark read byte as read)
    707      * ! wait for registers to be safely re-configurable 
     707     * ! wait for registers to be safely re-configurable
    708708     */
    709709    regs->rx0ctrl = 0; /* DISABLE RX CHANNEL */
     
    732732  unsigned int tmp;
    733733  int i;
    734  
     734
    735735  DBGC(DBG_TX,"\n");
    736736  /*FUNCDBG();*/
    737  
     737
    738738  rp = READ_REG(&regs->tx0rd);
    739739  wp = READ_REG(&regs->tx0wr);
    740740  size = READ_REG(&regs->tx0size);
    741  
     741
    742742  space_left = grcan_hw_txspace(rp,wp,size);
    743  
     743
    744744  /* is circular fifo full? */
    745745  if ( space_left < 1 )
    746746    return 0;
    747  
     747
    748748  /* Truncate size */
    749749  if ( space_left > count )
    750750    space_left = count;
    751751  ret = space_left;
    752  
     752
    753753  addr = (unsigned int)pDev->tx;
    754  
     754
    755755  dest = (struct grcan_msg *)(addr + wp);
    756756  source = (CANMsg *)buffer;
    757757  txmax = addr + (size-GRCAN_MSG_SIZE);
    758  
     758
    759759  while ( space_left>0 ) {
    760760    /* Convert and write CAN message to DMA buffer */
     
    774774    space_left--;
    775775  }
    776  
    777   /* Update write pointer 
    778    * ! wait for registers to be safely re-configurable 
     776
     777  /* Update write pointer
     778   * ! wait for registers to be safely re-configurable
    779779   */
    780780  regs->tx0ctrl = 0; /* DISABLE TX CHANNEL */
     
    797797  int wait;
    798798  IRQ_GLOBAL_PREPARE(oldLevel);
    799  
     799
    800800  FUNCDBG();
    801801
    802   /*** block until receive IRQ received 
    803    * Set up a valid IRQ point so that an IRQ is received 
     802  /*** block until receive IRQ received
     803   * Set up a valid IRQ point so that an IRQ is received
    804804   * when one or more messages are received
    805805   */
    806806  IRQ_GLOBAL_DISABLE(oldLevel);
    807    
     807
    808808  size = READ_REG(&pDev->regs->rx0size);
    809809  rp = READ_REG(&pDev->regs->rx0rd);
    810810  wp = READ_REG(&pDev->regs->rx0wr);
    811  
     811
    812812  /**** Calculate IRQ Pointer ****/
    813813  irq = wp + min*GRCAN_MSG_SIZE;
     
    817817  }else
    818818    irq_trunk = irq;
    819  
     819
    820820  /* init IRQ HW */
    821821  pDev->regs->rx0irq = irq_trunk;
    822  
     822
    823823  /* Clear pending Rx IRQ */
    824824  pDev->regs->picr = GRCAN_RXIRQ_IRQ;
    825  
     825
    826826  wp = READ_REG(&pDev->regs->rx0wr);
    827  
     827
    828828  /* Calculate messages available */
    829829  dataavail = grcan_hw_rxavail(rp,wp,size);
    830  
     830
    831831  if ( dataavail < min ){
    832832    /* Still empty, proceed with sleep - Turn on IRQ (unmask irq) */
     
    838838  }
    839839  IRQ_GLOBAL_ENABLE(oldLevel);
    840    
     840
    841841    /* Wait for IRQ to fire only if has been triggered */
    842842  if ( wait ){
     
    844844      return -1; /* Device driver has been closed or stopped, return with error status */
    845845  }
    846  
     846
    847847  return 0;
    848848}
     
    850850/* Wait until min bytes available in TX circular buffer.
    851851 * The IRQ RxIrq is used to pin point the location of
    852  * 
    853  * min must be at least WRAP_AROUND_TX_BYTES bytes less 
     852 *
     853 * min must be at least WRAP_AROUND_TX_BYTES bytes less
    854854 * than max buffer for this algo to work.
    855855 *
     
    864864  unsigned int irq_trunk;
    865865  IRQ_GLOBAL_PREPARE(oldLevel);
    866  
     866
    867867  DBGC(DBG_TX,"\n");
    868868  /*FUNCDBG();*/
    869  
     869
    870870  IRQ_GLOBAL_DISABLE(oldLevel);
    871871
    872872  /*pDev->regs->tx0ctrl = GRCAN_TXCTRL_ENABLE;*/
    873  
     873
    874874  size = READ_REG(&pDev->regs->tx0size);
    875   wp = READ_REG(&pDev->regs->tx0wr); 
    876  
     875  wp = READ_REG(&pDev->regs->tx0wr);
     876
    877877  rp = READ_REG(&pDev->regs->tx0rd);
    878  
     878
    879879  /**** Calculate IRQ Pointer ****/
    880880  irq = rp + min*GRCAN_MSG_SIZE;
     
    884884  }else
    885885    irq_trunk = irq;
    886  
     886
    887887  /* trigger HW to do a IRQ when enough room in buffer */
    888888  pDev->regs->tx0irq = irq_trunk;
    889  
     889
    890890  /* Clear pending Tx IRQ */
    891891  pDev->regs->picr = GRCAN_TXIRQ_IRQ;
    892  
    893   /* One problem, if HW already gone past IRQ place the IRQ will 
     892
     893  /* One problem, if HW already gone past IRQ place the IRQ will
    894894   * never be received resulting in a thread hang. We check if so
    895895   * before proceeding.
    896    * 
    897    * has the HW already gone past the IRQ generation place? 
     896   *
     897   * has the HW already gone past the IRQ generation place?
    898898   *  == does min fit info tx buffer?
    899899   */
    900900  rp = READ_REG(&pDev->regs->tx0rd);
    901  
     901
    902902  space_left = grcan_hw_txspace(rp,wp,size);
    903  
     903
    904904  if ( space_left < min ){
    905905    /* Still too full, proceed with sleep - Turn on IRQ (unmask irq) */
     
    911911  }
    912912  IRQ_GLOBAL_ENABLE(oldLevel);
    913  
     913
    914914  /* Wait for IRQ to fire only if it has been triggered */
    915915  if ( wait ){
    916916    if ( rtems_semaphore_obtain(pDev->tx_sem, RTEMS_WAIT, 100) ==
    917917         RTEMS_UNSATISFIED ){
    918       /* Device driver has flushed us, this may be due to another thread has 
     918      /* Device driver has flushed us, this may be due to another thread has
    919919       * closed the device, this is to avoid deadlock */
    920920      return -1;
    921921    }
    922922  }
    923  
     923
    924924  /* At this point the TxIRQ has been masked, we ned not to mask it */
    925925  return 0;
     
    932932  IRQ_GLOBAL_PREPARE(oldLevel);
    933933  FUNCDBG();
    934  
     934
    935935  /* loop until all data in circular buffer has been read by hw.
    936936   * (write pointer != read pointer )
    937    * 
     937   *
    938938   * Hardware doesn't update write pointer - we do
    939939   */
     
    943943    /* Clear pending TXEmpty IRQ */
    944944    pDev->regs->picr = GRCAN_TXEMPTY_IRQ;
    945      
     945
    946946    if ( wp != READ_REG(&pDev->regs->tx0rd) ) {
    947947      /* Still not empty, proceed with sleep - Turn on IRQ (unmask irq) */
     
    955955    if ( !wait )
    956956      break;
    957    
     957
    958958    /* Wait for IRQ to wake us */
    959959    if ( rtems_semaphore_obtain(pDev->txempty_sem, RTEMS_WAIT, RTEMS_NO_TIMEOUT) ==
     
    968968{
    969969  FUNCDBG();
    970  
     970
    971971  if ( tx ) {
    972972#ifdef STATIC_TX_BUF_ADDR
     
    985985    /* Align TX buffer */
    986986    pDev->tx = (struct grcan_msg *)
    987                (((unsigned int)pDev->_tx + (BUFFER_ALIGNMENT_NEEDS-1)) & 
     987               (((unsigned int)pDev->_tx + (BUFFER_ALIGNMENT_NEEDS-1)) &
    988988               ~(BUFFER_ALIGNMENT_NEEDS-1));
    989989#endif
    990990  }
    991  
     991
    992992  if ( rx ) {
    993993#ifdef STATIC_RX_BUF_ADDR
     
    10051005
    10061006    /* Align TX buffer */
    1007     pDev->rx = (struct grcan_msg *) 
    1008                (((unsigned int)pDev->_rx + (BUFFER_ALIGNMENT_NEEDS-1)) & 
     1007    pDev->rx = (struct grcan_msg *)
     1008               (((unsigned int)pDev->_rx + (BUFFER_ALIGNMENT_NEEDS-1)) &
    10091009               ~(BUFFER_ALIGNMENT_NEEDS-1));
    10101010#endif
     
    10161016{
    10171017  FUNCDBG();
    1018  
     1018
    10191019#ifndef STATIC_TX_BUF_ADDR
    10201020  if ( tx && pDev->_tx ){
     
    10441044
    10451045static rtems_device_driver grcan_initialize(
    1046   rtems_device_major_number major, 
     1046  rtems_device_major_number major,
    10471047  rtems_device_minor_number unused,
    10481048  void *arg
     
    10601060
    10611061  FUNCDBG();
    1062  
     1062
    10631063  /* find GRCAN cores */
    1064   if ( !grcan_cores ) {   
     1064  if ( !grcan_cores ) {
    10651065    grcan_core_cnt = amba_get_number_apbslv_devices(amba_bus,VENDOR_GAISLER,deviceid);
    10661066    if ( grcan_core_cnt < 1 ){
     
    11301130    pDev->corefreq_hz = sys_freq_hz;
    11311131    GRCAN_DEVNAME_NO(fs_name,minor);
    1132    
     1132
    11331133    /* Find core address & IRQ */
    11341134    if ( !grcan_cores ) {
     
    11401140      pDev->regs = (struct grcan_regs *)grcan_cores[minor].base_address;
    11411141    }
    1142    
     1142
    11431143    printk("Registering GRCAN core at [0x%x] irq %d, minor %d as %s\n\r",pDev->regs,pDev->irq,minor,fs_name);
    1144    
     1144
    11451145    status = rtems_io_register_name(fs_name, major, 0);
    11461146    if (status != RTEMS_SUCCESSFUL)
    11471147      rtems_fatal_error_occurred(status);
    1148    
     1148
    11491149                /* Reset Hardware before attaching IRQ handler */
    11501150    grcan_hw_reset(pDev->regs);
    1151                                
     1151
    11521152    /* Register interrupt handler */
    11531153    GRCAN_REG_INT(GRCAN_PREFIX(_interrupt_handler), pDev->irq+GRCAN_IRQ_IRQ, pDev);
     
    11561156    GRCAN_REG_INT(grcan_interrupt_handler, pDev->irq+GRCAN_IRQ_RXSYNC, pDev);
    11571157    */
    1158    
     1158
    11591159    /* RX Semaphore created with count = 0 */
    11601160    if ( rtems_semaphore_create(rtems_build_name('G', 'C', 'R', '0'+minor),
    11611161        0,
    11621162        RTEMS_FIFO|RTEMS_SIMPLE_BINARY_SEMAPHORE|RTEMS_NO_INHERIT_PRIORITY|\
    1163         RTEMS_LOCAL|RTEMS_NO_PRIORITY_CEILING, 
     1163        RTEMS_LOCAL|RTEMS_NO_PRIORITY_CEILING,
    11641164        0,
    11651165        &pDev->rx_sem) != RTEMS_SUCCESSFUL )
     
    11701170        0,
    11711171        RTEMS_FIFO|RTEMS_SIMPLE_BINARY_SEMAPHORE|RTEMS_NO_INHERIT_PRIORITY|\
    1172         RTEMS_LOCAL|RTEMS_NO_PRIORITY_CEILING, 
     1172        RTEMS_LOCAL|RTEMS_NO_PRIORITY_CEILING,
    11731173        0,
    11741174        &pDev->tx_sem) != RTEMS_SUCCESSFUL )
     
    11791179        0,
    11801180        RTEMS_FIFO|RTEMS_SIMPLE_BINARY_SEMAPHORE|RTEMS_NO_INHERIT_PRIORITY|\
    1181         RTEMS_LOCAL|RTEMS_NO_PRIORITY_CEILING, 
     1181        RTEMS_LOCAL|RTEMS_NO_PRIORITY_CEILING,
    11821182        0,
    11831183        &pDev->txempty_sem) != RTEMS_SUCCESSFUL )
     
    12001200  struct grcan_priv *pDev;
    12011201  rtems_device_driver ret;
    1202  
     1202
    12031203  FUNCDBG();
    12041204
     
    12071207    return RTEMS_INVALID_NUMBER;
    12081208  }
    1209  
     1209
    12101210  pDev = &grcans[minor];
    12111211
     
    12151215    return RTEMS_INTERNAL_ERROR;
    12161216  }
    1217  
     1217
    12181218  /* is device busy/taken? */
    12191219  if  ( pDev->open ) {
     
    12401240  pDev->rxbuf_size = RX_BUF_SIZE;
    12411241  printk("Defaulting to rxbufsize: %d, txbufsize: %d\n",RX_BUF_SIZE,TX_BUF_SIZE);
    1242  
     1242
    12431243  /* Default to accept all messages */
    12441244  pDev->afilter.mask = 0x00000000;
    12451245  pDev->afilter.code = 0x00000000;
    1246    
     1246
    12471247  /* Default to disable sync messages (only trigger when id is set to all ones) */
    12481248  pDev->sfilter.mask = 0xffffffff;
    12491249  pDev->sfilter.code = 0x00000000;
    1250    
     1250
    12511251  /* Calculate default timing register values */
    12521252  grcan_calc_timing(GRCAN_DEFAULT_BAUD,pDev->corefreq_hz,GRCAN_SAMPLING_POINT,&pDev->config.timing);
    1253  
     1253
    12541254  if ( grcan_alloc_buffers(pDev,1,1) ) {
    12551255    ret=RTEMS_NO_MEMORY;
    12561256    goto out;
    12571257  }
    1258  
     1258
    12591259  /* Clear statistics */
    12601260  memset(&pDev->stats,0,sizeof(struct grcan_stats));
    1261  
     1261
    12621262  ret = RTEMS_SUCCESSFUL;
    12631263out:
     
    12691269{
    12701270  struct grcan_priv *pDev = &grcans[minor];
    1271  
     1271
    12721272  FUNCDBG();
    1273  
     1273
    12741274  if ( pDev->started )
    12751275    grcan_stop(pDev);
    1276  
     1276
    12771277  grcan_hw_reset(pDev->regs);
    1278  
     1278
    12791279  grcan_free_buffers(pDev,1,1);
    1280  
     1280
    12811281  /* Mark Device as closed */
    12821282  pDev->open = 0;
     
    12881288{
    12891289  struct grcan_priv *pDev = &grcans[minor];
    1290   rtems_libio_rw_args_t *rw_args; 
     1290  rtems_libio_rw_args_t *rw_args;
    12911291  CANMsg *dest;
    12921292  unsigned int count, left;
    12931293  int req_cnt;
    1294  
     1294
    12951295  rw_args = (rtems_libio_rw_args_t *) arg;
    12961296  dest = (CANMsg *) rw_args->buffer;
     
    12981298
    12991299  FUNCDBG();
    1300  
     1300
    13011301  if ( (!dest) || (req_cnt<1) )
    13021302    return RTEMS_INVALID_NAME;
    1303  
     1303
    13041304  if ( !pDev->started )
    13051305    return RTEMS_RESOURCE_IN_USE;
    13061306
    13071307/*  FUNCDBG("grcan_read [%i,%i]: buf: 0x%x len: %i\n",major, minor, (unsigned int)rw_args->buffer,rw_args->count);*/
    1308  
     1308
    13091309  count = grcan_hw_read_try(pDev,pDev->regs,dest,req_cnt);
    13101310  if ( !( pDev->rxblock && pDev->rxcomplete && (count!=req_cnt) ) ){
     
    13141314      return RTEMS_SUCCESSFUL;
    13151315    }
    1316  
     1316
    13171317    /* nothing read, shall we block? */
    13181318    if ( !pDev->rxblock ) {
     
    13241324
    13251325  while(count == 0 || (pDev->rxcomplete && (count!=req_cnt)) ){
    1326  
     1326
    13271327    if ( !pDev->rxcomplete ){
    13281328      left = 1; /* return as soon as there is one message available */
     
    13301330      left = req_cnt - count;     /* return as soon as all data are available */
    13311331
    1332       /* never wait for more than the half the maximum size of the receive buffer 
     1332      /* never wait for more than the half the maximum size of the receive buffer
    13331333       * Why? We need some time to copy buffer before to catch up with hw, otherwise
    13341334       * we would have to copy everything when the data has been received.
     
    13401340
    13411341    if ( grcan_wait_rxdata(pDev,left) ) {
    1342       /* The wait has been aborted, probably due to 
     1342      /* The wait has been aborted, probably due to
    13431343       * the device driver has been closed by another
    13441344       * thread.
     
    13471347      return RTEMS_UNSATISFIED;
    13481348    }
    1349    
     1349
    13501350    /* Try read bytes from circular buffer */
    13511351    count += grcan_hw_read_try(
     
    13591359  return RTEMS_SUCCESSFUL;
    13601360}
    1361  
     1361
    13621362static rtems_device_driver grcan_write(rtems_device_major_number major, rtems_device_minor_number minor, void *arg)
    13631363{
     
    13671367  unsigned int count, left;
    13681368  int req_cnt;
    1369  
     1369
    13701370  DBGC(DBG_TX,"\n");
    13711371  /*FUNCDBG();*/
    1372  
     1372
    13731373  if ( !pDev->started || pDev->config.silent || pDev->flushing )
    13741374    return RTEMS_RESOURCE_IN_USE;
    1375  
     1375
    13761376  rw_args = (rtems_libio_rw_args_t *) arg;
    13771377  req_cnt = rw_args->count / sizeof(CANMsg);
    13781378  source = (CANMsg *) rw_args->buffer;
    1379  
     1379
    13801380  /* check proper length and buffer pointer */
    13811381  if (( req_cnt < 1) || (source == NULL) ){
    13821382    return RTEMS_INVALID_NAME;
    13831383  }
    1384    
     1384
    13851385  count = grcan_hw_write_try(pDev,pDev->regs,source,req_cnt);
    13861386  if ( !(pDev->txblock && pDev->txcomplete && (count!=req_cnt)) ) {
     
    13901390      return RTEMS_SUCCESSFUL;
    13911391    }
    1392  
     1392
    13931393    /* nothing written, shall we block? */
    13941394    if ( !pDev->txblock ) {
     
    13981398    }
    13991399  }
    1400  
     1400
    14011401  /* if in txcomplete mode we need to transmit all chars */
    14021402  while((count == 0) || (pDev->txcomplete && (count!=req_cnt)) ){
    14031403    /*** block until room to fit all or as much of transmit buffer as possible IRQ comes
    1404      * Set up a valid IRQ point so that an IRQ is received 
     1404     * Set up a valid IRQ point so that an IRQ is received
    14051405     * when we can put a chunk of data into transmit fifo
    14061406     */
     
    14091409    }else{
    14101410      left = req_cnt - count; /* wait for all data to fit in buffer */
    1411    
    1412       /* never wait for more than the half the maximum size of the transmitt buffer 
     1411
     1412      /* never wait for more than the half the maximum size of the transmitt buffer
    14131413       * Why? We need some time to fill buffer before hw catches up.
    14141414       */
     
    14171417      }
    14181418    }
    1419    
     1419
    14201420    /* Wait until more room in transmit buffer */
    14211421    if ( grcan_wait_txspace(pDev,left) ){
    1422       /* The wait has been aborted, probably due to 
     1422      /* The wait has been aborted, probably due to
    14231423       * the device driver has been closed by another
    14241424       * thread. To avoid deadlock we return directly
     
    14281428      return RTEMS_UNSATISFIED;
    14291429    }
    1430    
     1430
    14311431    if ( pDev->txerror ){
    14321432      /* Return number of bytes sent, compare write pointers */
    14331433      pDev->txerror = 0;
    1434 #if 0 
     1434#if 0
    14351435#error HANDLE AMBA error
    14361436#endif
    14371437    }
    1438    
     1438
    14391439    /* Try read bytes from circular buffer */
    14401440    count += grcan_hw_write_try(
     
    14451445  }
    14461446  /* no need to unmask IRQ as IRQ Handler do that for us. */
    1447  
     1447
    14481448  rw_args->bytes_moved = count * sizeof(CANMsg);
    14491449  return RTEMS_SUCCESSFUL;
     
    14631463  struct grcan_filter *filter;
    14641464  IRQ_GLOBAL_PREPARE(oldLevel);
    1465  
     1465
    14661466  FUNCDBG();
    1467  
     1467
    14681468  if (!ioarg)
    14691469    return RTEMS_INVALID_NAME;
     
    14741474      if ( pDev->started )
    14751475        return RTEMS_RESOURCE_IN_USE; /* EBUSY */
    1476      
     1476
    14771477      if ( (status=grcan_start(pDev)) != RTEMS_SUCCESSFUL ){
    14781478        return status;
     
    14811481      pDev->started = 1;
    14821482      break;
    1483    
     1483
    14841484    case GRCAN_IOC_STOP:
    14851485      if ( !pDev->started )
    14861486        return RTEMS_RESOURCE_IN_USE;
    1487      
     1487
    14881488      grcan_stop(pDev);
    14891489      pDev->started = 0;
    14901490      break;
    1491    
     1491
    14921492    case GRCAN_IOC_ISSTARTED:
    14931493      if ( !pDev->started )
    14941494        return RTEMS_RESOURCE_IN_USE;
    14951495      break;
    1496    
     1496
    14971497    case GRCAN_IOC_FLUSH:
    14981498      if ( !pDev->started || pDev->flushing || pDev->config.silent )
    14991499        return RTEMS_RESOURCE_IN_USE;
    1500      
     1500
    15011501      pDev->flushing = 1;
    15021502      tmp = grcan_tx_flush(pDev);
    15031503      pDev->flushing = 0;
    15041504      if ( tmp ) {
    1505         /* The wait has been aborted, probably due to 
     1505        /* The wait has been aborted, probably due to
    15061506         * the device driver has been closed by another
    15071507         * thread.
     
    15101510      }
    15111511      break;
    1512    
    1513 #if 0   
     1512
     1513#if 0
    15141514    /* Set physical link */
    15151515                case GRCAN_IOC_SET_LINK:
     
    15171517                        if ( pDev->started )
    15181518                                return RTEMS_RESOURCE_IN_USE; /* EBUSY */
    1519                        
     1519
    15201520                        /* switch HW channel */
    15211521                        pDev->channel = (unsigned int)ioargs->buffer;
     
    15311531      pDev->config.silent = (int)ioarg->buffer;
    15321532      pDev->config_changed = 1;
    1533       break;   
     1533      break;
    15341534
    15351535    case GRCAN_IOC_SET_ABORT:
     
    15371537        return RTEMS_RESOURCE_IN_USE;
    15381538      pDev->config.abort = (int)ioarg->buffer;
    1539       /* This Configuration parameter doesn't need HurriCANe reset 
     1539      /* This Configuration parameter doesn't need HurriCANe reset
    15401540       * ==> no pDev->config_changed = 1;
    15411541       */
    15421542      break;
    1543    
     1543
    15441544    case GRCAN_IOC_SET_SELECTION:
    15451545      if ( pDev->started )
     
    15491549      if ( !selection )
    15501550        return RTEMS_INVALID_NAME;
    1551      
     1551
    15521552      pDev->config.selection = *selection;
    15531553      pDev->config_changed = 1;
    15541554      break;
    1555        
     1555
    15561556    case GRCAN_IOC_SET_RXBLOCK:
    15571557      pDev->rxblock = (int)ioarg->buffer;
    15581558      break;
    1559      
     1559
    15601560    case GRCAN_IOC_SET_TXBLOCK:
    15611561      pDev->txblock = (int)ioarg->buffer;
    15621562      break;
    1563    
     1563
    15641564    case GRCAN_IOC_SET_TXCOMPLETE:
    15651565      pDev->txcomplete = (int)ioarg->buffer;
     
    15691569      pDev->rxcomplete = (int)ioarg->buffer;
    15701570      break;
    1571          
     1571
    15721572    case GRCAN_IOC_GET_STATS:
    15731573      stats = (struct grcan_stats *)ioarg->buffer;
     
    15761576      *stats = pDev->stats;
    15771577      break;
    1578    
     1578
    15791579    case GRCAN_IOC_CLR_STATS:
    15801580      IRQ_GLOBAL_DISABLE(oldLevel);
     
    15841584
    15851585                case GRCAN_IOC_SET_SPEED:
    1586                
     1586
    15871587                        /* cannot change speed during run mode */
    15881588                        if ( pDev->started )
    15891589                                return RTEMS_RESOURCE_IN_USE; /* EBUSY */
    1590                        
     1590
    15911591                        /* get speed rate from argument */
    15921592                        speed = (unsigned int)ioarg->buffer;
     
    15941594                        if ( ret )
    15951595                                return  RTEMS_INVALID_NAME; /* EINVAL */
    1596                        
     1596
    15971597                        /* save timing/speed */
    15981598                        pDev->config.timing = timing;
    15991599      pDev->config_changed = 1;
    16001600                        break;
    1601    
     1601
    16021602    case GRCAN_IOC_SET_BTRS:
    1603                         /* Set BTR registers manually 
     1603                        /* Set BTR registers manually
    16041604                         * Read GRCAN/HurriCANe Manual.
    16051605                         */
    16061606                        if ( pDev->started )
    16071607                                return RTEMS_RESOURCE_IN_USE; /* EBUSY */
    1608        
     1608
    16091609                        if ( !ioarg->buffer )
    16101610        return RTEMS_INVALID_NAME;
    1611      
     1611
    16121612                        pDev->config.timing = *(struct grcan_timing *)ioarg->buffer;
    16131613      pDev->config_changed = 1;
    16141614                        break;
    1615    
     1615
    16161616    case GRCAN_IOC_SET_AFILTER:
    16171617      filter = (struct grcan_filter *)ioarg->buffer;
     
    16241624        pDev->afilter = *filter;
    16251625      }
    1626       /* Set hardware acceptance filter */     
     1626      /* Set hardware acceptance filter */
    16271627      grcan_hw_accept(pDev->regs,&pDev->afilter);
    16281628      break;
    1629    
     1629
    16301630    case GRCAN_IOC_SET_SFILTER:
    16311631      filter = (struct grcan_filter *)ioarg->buffer;
    16321632      if ( !filter ){
    16331633        /* disable TX/RX SYNC filtering */
    1634         pDev->sfilter.mask = 0xffffffff; 
     1634        pDev->sfilter.mask = 0xffffffff;
    16351635        pDev->sfilter.mask = 0;
    1636        
     1636
    16371637        /* disable Sync interrupt */
    16381638        pDev->regs->imr = READ_REG(&pDev->regs->imr) & ~(GRCAN_RXSYNC_IRQ|GRCAN_TXSYNC_IRQ);
     
    16401640        /* Save filter */
    16411641        pDev->sfilter = *filter;
    1642        
     1642
    16431643        /* Enable Sync interrupt */
    16441644        pDev->regs->imr = READ_REG(&pDev->regs->imr) | (GRCAN_RXSYNC_IRQ|GRCAN_TXSYNC_IRQ);
     
    16541654      data[0] = READ_REG(&pDev->regs->stat);
    16551655      break;
    1656  
     1656
    16571657    default:
    16581658      return RTEMS_NOT_DEFINED;
     
    16801680  unsigned int status = READ_REG(&pDev->regs->pimsr);
    16811681  unsigned int canstat = READ_REG(&pDev->regs->stat);
    1682  
     1682
    16831683  /* Spurious IRQ call? */
    16841684  if ( !status && !canstat )
    16851685    return;
    1686  
     1686
    16871687  FUNCDBG();
    1688  
     1688
    16891689  /* Increment number of interrupts counter */
    16901690  pDev->stats.ints++;
    1691  
     1691
    16921692  if ( (status & GRCAN_ERR_IRQ) || (canstat & GRCAN_STAT_PASS) ){
    16931693    /* Error-Passive interrupt */
     
    16961696
    16971697  if ( (status & GRCAN_OFF_IRQ) || (canstat & GRCAN_STAT_OFF) ){
    1698     /* Bus-off condition interrupt 
     1698    /* Bus-off condition interrupt
    16991699     * The link is brought down by hardware, we wake all threads
    17001700     * that is blocked in read/write calls and stop futher calls
     
    17061706     goto out;
    17071707  }
    1708  
     1708
    17091709  if ( (status & GRCAN_OR_IRQ) || (canstat & GRCAN_STAT_OR) ){
    17101710    /* Over-run during reception interrupt */
    17111711    pDev->stats.overrun_cnt++;
    17121712  }
    1713  
     1713
    17141714  if ( (status & GRCAN_RXAHBERR_IRQ) ||
    17151715       (status & GRCAN_TXAHBERR_IRQ) ||
     
    17191719    pDev->stats.ahberr_cnt++;
    17201720  }
    1721  
     1721
    17221722  if ( status & GRCAN_TXLOSS_IRQ ) {
    17231723    pDev->stats.txloss_cnt++;
    17241724  }
    1725  
     1725
    17261726  if ( status & GRCAN_RXIRQ_IRQ ){
    17271727    /* RX IRQ pointer interrupt */
     
    17301730    rtems_semaphore_release(pDev->rx_sem);
    17311731  }
    1732  
     1732
    17331733  if ( status & GRCAN_TXIRQ_IRQ ){
    17341734    /* TX IRQ pointer interrupt */
     
    17361736    rtems_semaphore_release(pDev->tx_sem);
    17371737  }
    1738  
     1738
    17391739  if ( status & GRCAN_TXSYNC_IRQ ){
    17401740    /* TxSync message transmitted interrupt */
    17411741    pDev->stats.txsync_cnt++;
    17421742  }
    1743  
     1743
    17441744  if ( status & GRCAN_RXSYNC_IRQ ){
    17451745    /* RxSync message received interrupt */
    17461746    pDev->stats.rxsync_cnt++;
    17471747  }
    1748  
     1748
    17491749  if ( status & GRCAN_TXEMPTY_IRQ ){
    17501750    pDev->regs->imr = READ_REG(&pDev->regs->imr) & ~GRCAN_TXEMPTY_IRQ;
    17511751    rtems_semaphore_release(pDev->txempty_sem);
    17521752  }
    1753  
    1754 out: 
     1753
     1754out:
    17551755  /* Clear IRQs */
    17561756  pDev->regs->picr = status;
     
    17611761  rtems_status_code r;
    17621762  rtems_device_major_number m;
    1763  
    1764   if ((r = rtems_io_register_driver(0, &grcan_driver, &m)) != 
     1763
     1764  if ((r = rtems_io_register_driver(0, &grcan_driver, &m)) !=
    17651765       RTEMS_SUCCESSFUL) {
    17661766    switch(r) {
    17671767      case RTEMS_TOO_MANY:
    1768         DBG2("failed RTEMS_TOO_MANY\n"); 
     1768        DBG2("failed RTEMS_TOO_MANY\n");
    17691769        break;
    17701770      case RTEMS_INVALID_NUMBER:
    1771         DBG2("failed RTEMS_INVALID_NUMBER\n"); 
     1771        DBG2("failed RTEMS_INVALID_NUMBER\n");
    17721772        break;
    17731773      case RTEMS_RESOURCE_IN_USE:
    1774         DBG2("failed RTEMS_RESOURCE_IN_USE\n"); 
     1774        DBG2("failed RTEMS_RESOURCE_IN_USE\n");
    17751775        break;
    17761776      default:
    1777         DBG("failed %i\n",r); 
     1777        DBG("failed %i\n",r);
    17781778        break;
    17791779    }
     
    17891789{
    17901790  FUNCDBG();
    1791  
     1791
    17921792  if ( !devices || (dev_cnt<0) )
    17931793    return 1;
     
    18031803{
    18041804  FUNCDBG();
    1805  
     1805
    18061806  if ( !abus )
    18071807    return 1;
  • c/src/lib/libbsp/sparc/shared/can/grcan_rasta.c

    refdfd48 r44b06ca  
    77/*#define USE_AT697_RAM              1      */
    88
    9 /* memarea_to_hw(x) 
     9/* memarea_to_hw(x)
    1010 *
    1111 * x: address in AT697 address space
    12  * 
     12 *
    1313 * returns the address in the RASTA address space that can be used to access x with dma.
    14  * 
     14 *
    1515*/
    1616#ifdef USE_AT697_RAM
    1717static inline unsigned int memarea_to_hw(unsigned int addr) {