Index: cpukit/score/cpu/arm/armv7m-context-switch.c
===================================================================
--- cpukit/score/cpu/arm/armv7m-context-switch.c	(revision 52adc808422cf415027c07c54910086227bcb973)
+++ cpukit/score/cpu/arm/armv7m-context-switch.c	(revision 43e05991513c9d3d494b88920c0fbf3ef5b547bb)
@@ -1,2 +1,8 @@
+/**
+ * @file
+ *
+ * @brief ARM7M CPU Context Switch
+ */
+
 /*
  * Copyright (c) 2011 Sebastian Huber.  All rights reserved.
Index: cpukit/score/cpu/arm/armv7m-exception-priority-handler.c
===================================================================
--- cpukit/score/cpu/arm/armv7m-exception-priority-handler.c	(revision 52adc808422cf415027c07c54910086227bcb973)
+++ cpukit/score/cpu/arm/armv7m-exception-priority-handler.c	(revision 43e05991513c9d3d494b88920c0fbf3ef5b547bb)
@@ -1,2 +1,8 @@
+/**
+ * @file
+ *
+ * @brief ARMV7M Set Exception Priority and Handler
+ */
+
 /*
  * Copyright (c) 2012 Sebastian Huber.  All rights reserved.
Index: cpukit/score/cpu/arm/armv7m-initialize.c
===================================================================
--- cpukit/score/cpu/arm/armv7m-initialize.c	(revision 52adc808422cf415027c07c54910086227bcb973)
+++ cpukit/score/cpu/arm/armv7m-initialize.c	(revision 43e05991513c9d3d494b88920c0fbf3ef5b547bb)
@@ -1,2 +1,8 @@
+/**
+ * @file
+ *
+ * @brief ARM7M CPU Initialize
+ */
+
 /*
  * Copyright (c) 2011 Sebastian Huber.  All rights reserved.
Index: cpukit/score/cpu/arm/armv7m-isr-dispatch.c
===================================================================
--- cpukit/score/cpu/arm/armv7m-isr-dispatch.c	(revision 52adc808422cf415027c07c54910086227bcb973)
+++ cpukit/score/cpu/arm/armv7m-isr-dispatch.c	(revision 43e05991513c9d3d494b88920c0fbf3ef5b547bb)
@@ -1,2 +1,8 @@
+/**
+ * @file
+ *
+ * @brief ARMV7M ISR Dispatch
+ */
+
 /*
  * Copyright (c) 2011 Sebastian Huber.  All rights reserved.
Index: cpukit/score/cpu/arm/armv7m-multitasking-start-stop.c
===================================================================
--- cpukit/score/cpu/arm/armv7m-multitasking-start-stop.c	(revision 52adc808422cf415027c07c54910086227bcb973)
+++ cpukit/score/cpu/arm/armv7m-multitasking-start-stop.c	(revision 43e05991513c9d3d494b88920c0fbf3ef5b547bb)
@@ -1,2 +1,8 @@
+/**
+ * @file
+ *
+ * @brief ARMV7M Start and Stop Multitasking
+ */
+
 /*
  * Copyright (c) 2011 Sebastian Huber.  All rights reserved.
Index: cpukit/score/cpu/arm/rtems/score/armv7m.h
===================================================================
--- cpukit/score/cpu/arm/rtems/score/armv7m.h	(revision 52adc808422cf415027c07c54910086227bcb973)
+++ cpukit/score/cpu/arm/rtems/score/armv7m.h	(revision 43e05991513c9d3d494b88920c0fbf3ef5b547bb)
@@ -458,4 +458,8 @@
 );
 
+/**
+ *  @brief ARMV7M Set Exception Priority and Handler
+ *
+ */
 void _ARMV7M_Set_exception_priority_and_handler(
   int index,
Index: cpukit/score/cpu/arm/rtems/score/cpu.h
===================================================================
--- cpukit/score/cpu/arm/rtems/score/cpu.h	(revision 52adc808422cf415027c07c54910086227bcb973)
+++ cpukit/score/cpu/arm/rtems/score/cpu.h	(revision 43e05991513c9d3d494b88920c0fbf3ef5b547bb)
@@ -399,4 +399,8 @@
    } while (0);
 
+/**
+ *  @brief CPU Initialize
+ *
+ */
 void _CPU_Initialize( void );
 
@@ -407,4 +411,8 @@
 );
 
+/**
+ *  @brief CPU Context Switch
+ *
+ */
 void _CPU_Context_switch( Context_Control *run, Context_Control *heir );
 
Index: cpukit/score/cpu/bfin/cpu.c
===================================================================
--- cpukit/score/cpu/bfin/cpu.c	(revision 52adc808422cf415027c07c54910086227bcb973)
+++ cpukit/score/cpu/bfin/cpu.c	(revision 43e05991513c9d3d494b88920c0fbf3ef5b547bb)
@@ -1,4 +1,9 @@
-/*  Blackfin CPU Dependent Source
- *
+/**
+ * @file
+ *
+ * @brief Blackfin CPU Dependent Source
+ */
+
+/*
  *  COPYRIGHT (c) 2006 by Atos Automacao Industrial Ltda.
  *             written by Alain Schaefer <alain.schaefer@easc.ch>
Index: cpukit/score/cpu/bfin/rtems/score/cpu.h
===================================================================
--- cpukit/score/cpu/bfin/rtems/score/cpu.h	(revision 52adc808422cf415027c07c54910086227bcb973)
+++ cpukit/score/cpu/bfin/rtems/score/cpu.h	(revision 43e05991513c9d3d494b88920c0fbf3ef5b547bb)
@@ -1066,4 +1066,5 @@
 
 /**
+ *  @brief CPU Initialize
  *  This routine performs CPU dependent initialization.
  *
Index: cpukit/score/cpu/m32r/context_init.c
===================================================================
--- cpukit/score/cpu/m32r/context_init.c	(revision 52adc808422cf415027c07c54910086227bcb973)
+++ cpukit/score/cpu/m32r/context_init.c	(revision 43e05991513c9d3d494b88920c0fbf3ef5b547bb)
@@ -1,2 +1,8 @@
+/**
+ * @file
+ *
+ * @brief M32R CPU Context Initialize
+ */
+
 /*
  *  COPYRIGHT (c) 1989-2008.
Index: cpukit/score/cpu/m32r/cpu.c
===================================================================
--- cpukit/score/cpu/m32r/cpu.c	(revision 52adc808422cf415027c07c54910086227bcb973)
+++ cpukit/score/cpu/m32r/cpu.c	(revision 43e05991513c9d3d494b88920c0fbf3ef5b547bb)
@@ -1,5 +1,9 @@
+/**
+ * @file
+ *
+ * @brief M32R CPU Support
+ */
+
 /*
- *  M32R CPU Dependent Source
- *
  *  COPYRIGHT (c) 1989-2008.
  *  On-Line Applications Research Corporation (OAR).
Index: cpukit/score/cpu/m32r/cpu_asm.c
===================================================================
--- cpukit/score/cpu/m32r/cpu_asm.c	(revision 52adc808422cf415027c07c54910086227bcb973)
+++ cpukit/score/cpu/m32r/cpu_asm.c	(revision 43e05991513c9d3d494b88920c0fbf3ef5b547bb)
@@ -1,9 +1,17 @@
-/*  cpu_asm.c  ===> cpu_asm.S or cpu_asm.s
+/**
+ * @file
  *
- *  NOTE:  This is supposed to be a .S or .s file NOT a C file.
+ * @brief M32R ISR Handler
+ *
+ *  cpu_asm.c  ===> cpu_asm.S or cpu_asm.s
+ *
+ *  @note This is supposed to be a .S or .s file NOT a C file.
  *
  *  M32R does not yet have interrupt support.  When this functionality
  *  is written, this file should become obsolete.
  *
+ */
+
+/*
  *  COPYRIGHT (c) 1989-2008.
  *  On-Line Applications Research Corporation (OAR).
Index: cpukit/score/cpu/m32r/rtems/score/cpu.h
===================================================================
--- cpukit/score/cpu/m32r/rtems/score/cpu.h	(revision 52adc808422cf415027c07c54910086227bcb973)
+++ cpukit/score/cpu/m32r/rtems/score/cpu.h	(revision 43e05991513c9d3d494b88920c0fbf3ef5b547bb)
@@ -796,4 +796,5 @@
 
 /**
+ *  @brief CPU Context Initialize
  *  @ingroup CPUContext
  *  Initialize the context to a state suitable for starting a
@@ -1063,4 +1064,5 @@
 
 /**
+ *  @brief CPU Initialize
  *  This routine performs CPU dependent initialization.
  *
Index: cpukit/score/cpu/nios2/irq.c
===================================================================
--- cpukit/score/cpu/nios2/irq.c	(revision 52adc808422cf415027c07c54910086227bcb973)
+++ cpukit/score/cpu/nios2/irq.c	(revision 43e05991513c9d3d494b88920c0fbf3ef5b547bb)
@@ -1,7 +1,11 @@
+/**
+ * @file
+ *
+ * @brief NIOS2 Exception and Interrupt Handler
+ *
+ * @note Derived from c4x/irq.c
+ */
+
 /*
- *  NIOS2 exception and interrupt handler
- *
- *  Derived from c4x/irq.c
- *
  *  COPYRIGHT (c) 1989-2007.
  *  On-Line Applications Research Corporation (OAR).
@@ -79,5 +83,5 @@
     active = _Nios2_Get_ctlreg_ipending();
   }
-  
+
 }
 
@@ -101,5 +105,5 @@
 
   __IIC_Handler();
-  
+
   /* Make sure that interrupts are disabled again */
   _CPU_ISR_Disable( level );
Index: cpukit/score/cpu/nios2/nios2-initialize.c
===================================================================
--- cpukit/score/cpu/nios2/nios2-initialize.c	(revision 52adc808422cf415027c07c54910086227bcb973)
+++ cpukit/score/cpu/nios2/nios2-initialize.c	(revision 43e05991513c9d3d494b88920c0fbf3ef5b547bb)
@@ -1,2 +1,8 @@
+/**
+ * @file
+ *
+ * @brief NIOS2 CPU Initialize
+ */
+
 /*
  * Copyright (c) 2006 Kolja Waschk (rtemsdev/ixo.de)
Index: cpukit/score/cpu/nios2/nios2-isr-install-raw-handler.c
===================================================================
--- cpukit/score/cpu/nios2/nios2-isr-install-raw-handler.c	(revision 52adc808422cf415027c07c54910086227bcb973)
+++ cpukit/score/cpu/nios2/nios2-isr-install-raw-handler.c	(revision 43e05991513c9d3d494b88920c0fbf3ef5b547bb)
@@ -1,2 +1,8 @@
+/**
+ * @file
+ *
+ * @brief NIOS2 CPU ISR Install Raw Handler
+ */
+
 /*
  * Copyright (c) 2006 Kolja Waschk (rtemsdev/ixo.de)
Index: cpukit/score/cpu/nios2/nios2-isr-install-vector.c
===================================================================
--- cpukit/score/cpu/nios2/nios2-isr-install-vector.c	(revision 52adc808422cf415027c07c54910086227bcb973)
+++ cpukit/score/cpu/nios2/nios2-isr-install-vector.c	(revision 43e05991513c9d3d494b88920c0fbf3ef5b547bb)
@@ -1,2 +1,8 @@
+/**
+ * @file
+ *
+ * @brief NIOS2 CPU ISR Install Vector
+ */
+
 /*
  * Copyright (c) 2006 Kolja Waschk (rtemsdev/ixo.de)
Index: cpukit/score/cpu/nios2/nios2-isr-set-level.c
===================================================================
--- cpukit/score/cpu/nios2/nios2-isr-set-level.c	(revision 52adc808422cf415027c07c54910086227bcb973)
+++ cpukit/score/cpu/nios2/nios2-isr-set-level.c	(revision 43e05991513c9d3d494b88920c0fbf3ef5b547bb)
@@ -1,2 +1,8 @@
+/**
+ * @file
+ *
+ * @brief NIOS2 ISR Set Level
+ */
+
 /*
  * Copyright (c) 2011 embedded brains GmbH
Index: cpukit/score/cpu/nios2/nios2-mpu-descriptor.c
===================================================================
--- cpukit/score/cpu/nios2/nios2-mpu-descriptor.c	(revision 52adc808422cf415027c07c54910086227bcb973)
+++ cpukit/score/cpu/nios2/nios2-mpu-descriptor.c	(revision 43e05991513c9d3d494b88920c0fbf3ef5b547bb)
@@ -1,2 +1,8 @@
+/**
+ * @file
+ *
+ * @brief NIOS2 MPU Descriptor
+ */
+
 /*
  * Copyright (c) 2011 embedded brains GmbH.  All rights reserved.
Index: cpukit/score/cpu/nios2/nios2-mpu-disable-protected.c
===================================================================
--- cpukit/score/cpu/nios2/nios2-mpu-disable-protected.c	(revision 52adc808422cf415027c07c54910086227bcb973)
+++ cpukit/score/cpu/nios2/nios2-mpu-disable-protected.c	(revision 43e05991513c9d3d494b88920c0fbf3ef5b547bb)
@@ -1,2 +1,8 @@
+/**
+ * @file
+ *
+ * @brief NIOS2 MPU Disable Protected
+ */
+
 /*
  * Copyright (c) 2011 embedded brains GmbH.  All rights reserved.
Index: cpukit/score/cpu/nios2/nios2-thread-dispatch-disabled.c
===================================================================
--- cpukit/score/cpu/nios2/nios2-thread-dispatch-disabled.c	(revision 52adc808422cf415027c07c54910086227bcb973)
+++ cpukit/score/cpu/nios2/nios2-thread-dispatch-disabled.c	(revision 43e05991513c9d3d494b88920c0fbf3ef5b547bb)
@@ -1,2 +1,8 @@
+/**
+ * @file
+ *
+ * @brief NIOS II Specific Thread Dispatch Disabled Indicator.
+ */
+
 /*
  * Copyright (c) 2011 embedded brains GmbH.  All rights reserved.
Index: cpukit/score/cpu/nios2/rtems/score/cpu.h
===================================================================
--- cpukit/score/cpu/nios2/rtems/score/cpu.h	(revision 52adc808422cf415027c07c54910086227bcb973)
+++ cpukit/score/cpu/nios2/rtems/score/cpu.h	(revision 43e05991513c9d3d494b88920c0fbf3ef5b547bb)
@@ -291,5 +291,5 @@
 /**
  * @brief Initializes the CPU context.
- * 
+ *
  * The following steps are performed:
  *  - setting a starting address
@@ -319,6 +319,14 @@
 void _CPU_Fatal_halt( uint32_t _error ) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
 
+/**
+ * @brief CPU Initialize
+ *
+ */
 void _CPU_Initialize( void );
 
+/**
+ * @brief CPU ISR Install Raw Handler
+ *
+ */
 void _CPU_ISR_install_raw_handler(
   uint32_t vector,
@@ -327,4 +335,8 @@
 );
 
+/**
+ * @brief CPU ISR Install Vector.
+ *
+ */
 void _CPU_ISR_install_vector(
   uint32_t vector,
Index: cpukit/score/cpu/nios2/rtems/score/nios2-utility.h
===================================================================
--- cpukit/score/cpu/nios2/rtems/score/nios2-utility.h	(revision 52adc808422cf415027c07c54910086227bcb973)
+++ cpukit/score/cpu/nios2/rtems/score/nios2-utility.h	(revision 43e05991513c9d3d494b88920c0fbf3ef5b547bb)
@@ -308,4 +308,8 @@
 }
 
+/*
+ *  @brief Nios2 ISR Set level
+ *
+ */
 uint32_t _Nios2_ISR_Set_level( uint32_t new_level, uint32_t status );
 
@@ -400,4 +404,8 @@
 );
 
+/**
+ * @brief Nios2 MPU Get region descriptor.
+ *
+ */
 bool _Nios2_MPU_Get_region_descriptor(
   const Nios2_MPU_Configuration *config,
@@ -489,4 +497,8 @@
 }
 
+/*
+ *  @brief Nios2 MPU Disable Protected
+ *
+ */
 uint32_t _Nios2_MPU_Disable_protected( void );
 
Index: cpukit/score/cpu/sh/context.c
===================================================================
--- cpukit/score/cpu/sh/context.c	(revision 52adc808422cf415027c07c54910086227bcb973)
+++ cpukit/score/cpu/sh/context.c	(revision 43e05991513c9d3d494b88920c0fbf3ef5b547bb)
@@ -1,2 +1,8 @@
+/**
+ * @file
+ *
+ * @brief SuperH CPU Context
+ */
+
 /*
  *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
Index: cpukit/score/cpu/sh/cpu.c
===================================================================
--- cpukit/score/cpu/sh/cpu.c	(revision 52adc808422cf415027c07c54910086227bcb973)
+++ cpukit/score/cpu/sh/cpu.c	(revision 43e05991513c9d3d494b88920c0fbf3ef5b547bb)
@@ -1,6 +1,12 @@
-/*
- *  This file contains information pertaining to the Hitachi SH
- *  processor.
- *
+/**
+ * @file
+ *
+ * @brief SuperH CPU Support
+ *
+ * This file contains information pertaining to the Hitachi SH
+ * processor.
+ */
+
+/*
  *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
  *           Bernd Becker (becker@faw.uni-ulm.de)
Index: cpukit/score/cpu/sh/rtems/score/cpu.h
===================================================================
--- cpukit/score/cpu/sh/rtems/score/cpu.h	(revision 52adc808422cf415027c07c54910086227bcb973)
+++ cpukit/score/cpu/sh/rtems/score/cpu.h	(revision 43e05991513c9d3d494b88920c0fbf3ef5b547bb)
@@ -790,9 +790,10 @@
 
 /*
+ *  @brief CPU Initialize
+ *
  *  _CPU_Initialize
  *
  *  This routine performs CPU dependent initialization.
  */
-
 void _CPU_Initialize(void);
 
@@ -867,9 +868,9 @@
 
 /*
+ *  @brief This routine saves the floating point context passed to it.
+ *
  *  _CPU_Context_save_fp
  *
- *  This routine saves the floating point context passed to it.
- */
-
+ */
 void _CPU_Context_save_fp(
   Context_Control_fp **fp_context_ptr
@@ -877,9 +878,9 @@
 
 /*
+ *  @brief This routine restores the floating point context passed to it.
+ *
  *  _CPU_Context_restore_fp
  *
- *  This routine restores the floating point context passed to it.
- */
-
+ */
 void _CPU_Context_restore_fp(
   Context_Control_fp **fp_context_ptr
Index: cpukit/score/cpu/v850/cpu.c
===================================================================
--- cpukit/score/cpu/v850/cpu.c	(revision 52adc808422cf415027c07c54910086227bcb973)
+++ cpukit/score/cpu/v850/cpu.c	(revision 43e05991513c9d3d494b88920c0fbf3ef5b547bb)
@@ -1,6 +1,6 @@
 /**
- *  @file
+ * @file
  *
- *  v850 CPU Dependent Source
+ * @brief v850 CPU Initialize
  */
 
Index: cpukit/score/cpu/v850/rtems/score/cpu.h
===================================================================
--- cpukit/score/cpu/v850/rtems/score/cpu.h	(revision 52adc808422cf415027c07c54910086227bcb973)
+++ cpukit/score/cpu/v850/rtems/score/cpu.h	(revision 43e05991513c9d3d494b88920c0fbf3ef5b547bb)
@@ -1042,4 +1042,5 @@
 
 /**
+ *  @brief CPU Initialize
  *  This routine performs CPU dependent initialization.
  *
@@ -1047,4 +1048,6 @@
  *
  *  This is implemented in C.
+ *
+ *  v850 CPU Dependent Source
  */
 void _CPU_Initialize(void);
