Changeset 43e0599 in rtems


Ignore:
Timestamp:
Dec 2, 2012, 9:23:57 PM (7 years ago)
Author:
Mathew Kallada <matkallada@…>
Branches:
4.11, master
Children:
88c47041, c05d7502
Parents:
52adc808
git-author:
Mathew Kallada <matkallada@…> (12/02/12 21:23:57)
git-committer:
Joel Sherrill <joel.sherrill@…> (12/02/12 21:23:57)
Message:

score misc: Clean up Doxygen #13 (GCI 2012)

This patch is a task from GCI 2012 which improves the Doxygen
comments in the RTEMS source.

http://www.google-melange.com/gci/task/view/google/gci2012/8013205

Location:
cpukit/score/cpu
Files:
28 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/arm/armv7m-context-switch.c

    r52adc808 r43e0599  
     1/**
     2 * @file
     3 *
     4 * @brief ARM7M CPU Context Switch
     5 */
     6
    17/*
    28 * Copyright (c) 2011 Sebastian Huber.  All rights reserved.
  • cpukit/score/cpu/arm/armv7m-exception-priority-handler.c

    r52adc808 r43e0599  
     1/**
     2 * @file
     3 *
     4 * @brief ARMV7M Set Exception Priority and Handler
     5 */
     6
    17/*
    28 * Copyright (c) 2012 Sebastian Huber.  All rights reserved.
  • cpukit/score/cpu/arm/armv7m-initialize.c

    r52adc808 r43e0599  
     1/**
     2 * @file
     3 *
     4 * @brief ARM7M CPU Initialize
     5 */
     6
    17/*
    28 * Copyright (c) 2011 Sebastian Huber.  All rights reserved.
  • cpukit/score/cpu/arm/armv7m-isr-dispatch.c

    r52adc808 r43e0599  
     1/**
     2 * @file
     3 *
     4 * @brief ARMV7M ISR Dispatch
     5 */
     6
    17/*
    28 * Copyright (c) 2011 Sebastian Huber.  All rights reserved.
  • cpukit/score/cpu/arm/armv7m-multitasking-start-stop.c

    r52adc808 r43e0599  
     1/**
     2 * @file
     3 *
     4 * @brief ARMV7M Start and Stop Multitasking
     5 */
     6
    17/*
    28 * Copyright (c) 2011 Sebastian Huber.  All rights reserved.
  • cpukit/score/cpu/arm/rtems/score/armv7m.h

    r52adc808 r43e0599  
    458458);
    459459
     460/**
     461 *  @brief ARMV7M Set Exception Priority and Handler
     462 *
     463 */
    460464void _ARMV7M_Set_exception_priority_and_handler(
    461465  int index,
  • cpukit/score/cpu/arm/rtems/score/cpu.h

    r52adc808 r43e0599  
    399399   } while (0);
    400400
     401/**
     402 *  @brief CPU Initialize
     403 *
     404 */
    401405void _CPU_Initialize( void );
    402406
     
    407411);
    408412
     413/**
     414 *  @brief CPU Context Switch
     415 *
     416 */
    409417void _CPU_Context_switch( Context_Control *run, Context_Control *heir );
    410418
  • cpukit/score/cpu/bfin/cpu.c

    r52adc808 r43e0599  
    1 /*  Blackfin CPU Dependent Source
    2  *
     1/**
     2 * @file
     3 *
     4 * @brief Blackfin CPU Dependent Source
     5 */
     6
     7/*
    38 *  COPYRIGHT (c) 2006 by Atos Automacao Industrial Ltda.
    49 *             written by Alain Schaefer <alain.schaefer@easc.ch>
  • cpukit/score/cpu/bfin/rtems/score/cpu.h

    r52adc808 r43e0599  
    10661066
    10671067/**
     1068 *  @brief CPU Initialize
    10681069 *  This routine performs CPU dependent initialization.
    10691070 *
  • cpukit/score/cpu/m32r/context_init.c

    r52adc808 r43e0599  
     1/**
     2 * @file
     3 *
     4 * @brief M32R CPU Context Initialize
     5 */
     6
    17/*
    28 *  COPYRIGHT (c) 1989-2008.
  • cpukit/score/cpu/m32r/cpu.c

    r52adc808 r43e0599  
     1/**
     2 * @file
     3 *
     4 * @brief M32R CPU Support
     5 */
     6
    17/*
    2  *  M32R CPU Dependent Source
    3  *
    48 *  COPYRIGHT (c) 1989-2008.
    59 *  On-Line Applications Research Corporation (OAR).
  • cpukit/score/cpu/m32r/cpu_asm.c

    r52adc808 r43e0599  
    1 /*  cpu_asm.c  ===> cpu_asm.S or cpu_asm.s
     1/**
     2 * @file
    23 *
    3  *  NOTE:  This is supposed to be a .S or .s file NOT a C file.
     4 * @brief M32R ISR Handler
     5 *
     6 *  cpu_asm.c  ===> cpu_asm.S or cpu_asm.s
     7 *
     8 *  @note This is supposed to be a .S or .s file NOT a C file.
    49 *
    510 *  M32R does not yet have interrupt support.  When this functionality
    611 *  is written, this file should become obsolete.
    712 *
     13 */
     14
     15/*
    816 *  COPYRIGHT (c) 1989-2008.
    917 *  On-Line Applications Research Corporation (OAR).
  • cpukit/score/cpu/m32r/rtems/score/cpu.h

    r52adc808 r43e0599  
    796796
    797797/**
     798 *  @brief CPU Context Initialize
    798799 *  @ingroup CPUContext
    799800 *  Initialize the context to a state suitable for starting a
     
    10631064
    10641065/**
     1066 *  @brief CPU Initialize
    10651067 *  This routine performs CPU dependent initialization.
    10661068 *
  • cpukit/score/cpu/nios2/irq.c

    r52adc808 r43e0599  
     1/**
     2 * @file
     3 *
     4 * @brief NIOS2 Exception and Interrupt Handler
     5 *
     6 * @note Derived from c4x/irq.c
     7 */
     8
    19/*
    2  *  NIOS2 exception and interrupt handler
    3  *
    4  *  Derived from c4x/irq.c
    5  *
    610 *  COPYRIGHT (c) 1989-2007.
    711 *  On-Line Applications Research Corporation (OAR).
     
    7983    active = _Nios2_Get_ctlreg_ipending();
    8084  }
    81  
     85
    8286}
    8387
     
    101105
    102106  __IIC_Handler();
    103  
     107
    104108  /* Make sure that interrupts are disabled again */
    105109  _CPU_ISR_Disable( level );
  • cpukit/score/cpu/nios2/nios2-initialize.c

    r52adc808 r43e0599  
     1/**
     2 * @file
     3 *
     4 * @brief NIOS2 CPU Initialize
     5 */
     6
    17/*
    28 * Copyright (c) 2006 Kolja Waschk (rtemsdev/ixo.de)
  • cpukit/score/cpu/nios2/nios2-isr-install-raw-handler.c

    r52adc808 r43e0599  
     1/**
     2 * @file
     3 *
     4 * @brief NIOS2 CPU ISR Install Raw Handler
     5 */
     6
    17/*
    28 * Copyright (c) 2006 Kolja Waschk (rtemsdev/ixo.de)
  • cpukit/score/cpu/nios2/nios2-isr-install-vector.c

    r52adc808 r43e0599  
     1/**
     2 * @file
     3 *
     4 * @brief NIOS2 CPU ISR Install Vector
     5 */
     6
    17/*
    28 * Copyright (c) 2006 Kolja Waschk (rtemsdev/ixo.de)
  • cpukit/score/cpu/nios2/nios2-isr-set-level.c

    r52adc808 r43e0599  
     1/**
     2 * @file
     3 *
     4 * @brief NIOS2 ISR Set Level
     5 */
     6
    17/*
    28 * Copyright (c) 2011 embedded brains GmbH
  • cpukit/score/cpu/nios2/nios2-mpu-descriptor.c

    r52adc808 r43e0599  
     1/**
     2 * @file
     3 *
     4 * @brief NIOS2 MPU Descriptor
     5 */
     6
    17/*
    28 * Copyright (c) 2011 embedded brains GmbH.  All rights reserved.
  • cpukit/score/cpu/nios2/nios2-mpu-disable-protected.c

    r52adc808 r43e0599  
     1/**
     2 * @file
     3 *
     4 * @brief NIOS2 MPU Disable Protected
     5 */
     6
    17/*
    28 * Copyright (c) 2011 embedded brains GmbH.  All rights reserved.
  • cpukit/score/cpu/nios2/nios2-thread-dispatch-disabled.c

    r52adc808 r43e0599  
     1/**
     2 * @file
     3 *
     4 * @brief NIOS II Specific Thread Dispatch Disabled Indicator.
     5 */
     6
    17/*
    28 * Copyright (c) 2011 embedded brains GmbH.  All rights reserved.
  • cpukit/score/cpu/nios2/rtems/score/cpu.h

    r52adc808 r43e0599  
    291291/**
    292292 * @brief Initializes the CPU context.
    293  * 
     293 *
    294294 * The following steps are performed:
    295295 *  - setting a starting address
     
    319319void _CPU_Fatal_halt( uint32_t _error ) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
    320320
     321/**
     322 * @brief CPU Initialize
     323 *
     324 */
    321325void _CPU_Initialize( void );
    322326
     327/**
     328 * @brief CPU ISR Install Raw Handler
     329 *
     330 */
    323331void _CPU_ISR_install_raw_handler(
    324332  uint32_t vector,
     
    327335);
    328336
     337/**
     338 * @brief CPU ISR Install Vector.
     339 *
     340 */
    329341void _CPU_ISR_install_vector(
    330342  uint32_t vector,
  • cpukit/score/cpu/nios2/rtems/score/nios2-utility.h

    r52adc808 r43e0599  
    308308}
    309309
     310/*
     311 *  @brief Nios2 ISR Set level
     312 *
     313 */
    310314uint32_t _Nios2_ISR_Set_level( uint32_t new_level, uint32_t status );
    311315
     
    400404);
    401405
     406/**
     407 * @brief Nios2 MPU Get region descriptor.
     408 *
     409 */
    402410bool _Nios2_MPU_Get_region_descriptor(
    403411  const Nios2_MPU_Configuration *config,
     
    489497}
    490498
     499/*
     500 *  @brief Nios2 MPU Disable Protected
     501 *
     502 */
    491503uint32_t _Nios2_MPU_Disable_protected( void );
    492504
  • cpukit/score/cpu/sh/context.c

    r52adc808 r43e0599  
     1/**
     2 * @file
     3 *
     4 * @brief SuperH CPU Context
     5 */
     6
    17/*
    28 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
  • cpukit/score/cpu/sh/cpu.c

    r52adc808 r43e0599  
    1 /*
    2  *  This file contains information pertaining to the Hitachi SH
    3  *  processor.
    4  *
     1/**
     2 * @file
     3 *
     4 * @brief SuperH CPU Support
     5 *
     6 * This file contains information pertaining to the Hitachi SH
     7 * processor.
     8 */
     9
     10/*
    511 *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
    612 *           Bernd Becker (becker@faw.uni-ulm.de)
  • cpukit/score/cpu/sh/rtems/score/cpu.h

    r52adc808 r43e0599  
    790790
    791791/*
     792 *  @brief CPU Initialize
     793 *
    792794 *  _CPU_Initialize
    793795 *
    794796 *  This routine performs CPU dependent initialization.
    795797 */
    796 
    797798void _CPU_Initialize(void);
    798799
     
    867868
    868869/*
     870 *  @brief This routine saves the floating point context passed to it.
     871 *
    869872 *  _CPU_Context_save_fp
    870873 *
    871  *  This routine saves the floating point context passed to it.
    872  */
    873 
     874 */
    874875void _CPU_Context_save_fp(
    875876  Context_Control_fp **fp_context_ptr
     
    877878
    878879/*
     880 *  @brief This routine restores the floating point context passed to it.
     881 *
    879882 *  _CPU_Context_restore_fp
    880883 *
    881  *  This routine restores the floating point context passed to it.
    882  */
    883 
     884 */
    884885void _CPU_Context_restore_fp(
    885886  Context_Control_fp **fp_context_ptr
  • cpukit/score/cpu/v850/cpu.c

    r52adc808 r43e0599  
    11/**
    2  *  @file
     2 * @file
    33 *
    4  *  v850 CPU Dependent Source
     4 * @brief v850 CPU Initialize
    55 */
    66
  • cpukit/score/cpu/v850/rtems/score/cpu.h

    r52adc808 r43e0599  
    10421042
    10431043/**
     1044 *  @brief CPU Initialize
    10441045 *  This routine performs CPU dependent initialization.
    10451046 *
     
    10471048 *
    10481049 *  This is implemented in C.
     1050 *
     1051 *  v850 CPU Dependent Source
    10491052 */
    10501053void _CPU_Initialize(void);
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