Index: c/src/ChangeLog
===================================================================
--- c/src/ChangeLog	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ c/src/ChangeLog	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -1,2 +1,11 @@
+2008-05-15	Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
+
+	* libchip/i2c/spi-flash-m25p40.c, libchip/i2c/spi-flash-m25p40.h,
+	* libchip/i2c/spi-fram-fm25l256.c, libchip/i2c/spi-fram-fm25l256.h,
+	* libchip/i2c/spi-memdrv.c, libchip/i2c/spi-memdrv.h,
+	* libchip/Makefile.am:
+	derived a generic spi memory driver from spi-flash-m25p40, 
+	added descriptor for fram fm25l256
+
 2008-05-07	Till Straumann <strauman@slac.stanford.edu>
 
Index: c/src/lib/libbsp/arm/edb7312/preinstall.am
===================================================================
--- c/src/lib/libbsp/arm/edb7312/preinstall.am	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ c/src/lib/libbsp/arm/edb7312/preinstall.am	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -69,2 +69,6 @@
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/irq.h
 
+$(PROJECT_INCLUDE)/irq.h: irq/irq.h $(PROJECT_INCLUDE)/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/irq.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/irq.h
+
Index: c/src/lib/libbsp/arm/nds/preinstall.am
===================================================================
--- c/src/lib/libbsp/arm/nds/preinstall.am	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ c/src/lib/libbsp/arm/nds/preinstall.am	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -1,5 +1,3 @@
-##
-## $Id$
-##
+## Automatically generated by ampolish3 - Do not edit
 
 if AMPOLISH3
@@ -39,4 +37,8 @@
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h
 
+$(PROJECT_INCLUDE)/tm27.h: include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h
+
 $(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
@@ -47,8 +49,4 @@
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h
 
-$(PROJECT_INCLUDE)/tm27.h: include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h
-
 $(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT)
@@ -59,5 +57,183 @@
 PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds
 
+$(PROJECT_INCLUDE)/rtems/$(dirstamp):
+	@$(MKDIR_P) $(PROJECT_INCLUDE)/rtems
+	@: > $(PROJECT_INCLUDE)/rtems/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp)
+
+$(PROJECT_INCLUDE)/rtems/fb.h: fb/fb.h $(PROJECT_INCLUDE)/rtems/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/fb.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/fb.h
+
+$(PROJECT_INCLUDE)/rtems/touchscreen.h: touchscreen/touchscreen.h $(PROJECT_INCLUDE)/rtems/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/touchscreen.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/touchscreen.h
+
+$(PROJECT_INCLUDE)/rtems/sound.h: sound/sound.h $(PROJECT_INCLUDE)/rtems/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/sound.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/sound.h
+
 $(PROJECT_INCLUDE)/irq.h: irq/irq.h $(PROJECT_INCLUDE)/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/irq.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/irq.h
+
+$(PROJECT_INCLUDE)/libnds/$(dirstamp):
+	@$(MKDIR_P) $(PROJECT_INCLUDE)/libnds
+	@: > $(PROJECT_INCLUDE)/libnds/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libnds/$(dirstamp)
+
+$(PROJECT_INCLUDE)/libnds/gbfs.h: libnds/include/gbfs.h $(PROJECT_INCLUDE)/libnds/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/gbfs.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/gbfs.h
+
+$(PROJECT_INCLUDE)/libnds/nds.h: libnds/include/nds.h $(PROJECT_INCLUDE)/libnds/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds.h
+
+$(PROJECT_INCLUDE)/libnds/nds/$(dirstamp):
+	@$(MKDIR_P) $(PROJECT_INCLUDE)/libnds/nds
+	@: > $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
+
+$(PROJECT_INCLUDE)/libnds/nds/memory.h: libnds/include/nds/memory.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/memory.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/memory.h
+
+$(PROJECT_INCLUDE)/libnds/nds/system.h: libnds/include/nds/system.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/system.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/system.h
+
+$(PROJECT_INCLUDE)/libnds/nds/bios.h: libnds/include/nds/bios.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/bios.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/bios.h
+
+$(PROJECT_INCLUDE)/libnds/nds/registers_alt.h: libnds/include/nds/registers_alt.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/registers_alt.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/registers_alt.h
+
+$(PROJECT_INCLUDE)/libnds/nds/interrupts.h: libnds/include/nds/interrupts.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/interrupts.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/interrupts.h
+
+$(PROJECT_INCLUDE)/libnds/nds/card.h: libnds/include/nds/card.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/card.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/card.h
+
+$(PROJECT_INCLUDE)/libnds/nds/ipc.h: libnds/include/nds/ipc.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/ipc.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/ipc.h
+
+$(PROJECT_INCLUDE)/libnds/nds/timers.h: libnds/include/nds/timers.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/timers.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/timers.h
+
+$(PROJECT_INCLUDE)/libnds/nds/dma.h: libnds/include/nds/dma.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/dma.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/dma.h
+
+$(PROJECT_INCLUDE)/libnds/nds/reload.h: libnds/include/nds/reload.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/reload.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/reload.h
+
+$(PROJECT_INCLUDE)/libnds/nds/jtypes.h: libnds/include/nds/jtypes.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/jtypes.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/jtypes.h
+
+$(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp):
+	@$(MKDIR_P) $(PROJECT_INCLUDE)/libnds/nds/arm9
+	@: > $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
+
+$(PROJECT_INCLUDE)/libnds/nds/arm9/ndsmotion.h: libnds/include/nds/arm9/ndsmotion.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/ndsmotion.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/ndsmotion.h
+
+$(PROJECT_INCLUDE)/libnds/nds/arm9/pcx.h: libnds/include/nds/arm9/pcx.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/pcx.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/pcx.h
+
+$(PROJECT_INCLUDE)/libnds/nds/arm9/input.h: libnds/include/nds/arm9/input.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/input.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/input.h
+
+$(PROJECT_INCLUDE)/libnds/nds/arm9/math.h: libnds/include/nds/arm9/math.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/math.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/math.h
+
+$(PROJECT_INCLUDE)/libnds/nds/arm9/console.h: libnds/include/nds/arm9/console.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/console.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/console.h
+
+$(PROJECT_INCLUDE)/libnds/nds/arm9/sprite.h: libnds/include/nds/arm9/sprite.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/sprite.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/sprite.h
+
+$(PROJECT_INCLUDE)/libnds/nds/arm9/videoGL.h: libnds/include/nds/arm9/videoGL.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/videoGL.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/videoGL.h
+
+$(PROJECT_INCLUDE)/libnds/nds/arm9/cache.h: libnds/include/nds/arm9/cache.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/cache.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/cache.h
+
+$(PROJECT_INCLUDE)/libnds/nds/arm9/image.h: libnds/include/nds/arm9/image.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/image.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/image.h
+
+$(PROJECT_INCLUDE)/libnds/nds/arm9/trig_lut.h: libnds/include/nds/arm9/trig_lut.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/trig_lut.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/trig_lut.h
+
+$(PROJECT_INCLUDE)/libnds/nds/arm9/video.h: libnds/include/nds/arm9/video.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/video.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/video.h
+
+$(PROJECT_INCLUDE)/libnds/nds/arm9/exceptions.h: libnds/include/nds/arm9/exceptions.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/exceptions.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/exceptions.h
+
+$(PROJECT_INCLUDE)/libnds/nds/arm9/rumble.h: libnds/include/nds/arm9/rumble.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/rumble.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/rumble.h
+
+$(PROJECT_INCLUDE)/libnds/nds/arm9/background.h: libnds/include/nds/arm9/background.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/background.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/background.h
+
+$(PROJECT_INCLUDE)/libnds/nds/arm9/boxtest.h: libnds/include/nds/arm9/boxtest.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/boxtest.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/boxtest.h
+
+$(PROJECT_INCLUDE)/libnds/nds/arm9/postest.h: libnds/include/nds/arm9/postest.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/postest.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/postest.h
+
+$(PROJECT_INCLUDE)/libnds/nds/arm9/sound.h: libnds/include/nds/arm9/sound.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/sound.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/sound.h
+
+$(PROJECT_INCLUDE)/libnds/nds/arm7/$(dirstamp):
+	@$(MKDIR_P) $(PROJECT_INCLUDE)/libnds/nds/arm7
+	@: > $(PROJECT_INCLUDE)/libnds/nds/arm7/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libnds/nds/arm7/$(dirstamp)
+
+$(PROJECT_INCLUDE)/libnds/nds/arm7/serial.h: libnds/include/nds/arm7/serial.h $(PROJECT_INCLUDE)/libnds/nds/arm7/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm7/serial.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm7/serial.h
+
+$(PROJECT_INCLUDE)/libnds/nds/arm7/audio.h: libnds/include/nds/arm7/audio.h $(PROJECT_INCLUDE)/libnds/nds/arm7/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm7/audio.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm7/audio.h
+
+$(PROJECT_INCLUDE)/libnds/nds/arm7/clock.h: libnds/include/nds/arm7/clock.h $(PROJECT_INCLUDE)/libnds/nds/arm7/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm7/clock.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm7/clock.h
+
+$(PROJECT_INCLUDE)/libnds/nds/arm7/touch.h: libnds/include/nds/arm7/touch.h $(PROJECT_INCLUDE)/libnds/nds/arm7/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm7/touch.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm7/touch.h
+
+$(PROJECT_LIB)/coproc.bin: coproc.bin $(PROJECT_LIB)/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_LIB)/coproc.bin
+TMPINSTALL_FILES += $(PROJECT_LIB)/coproc.bin
+
Index: c/src/lib/libbsp/bfin/eZKit533/preinstall.am
===================================================================
--- c/src/lib/libbsp/bfin/eZKit533/preinstall.am	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ c/src/lib/libbsp/bfin/eZKit533/preinstall.am	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -37,8 +37,4 @@
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h
 
-$(PROJECT_INCLUDE)/cplb.h: include/cplb.h $(PROJECT_INCLUDE)/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/cplb.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/cplb.h
-
 $(PROJECT_INCLUDE)/tm27.h: include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h
Index: c/src/lib/libbsp/powerpc/gen83xx/ChangeLog
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/ChangeLog	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ c/src/lib/libbsp/powerpc/gen83xx/ChangeLog	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -1,2 +1,35 @@
+2008-05-15	Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
+
+	* network/network.c, start/start.S:
+	add support for different board
+
+2008-05-15	Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
+
+	* irq/ipic.c:
+	make sure, that the masking operations in 
+	ICTL and MSR are executed in order
+
+2008-05-15	Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
+
+	* include/bsp.h, startup/bspstart.c, 
+	* console/console.c, console/config.c:
+	derived module input frequencies from internal bus clock during
+	start time
+
+2008-05-15	Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
+
+	* spi/spi_init.c:
+	added base frequency into softc structure, added fm25l256 driver
+
+2008-05-15	Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
+
+	* i2c/i2c_init.c:
+	added base frequency into softc structure
+
+2008-05-15	Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
+
+	* include/bsp.h, include/hwreg_vals.h, ./Makefile.am: 
+	moved HW register settings from bsp.h to hwreg_vals.h
+
 2008-05-14	Joel Sherrill <joel.sherrill@OARcorp.com>
 
Index: c/src/lib/libbsp/powerpc/gen83xx/Makefile.am
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/Makefile.am	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ c/src/lib/libbsp/powerpc/gen83xx/Makefile.am	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -46,5 +46,7 @@
 
 include_bsp_HEADERS = ./irq/irq.h \
+    ./include/hwreg_vals.h        \
     ../../powerpc/shared/vectors/vectors.h
+
 vectors_SOURCES = ../../powerpc/shared/vectors/vectors.h \
     ../../powerpc/shared/vectors/vectors_init.c \
Index: c/src/lib/libbsp/powerpc/gen83xx/console/config.c
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/console/config.c	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ c/src/lib/libbsp/powerpc/gen83xx/console/config.c	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -106,8 +106,9 @@
 		NULL,				/* getData */
 		NULL,				/* setData */
-		BSP_CSB_CLK_FRQ,		/* ulClock */
+		0,		                /* ulClock (filled in init) */
                 0				/* ulIntVector */
-	},
-        {
+	}
+#if BSP_USE_UART2
+        ,{
                 "/dev/ttyS1",                   /* sDeviceName */
                 SERIAL_NS16550,                 /* deviceType */
@@ -125,7 +126,8 @@
                 NULL,                           /* getData */
                 NULL,                           /* setData */
-                BSP_CSB_CLK_FRQ,                /* ulClock */
+		0,		                /* ulClock (filled in init) */
                 0                               /* ulIntVector */
         }
+#endif
 };
 
Index: c/src/lib/libbsp/powerpc/gen83xx/console/console.c
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/console/console.c	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ c/src/lib/libbsp/powerpc/gen83xx/console/console.c	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -174,4 +174,9 @@
   {
     /*
+     * transfer the real internal bus frequency into the 
+     * console port table
+     */
+    Console_Port_Tbl[minor].ulClock = BSP_bus_frequency;
+    /*
      * First perform the configuration dependant probe, then the
      * device dependant probe
Index: c/src/lib/libbsp/powerpc/gen83xx/i2c/i2c_init.c
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/i2c/i2c_init.c	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ c/src/lib/libbsp/powerpc/gen83xx/i2c/i2c_init.c	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -32,5 +32,6 @@
       reg_ptr:	 &mpc83xx.i2c[0],
       initialized: FALSE,
-      irq_number:  BSP_IPIC_IRQ_I2C1
+      irq_number :  BSP_IPIC_IRQ_I2C1,
+      base_frq   : 0 /* will be set during initiailization */
     }
   },
@@ -44,5 +45,6 @@
       reg_ptr:	 &mpc83xx.i2c[1],
       initialized: FALSE,
-      irq_number:  BSP_IPIC_IRQ_I2C2
+      irq_number :  BSP_IPIC_IRQ_I2C2,
+      base_frq   : 0 /* will be set during initiailization */
     }
   } 
@@ -82,4 +84,17 @@
 
   /*
+   * update input frequency of I2c modules into descriptor
+   */
+  /*
+   * I2C1 is clocked with TSEC 1
+   */
+  if (((mpc83xx.clk.sccr >> (31-1)) & 0x03) > 0) {
+    mpc83xx_i2c_bus_tbl[0].softc.base_frq = 
+      (BSP_bus_frequency
+       /((mpc83xx.clk.sccr >> (31-1)) & 0x03));
+  }
+
+  mpc83xx_i2c_bus_tbl[1].softc.base_frq = BSP_bus_frequency;
+  /*
    * register first I2C bus
    */
@@ -99,4 +114,5 @@
   }
   i2c2_busno = ret_code;
+
   /*
    * register EEPROM to bus 1, Address 0x50
@@ -108,4 +124,5 @@
     return -ret_code;
   }
+
   /*
    * FIXME: register RTC driver, when available
Index: c/src/lib/libbsp/powerpc/gen83xx/include/bsp.h
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/include/bsp.h	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ c/src/lib/libbsp/powerpc/gen83xx/include/bsp.h	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -21,164 +21,5 @@
 #define __GEN83xx_BSP_h
 
-/*
- * distinguish board characteristics
- */
-/*
- * for Freescale MPC8349 EAMDS
- */
-#if defined(MPC8349EAMDS)
-/*
- * two DUART channels supported
- */
-#define GEN83xx_DUART_AVAIL_MASK 0x03
-
-/* we need the low level initialization in start.S*/
-#define NEED_LOW_LEVEL_INIT
-/*
- * clocking infos
- */
-#define BSP_CLKIN_FRQ 66000000L
-#define BSP_SYSPLL_MF 4 /* FIXME: derive from clock register */
-
-/*
- * Reset configuration words
- */
-#define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 |	\
-			  RCWLR_DDRCM_1_1  |	\
-			  RCWLR_SPMF(4)    |	\
-			  RCWLR_COREPLL(4))
-
-#define RESET_CONF_WRD_H (RCWHR_PCI_HOST     |	\
-			  RCWHR_PCI_32       |	\
-			  RCWHR_PCI1ARB_EN   |	\
-			  RCWHR_PCI2ARB_EN   |	\
-			  RCWHR_CORE_EN      |	\
-			  RCWHR_BMS_LOW      |	\
-			  RCWHR_BOOTSEQ_NONE |	\
-			  RCWHR_SW_DIS       |	\
-			  RCWHR_ROMLOC_LB16  |	\
-			  RCWHR_TSEC1M_GMII  |	\
-			  RCWHR_TSEC2M_GMII  |	\
-			  RCWHR_ENDIAN_BIG   |	\
-			  RCWHR_LALE_NORM    |	\
-			  RCWHR_LDP_PAR)
-/*
- * for JPK HSC_CM01
- */
-#elif defined(HSC_CM01)
-/*
- * one DUART channel (UART1) supported
- */
-#define GEN83xx_DUART_AVAIL_MASK 0x01
-
-/* we need the low level initialization in start.S*/
-#define NEED_LOW_LEVEL_INIT
-/*
- * clocking infos
- */
-#define BSP_CLKIN_FRQ 66000000L
-#define BSP_SYSPLL_MF 4 /* FIXME: derive from clock register */
-
-/*
- * Reset configuration words
- */
-#define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 |	\
-			  RCWLR_DDRCM_1_1  |	\
-			  RCWLR_SPMF(4)    |	\
-			  RCWLR_COREPLL(4))
-
-#define RESET_CONF_WRD_H (RCWHR_PCI_HOST     |	\
-			  RCWHR_PCI_32       |	\
-			  RCWHR_PCI1ARB_EN   |	\
-			  RCWHR_PCI2ARB_EN   |	\
-			  RCWHR_CORE_EN      |	\
-			  RCWHR_BMS_LOW      |	\
-			  RCWHR_BOOTSEQ_NONE |	\
-			  RCWHR_SW_DIS       |	\
-			  RCWHR_ROMLOC_LB16  |	\
-			  RCWHR_TSEC1M_RGMII |	\
-			  RCWHR_TSEC2M_GMII  |	\
-			  RCWHR_ENDIAN_BIG   |	\
-			  RCWHR_LALE_NORM    |	\
-			  RCWHR_LDP_PAR)
-#else
-#error "board type not defined"
-#endif
-
-/*
- * for JPK HSC_CM01 and freescale MPC8349EAMDS
- */
-#if defined(MPC8349EAMDS) || defined(HSC_CM01)
-/*
- * address range definitions
- */
-/* ROM definitions (8 MB, mirrored multiple times) */
-#define	ROM_START	0xFE000000
-#define ROM_SIZE        0x02000000
-#define	ROM_END		(ROM_START+ROM_SIZE-1)
-#define	BOOT_START      ROM_START
-#define	BOOT_END        ROM_END
-
-/* SDRAM definitions (256 MB) */
-#define	RAM_START       0x00000000
-#define RAM_SIZE        0x10000000
-#define	RAM_END		(RAM_START+RAM_SIZE-1)
-
-
-/* working internal memory map base address */
-#define	IMMRBAR         0xE0000000
-
-/*
- * working values for various registers, used in start/start.S
- */
-/*
- * Local Access Windows
- * FIXME: decode bit settings 
- */
-#define LBLAWBAR0_VAL  0xFE000000
-#define LBLAWAR0_VAL   0x80000016
-#define LBLAWBAR1_VAL  0xF8000000
-#define LBLAWAR1_VAL   0x8000000E
-#define LBLAWBAR2_VAL  0xF0000000
-#define LBLAWAR2_VAL   0x80000019
-#define DDRLAWBAR0_VAL 0x00000000
-#define DDRLAWAR0_VAL  0x8000001B
-/*
- * Local Bus (Memory) Controller
- * FIXME: decode bit settings 
- */
-#define BR0_VAL 0xFE001001
-#define OR0_VAL 0xFF806FF7
-#define BR1_VAL 0xF8000801
-#define OR1_VAL 0xFFFFE8F0
-#define BR2_VAL 0xF0001861
-#define OR2_VAL 0xFC006901
-/*
- * SDRAM registers
- * FIXME: decode bit settings 
- */
-#define MRPTR_VAL 0x20000000
-#define LSRT_VAL  0x32000000
-#define LSDMR_VAL 0x4062D733
-#define LCRR_VAL  0x80000004
-
-/*
- * DDR-SDRAM registers
- * FIXME: decode bit settings 
- */
-#define CS2_BNDS_VAL                 0x00000007
-#define CS3_BNDS_VAL                 0x0008000F
-#define CS2_CONFIG_VAL               0x80000101
-#define CS3_CONFIG_VAL               0x80000101
-#define TIMING_CFG_1_VAL             0x36333321
-#define TIMING_CFG_2_VAL             0x00000800
-#define DDR_SDRAM_CFG_VAL            0xC2000000
-#define DDR_SDRAM_MODE_VAL           0x00000022
-#define DDR_SDRAM_INTTVL_VAL         0x045B0100
-#define DDR_SDRAM_CLK_CNTL_VAL       0x00000000
-
-#else
-#error "board type not defined"
-#endif
+#include <bsp/hwreg_vals.h>
 
 #ifndef ASM
@@ -247,4 +88,10 @@
 #define PRINTK_MINOR BSP_UART1_MINOR
 
+#if defined(MPC8249EAMDS)
+#define BSP_USE_UART2 TRUE
+#else
+#define BSP_USE_UART2 FALSE
+#endif
+
 #define SINGLE_CHAR_MODE
 #define UARTS_USE_TERMIOS_INT   1
@@ -261,7 +108,8 @@
  *   (int) ((float)(_value) / ((XLB_CLOCK/1000000 * 0.1) / 4.0))
  */
-#define BSP_CSB_CLK_FRQ (BSP_CLKIN_FRQ * BSP_SYSPLL_MF)
+
+extern unsigned int BSP_bus_frequency;
 #define BSP_Convert_decrementer( _value ) \
-  (int) (((_value) * 4000) / (BSP_CSB_CLK_FRQ/10000))
+  (int) (((_value) * 4000) / (BSP_bus_frequency/10000))
 
 /*
@@ -275,4 +123,5 @@
 #define RTEMS_BSP_NETWORK_DRIVER_NAME2	"tsec2"
 
+#if defined(MPC8349EAMDS)
 /*
  * i2c EEPROM device name
@@ -286,4 +135,19 @@
 #define RTEMS_BSP_SPI_FLASH_DEVICE_NAME "flash"
 #define RTEMS_BSP_SPI_FLASH_DEVICE_PATH "/dev/spi.flash"
+#endif /* defined(MPC8349EAMDS) */
+
+#if defined(HSC_CM01)
+/*
+ * i2c EEPROM device name
+ */
+#define RTEMS_BSP_I2C_EEPROM_DEVICE_NAME "eeprom"
+#define RTEMS_BSP_I2C_EEPROM_DEVICE_PATH "/dev/i2c1.eeprom"
+
+/*
+ * SPI FRAM device name
+ */
+#define RTEMS_BSP_SPI_FRAM_DEVICE_NAME "fram"
+#define RTEMS_BSP_SPI_FRAM_DEVICE_PATH "/dev/spi.fram"
+#endif /* defined(HSC_CM01) */
 
 #ifdef __cplusplus
Index: c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
+++ c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -0,0 +1,268 @@
+/*===============================================================*\
+| Project: RTEMS generic MPC83xx BSP                              |
++-----------------------------------------------------------------+
+|                    Copyright (c) 2007                           |
+|                    Embedded Brains GmbH                         |
+|                    Obere Lagerstr. 30                           |
+|                    D-82178 Puchheim                             |
+|                    Germany                                      |
+|                    rtems@embedded-brains.de                     |
++-----------------------------------------------------------------+
+| The license and distribution terms for this file may be         |
+| found in the file LICENSE in this distribution or at            |
+|                                                                 |
+| http://www.rtems.com/license/LICENSE.                           |
+|                                                                 |
++-----------------------------------------------------------------+
+| this file contains board specific definitions                   |
+\*===============================================================*/
+
+#ifndef __GEN83xx_HWREG_VALS_h
+#define __GEN83xx_HWREG_VALS_h
+
+#include <mpc83xx/mpc83xx.h>
+/*
+ * distinguish board characteristics
+ */
+#if defined(MPC8349EAMDS)
+/*
+ * for Freescale MPC8349 EAMDS
+ */
+/*
+ * two DUART channels supported
+ */
+#define GEN83xx_DUART_AVAIL_MASK 0x03
+
+/* we need the low level initialization in start.S*/
+#define NEED_LOW_LEVEL_INIT
+/*
+ * clocking infos
+ */
+#define BSP_CLKIN_FRQ 66000000L
+#define RCFG_SYSPLL_MF 4 
+#define RCFG_COREPLL_MF 4
+
+/*
+ * Reset configuration words
+ */
+#define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 |	\
+			  RCWLR_DDRCM_1_1  |	\
+			  RCWLR_SPMF(RCFG_SYSPLL_MF)    |	\
+			  RCWLR_COREPLL(RCFG_COREPLL_MF))
+
+#define RESET_CONF_WRD_H (RCWHR_PCI_HOST     |	\
+			  RCWHR_PCI_32       |	\
+			  RCWHR_PCI1ARB_EN   |	\
+			  RCWHR_PCI2ARB_EN   |	\
+			  RCWHR_CORE_EN      |	\
+			  RCWHR_BMS_LOW      |	\
+			  RCWHR_BOOTSEQ_NONE |	\
+			  RCWHR_SW_DIS       |	\
+			  RCWHR_ROMLOC_LB16  |	\
+			  RCWHR_TSEC1M_GMII  |	\
+			  RCWHR_TSEC2M_GMII  |	\
+			  RCWHR_ENDIAN_BIG   |	\
+			  RCWHR_LALE_NORM    |	\
+			  RCWHR_LDP_PAR)
+#elif defined(HSC_CM01)
+/*
+ * for JPK HSC_CM01
+ */
+/*
+ * one DUART channel (UART1) supported
+ */
+#define GEN83xx_DUART_AVAIL_MASK 0x01
+
+/* we need the low level initialization in start.S*/
+#define NEED_LOW_LEVEL_INIT
+/*
+ * clocking infos
+ */
+#define BSP_CLKIN_FRQ 30000000L
+#define RCFG_SYSPLL_MF 11 
+#define RCFG_COREPLL_MF 4
+/*
+ * Reset configuration words
+ */
+#define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 |	\
+			  RCWLR_DDRCM_1_1  |	\
+			  RCWLR_SPMF(RCFG_SYSPLL_MF)    |	\
+			  RCWLR_COREPLL(RCFG_COREPLL_MF))
+
+#define RESET_CONF_WRD_H (RCWHR_PCI_HOST     |	\
+			  RCWHR_PCI_32       |	\
+			  RCWHR_PCI1ARB_EN   |	\
+			  RCWHR_PCI2ARB_EN   |	\
+			  RCWHR_CORE_EN      |	\
+			  RCWHR_BMS_LOW      |	\
+			  RCWHR_BOOTSEQ_NONE |	\
+			  RCWHR_SW_DIS       |	\
+			  RCWHR_ROMLOC_LB16  |	\
+			  RCWHR_TSEC1M_RGMII |	\
+			  RCWHR_TSEC2M_GMII  |	\
+			  RCWHR_ENDIAN_BIG   |	\
+			  RCWHR_LALE_NORM    |	\
+			  RCWHR_LDP_PAR)
+#else
+#error "board type not defined"
+#endif
+
+#if defined(MPC8349EAMDS) 
+/**************************
+ * for Freescale MPC8349EAMDS
+ */
+/*
+ * address range definitions
+ */
+/* ROM definitions (8 MB, mirrored multiple times) */
+#define	ROM_START	0xFE000000
+#define ROM_SIZE        0x02000000
+#define	ROM_END		(ROM_START+ROM_SIZE-1)
+#define	BOOT_START      ROM_START
+#define	BOOT_END        ROM_END
+
+/* SDRAM definitions (256 MB) */
+#define	RAM_START       0x00000000
+#define RAM_SIZE        0x10000000
+#define	RAM_END		(RAM_START+RAM_SIZE-1)
+
+
+/* working internal memory map base address */
+#define	IMMRBAR         0xE0000000
+
+/*
+ * working values for various registers, used in start/start.S
+ */
+/*
+ * Local Access Windows
+ * FIXME: decode bit settings 
+ */
+#define LBLAWBAR0_VAL  0xFE000000
+#define LBLAWAR0_VAL   0x80000016
+#define LBLAWBAR1_VAL  0xF8000000
+#define LBLAWAR1_VAL   0x8000000E
+#define LBLAWBAR2_VAL  0xF0000000
+#define LBLAWAR2_VAL   0x80000019
+#define DDRLAWBAR0_VAL 0x00000000
+#define DDRLAWAR0_VAL  0x8000001B
+/*
+ * Local Bus (Memory) Controller
+ * FIXME: decode bit settings 
+ */
+#define BR0_VAL 0xFE001001
+#define OR0_VAL 0xFF806FF7
+#define BR1_VAL 0xF8000801
+#define OR1_VAL 0xFFFFE8F0
+#define BR2_VAL 0xF0001861
+#define OR2_VAL 0xFC006901
+/*
+ * SDRAM registers
+ * FIXME: decode bit settings 
+ */
+#define MRPTR_VAL 0x20000000
+#define LSRT_VAL  0x32000000
+#define LSDMR_VAL 0x4062D733
+#define LCRR_VAL  0x80000004
+
+/*
+ * DDR-SDRAM registers
+ * FIXME: decode bit settings 
+ */
+#define CS2_BNDS_VAL                 0x00000007
+#define CS3_BNDS_VAL                 0x0008000F
+#define CS2_CONFIG_VAL               0x80000101
+#define CS3_CONFIG_VAL               0x80000101
+#define TIMING_CFG_1_VAL             0x36333321
+#define TIMING_CFG_2_VAL             0x00000800
+#define DDR_SDRAM_CFG_VAL            0xC2000000
+#define DDR_SDRAM_MODE_VAL           0x00000022
+#define DDR_SDRAM_INTTVL_VAL         0x045B0100
+#define DDR_SDRAM_CLK_CNTL_VAL       0x00000000
+
+#elif defined(HSC_CM01)
+/**************************
+ * for JPK HSC_CM01
+ */
+/*
+ * address range definitions
+ */
+/* ROM definitions (8 MB, mirrored multiple times) */
+#define	ROM_START	0xFE000000
+#define ROM_SIZE        0x02000000
+#define	ROM_END		(ROM_START+ROM_SIZE-1)
+#define	BOOT_START      ROM_START
+#define	BOOT_END        ROM_END
+
+/* SDRAM definitions (256 MB) */
+#define	RAM_START       0x00000000
+#define RAM_SIZE        0x10000000
+#define	RAM_END		(RAM_START+RAM_SIZE-1)
+
+
+/* working internal memory map base address */
+#define	IMMRBAR         0xE0000000
+
+/*
+ * working values for various registers, used in start/start.S
+ */
+/*
+ * Local Access Windows
+ * FIXME: decode bit settings 
+ */
+
+#define LBLAWBAR0_VAL  ROM_START
+#define LBLAWAR0_VAL   0x80000018
+#define LBLAWBAR1_VAL  0xF8000000
+#define LBLAWAR1_VAL   0x80000015
+#define DDRLAWBAR0_VAL RAM_START
+#define DDRLAWAR0_VAL  0x8000001B
+/*
+ * Local Bus (Memory) Controller
+ * FIXME: decode bit settings 
+ */
+#define BR0_VAL 0xFE001001
+#define OR0_VAL 0xFE000E54
+#define BR3_VAL 0xF8001881
+#define OR3_VAL 0xFFC01100
+/*
+ * Local (memory) bus divider
+ * FIXME: decode bit settings 
+ */
+#define LCRR_VAL  0x00010004
+
+/*
+ * DDR-SDRAM registers
+ * FIXME: decode bit settings 
+ */
+#define DDRCDR_VAL                   0x00000001
+#define CS0_BNDS_VAL                 0x0000000F
+#define CS0_CONFIG_VAL               0x80810102
+#define TIMING_CFG_0_VAL             0x00420802
+#define TIMING_CFG_1_VAL             0x3735A322
+#define TIMING_CFG_2_VAL             0x2F9044C7
+#define DDR_SDRAM_CFG_2_VAL          0x00401000
+#define DDR_SDRAM_MODE_VAL           0x44521632
+#define DDR_SDRAM_CLK_CNTL_VAL       0x01800000
+#define DDR_SDRAM_CFG_VAL            0x43000008
+
+#define DDR_ERR_DISABLE_VAL          0x0000008D
+#define DDR_ERR_DISABLE_VAL2         0x00000089
+#define DDR_SDRAM_DATA_INIT_VAL      0xC01DCAFE
+#define DDR_SDRAM_INIT_ADDR_VAL      0
+#define DDR_SDRAM_INTERVAL_VAL       0x05080000
+#else
+#error "board type not defined"
+#endif
+
+
+/**************************
+ * derived values for all boards
+ */
+/* value of input clock divider (derived from pll mode reg) */
+#define BSP_SYSPLL_CKID (((mpc83xx.clk.spmr>>(31-8))&0x01)+1)
+/* value of system pll (derived from pll mode reg) */
+#define BSP_SYSPLL_MF    ((mpc83xx.clk.spmr>>(31-7))&0x0f) 
+/* value of system pll (derived from pll mode reg) */
+#define BSP_COREPLL_MF   ((mpc83xx.clk.spmr>>(31-15))&0x7f) 
+
+#endif /* __GEN83xx_HWREG_VALS_h */
Index: c/src/lib/libbsp/powerpc/gen83xx/irq/ipic.c
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/irq/ipic.c	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ c/src/lib/libbsp/powerpc/gen83xx/irq/ipic.c	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -273,4 +273,11 @@
     mpc83xx.ipic.semsr    &= mask_ptr->semsr_mask   ;
     mpc83xx.ipic.sermr    &= mask_ptr->sermr_mask   ;
+
+    /* 
+     * make sure, that the masking operations in 
+     * ICTL and MSR are executed in order
+     */
+    asm volatile("sync":::"memory");
+    
     /*
      * reenable msr_ee
@@ -294,4 +301,11 @@
      */
     _CPU_MSR_SET(msr_save);
+
+    /* 
+     * make sure, that the masking operations in 
+     * ICTL and MSR are executed in order
+     */
+    asm volatile("sync":::"memory");
+
     /*
      * restore initial masks
Index: c/src/lib/libbsp/powerpc/gen83xx/network/network.c
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/network/network.c	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ c/src/lib/libbsp/powerpc/gen83xx/network/network.c	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -27,8 +27,14 @@
 #include <stdio.h>
 
-#define TSEC_BITRATE 1000
 #define TSEC_IFMODE_RGMII 0
 #define TSEC_IFMODE_GMII  1
+
+#if defined(MPC8349EAMDS)
+#define TSEC_IFMODE TSEC_IFMODE_GMII
+#endif
+
+#if defined(HSC_CM01)
 #define TSEC_IFMODE TSEC_IFMODE_RGMII
+#endif
 
 /*=========================================================================*\
@@ -62,4 +68,5 @@
   }
   if (attaching) {
+#if (TSEC_IFMODE==TSEC_IFMODE_GMII)
     if (unitNumber == 1) {
       /*
@@ -74,11 +81,18 @@
 			       |                         0x0000001f);
     }
-  }
-  if (unitNumber == 2) {
+    if (unitNumber == 2) {
+      /*
+       * init port registers (GPIO2DIR) for TSEC2
+       */
+      mpc83xx.gpio[0].gpdir = ((mpc83xx.gpio[0].gpdir & ~0x000FFFFF)
+			       |                         0x00087881);
+    }
+#endif
+#if (TSEC_IFMODE==TSEC_IFMODE_RGMII)
+
     /*
-     * init port registers (GPIO2DIR) for TSEC2
+     * Nothing special needed for TSEC1 operation
      */
-    mpc83xx.gpio[0].gpdir = ((mpc83xx.gpio[0].gpdir & ~0x000FFFFF)
-			     |                         0x00087881);
+#endif    
   }
   /*
Index: c/src/lib/libbsp/powerpc/gen83xx/preinstall.am
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/preinstall.am	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ c/src/lib/libbsp/powerpc/gen83xx/preinstall.am	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -82,4 +82,8 @@
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
 
+$(PROJECT_INCLUDE)/bsp/hwreg_vals.h: ./include/hwreg_vals.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/hwreg_vals.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/hwreg_vals.h
+
 $(PROJECT_INCLUDE)/bsp/vectors.h: ../../powerpc/shared/vectors/vectors.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vectors.h
Index: c/src/lib/libbsp/powerpc/gen83xx/spi/spi_init.c
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/spi/spi_init.c	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ c/src/lib/libbsp/powerpc/gen83xx/spi/spi_init.c	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -22,6 +22,8 @@
 #include <bsp.h>
 #if defined(MPC8349EAMDS)
-#include <libchip/i2c-2b-eeprom.h>
 #include <libchip/spi-flash-m25p40.h>
+#endif
+#if defined(HSC_CM01)
+#include <libchip/spi-fram-fm25l256.h>
 #endif
 
@@ -190,5 +192,6 @@
     reg_ptr:	 &mpc83xx.spi,
     initialized: FALSE,
-    irq_number:  BSP_IPIC_IRQ_SPI
+    irq_number:  BSP_IPIC_IRQ_SPI,
+    base_frq  :  0 /* filled in during init */
   }
 };
@@ -248,4 +251,9 @@
   mpc83xx.gpio[0].gpdr  &= ~(0xf << (31-27));
 #endif
+  /*
+   * update base frequency in spi descriptor
+   */
+  bsp_spi_bus_desc.softc.base_frq = BSP_bus_frequency;
+
   /*
    * register SPI bus
@@ -257,8 +265,8 @@
   }
   spi_busno = ret_code;
-  /*
-   * register M25P40 Flash, when available
-   */
-#if defined(MPC8349EAMDS)
+#if defined(MPC8349EAMDS)
+  /*
+   * register M25P40 Flash
+   */
   ret_code = rtems_libi2c_register_drv(RTEMS_BSP_SPI_FLASH_DEVICE_NAME,
 				       spi_flash_m25p40_rw_driver_descriptor,
@@ -268,4 +276,15 @@
   }
 #endif
+#if defined(HSC_CM01)
+  /*
+   * register FM25L256 FRAM
+   */
+  ret_code = rtems_libi2c_register_drv(RTEMS_BSP_SPI_FRAM_DEVICE_NAME,
+				       spi_fram_fm25l256_rw_driver_descriptor,
+				       spi_busno,0x02);
+  if (ret_code < 0) {
+    return -ret_code;
+  }
+#endif
   /*
    * FIXME: further drivers, when available
Index: c/src/lib/libbsp/powerpc/gen83xx/start/start.S
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/start/start.S	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ c/src/lib/libbsp/powerpc/gen83xx/start/start.S	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -86,4 +86,5 @@
 .extern MBAR   
 
+#if defined(RESET_CONF_WRD_L)
 .section ".resconf","ax"
 PUBLIC_VAR (reset_conf_words)
@@ -98,4 +99,5 @@
 	REP8( .byte ((RESET_CONF_WRD_H >>  8) & 0xff))
 	REP8( .byte ((RESET_CONF_WRD_H >>  0) & 0xff))
+#endif
 
 .section ".vectors","ax"
@@ -146,5 +148,4 @@
 	*/
 	/*
-	 * FIXME:	 
 	 * we start from 0x100, so ROM is currently mapped to
 	 * 0x00000000..
@@ -224,4 +225,5 @@
 	SET_IMM_REGW r31,r30,OR3_OFF,OR3_VAL
 #endif
+	
 	/*
 	 * ROM startup: init SDRAM access window
@@ -240,6 +242,18 @@
 #endif
 	/*
+	 * ROM startup: init refresh interval
+	 */
+#ifdef MRPTR_VAL
+	SET_IMM_REGW r31,r30,MRPTR_OFF,MRPTR_VAL
+#endif	
+	/*
 	 * ROM startup: init SDRAM
 	 */
+#ifdef LSRT_VAL
+	SET_IMM_REGW r31,r30, LSRT_OFF, LSRT_VAL
+#endif
+#ifdef LSDMR_VAL
+	SET_IMM_REGW r31,r30, LSDMR_OFF, LSDMR_VAL
+#endif
 #ifdef CS0_BNDS_VAL
 	SET_IMM_REGW r31,r30,CS0_BNDS_OFF,CS0_BNDS_VAL
@@ -278,6 +292,6 @@
 	SET_IMM_REGW r31,r30,TIMING_CFG_2_OFF,TIMING_CFG_2_VAL
 #endif
-#ifdef DDR_SDRAM_CFG_VAL
-	SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_OFF,DDR_SDRAM_CFG_VAL
+#ifdef DDRCDR_VAL
+	SET_IMM_REGW r31,r30,DDRCDR_OFF,DDRCDR_VAL
 #endif
 #ifdef DDR_SDRAM_CFG_2_VAL
@@ -299,37 +313,121 @@
 	SET_IMM_REGW r31,r30,DDR_SDRAM_CLK_CNTL_OFF,DDR_SDRAM_CLK_CNTL_VAL
 #endif
+#ifdef DDR_SDRAM_CFG_2_VAL
+	SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_2_OFF,DDR_SDRAM_CFG_2_VAL|DDR_SDRAM_CFG_2_D_INIT
+#endif
+
+#ifdef DDR_ERR_DISABLE_VAL
+	/*
+	 * disable detect of RAM errors
+	 */
+	SET_IMM_REGW r31,r30,DDR_ERR_DISABLE_OFF,DDR_ERR_DISABLE_VAL
+#endif
+#ifdef DDR_SDRAM_DATA_INIT_VAL
+	/*
+	 * set this value to initialize memory
+	 */
+	SET_IMM_REGW r31,r30,DDR_SDRAM_DATA_INIT_OFF,DDR_SDRAM_DATA_INIT_VAL
+#endif
 #ifdef DDR_SDRAM_INIT_ADDR_VAL
 	SET_IMM_REGW r31,r30,DDR_SDRAM_INIT_ADDR_OFF,DDR_SDRAM_INIT_ADDR_VAL
 #endif
-	/*
-	 * FIXME: ROM startup: perform mode set commands etc for SDRAM
-	 */
-	/*
-	 * ROM startup: copy code to SDRAM
-	 */
-	LA	r30, _text_start  /* get start address of text section in RAM */
-	add	r30, r20, r30    /* get start address of text section in ROM (add reloc offset) */
-	LA	r29, _text_start /* get start address of text section in RAM */
-	LA	r28, _text_size  /* get size of RAM image */
-	bl	copy_image      /* copy text section from ROM to RAM location */
-	
-	/*
-	 * FIXME: ROM startup: copy data to SDRAM
-	 */
-	LA	r30, _data_start /* get start address of data section in RAM */
-	add	r30, r20, r30    /* get start address of data section in ROM (add reloc offset) */
-	LA	r29, _data_start /* get start address of data section in RAM */
-	LA	r28, _data_size  /* get size of RAM image */
-	bl	copy_image       /* copy initialized data section from ROM to RAM location */
+#ifdef DDR_SDRAM_CFG_VAL
+	/*
+	 * config DDR SDRAM
+	 */
+	SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_OFF,DDR_SDRAM_CFG_VAL & ~DDR_SDRAM_CFG_MEM_EN
+	/*
+	 * FIXME: wait 200us
+	 */
+	/*
+	 * enable  DDR SDRAM
+	 */
+	SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_OFF,DDR_SDRAM_CFG_VAL | DDR_SDRAM_CFG_MEM_EN
+	/*
+	 * wait, until DDR_SDRAM_CFG_2_D_INIT is cleared
+	 */
+1:	lwz r30,DDR_SDRAM_CFG_2_OFF(r31)
+	andi. r30,r30,DDR_SDRAM_CFG_2_D_INIT
+	bne 1b
+#endif
+#ifdef DDR_ERR_DISABLE_VAL2
+	/*
+	 * enable detect of some RAM errors
+	 */
+	SET_IMM_REGW r31,r30,DDR_ERR_DISABLE_OFF,DDR_ERR_DISABLE_VAL2
+#endif
+#ifdef DDR_SDRAM_INTERVAL_VAL
+	/*
+	 * set the refresh interval
+	 */
+	SET_IMM_REGW r31,r30,DDR_SDRAM_INTERVAL_OFF,DDR_SDRAM_INTERVAL_VAL
+#endif
+start_rom_skip:
+	/*
+	 * determine current execution address offset
+	 */
+	bl start_rom_skip1
+start_rom_skip1:
+	mflr r20
+	LA   r30,start_rom_skip1
+	sub. r20,r20,r30	
+	/*
+	 * execution address offset == 0?
+	 * then do not relocate code and data
+	 */
+	beq  start_code_in_ram
+	/*
+	 * ROM or relocatable startup: copy startup code to SDRAM
+	 */
+	/* get start address of text section in RAM */
+	LA	r29, _text_start  
+	/* get start address of text section in ROM (add reloc offset) */
+	add	r30, r20, r29    
+	/* get size of startup code */
+	LA	r28, end_reloc_startup
+	LA	r31, _text_start
+	sub	28,r28,r31
+	/* copy startup code from ROM to RAM location */
+	bl	copy_image      
+	
 	/*
 	 * ROM startup: jump to code copy in  SDRAM
 	 */
-	LA	r29, start_code_in_ram /* get compile time address of label */
+	/* get compile time address of label */
+	LA	r29, copy_rest_of_text 
 	mtlr	r29
 	blr                     /* now further execution RAM */
+copy_rest_of_text:	
+#ifdef LCRR_VAL
+	SET_IMM_REGW r31,r30,LCRR_OFF,LCRR_VAL
+#endif
+	/*
+	 * ROM or relocatable startup: copy rest of code to SDRAM
+	 */
+	/* get start address of rest of code in RAM */
+	LA	r29, end_reloc_startup
+	/* get start address of text section in ROM (add reloc offset) */
+	add	r30, r20, r29    
+	/* get size of rest of code */
+	LA	r28, _text_start
+	LA	r31, _text_size
+	add	r28,r28,r31
+	sub	r28,r28,r29
+	bl	copy_image      /* copy text section from ROM to RAM location */
+	
+	/*
+	 * ROM or relocatable startup: copy data to SDRAM
+	 */
+	/* get start address of data section in RAM */
+	LA	r29, _data_start 
+	/* get start address of data section in ROM (add reloc offset) */
+	add	r30, r20, r29    
+	/* get size of RAM image */
+	LA	r28, _data_size  
+	/* copy initialized data section from ROM to RAM location */
+	bl	copy_image       
 
 start_code_in_ram:	
 
-start_rom_skip:	
 	/*
 	 * ROM/RAM startup: clear bss in SDRAM
@@ -418,2 +516,3 @@
 clr_mem_end:
         blr					/* return */
+end_reloc_startup:
Index: c/src/lib/libbsp/powerpc/gen83xx/startup/bspstart.c
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/startup/bspstart.c	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ c/src/lib/libbsp/powerpc/gen83xx/startup/bspstart.c	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -49,5 +49,5 @@
  * BSP_time_base_divisor = TB ticks per millisecond/BSP_bus_frequency
  */
-unsigned int BSP_bus_frequency = BSP_CSB_CLK_FRQ;
+unsigned int BSP_bus_frequency;
 unsigned int BSP_time_base_divisor = 4000;  /* 4 bus clicks per TB click */
 
@@ -189,7 +189,12 @@
 
   /*
+   * this is evaluated during runtime, so it should be ok to set it 
+   * before we initialize the drivers
+   */
+  BSP_bus_frequency   = BSP_CLKIN_FRQ * BSP_SYSPLL_MF / BSP_SYSPLL_CKID;
+  /*
    *  initialize the device driver parameters
    */
-  bsp_clicks_per_usec        = (BSP_CSB_CLK_FRQ/1000000);
+  bsp_clicks_per_usec = (BSP_bus_frequency/1000000);
 
   /*
Index: c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -44,5 +44,8 @@
     { 
     IMMRBAR = .;
-    *mpc83xx_regs*(*)
+    mpc83xx_regs*(.text)
+    mpc83xx_regs*(.data)
+    mpc83xx_regs*(.bss)
+    mpc83xx_regs*(*COM*)
     } > mpc83xx_regs
 
Index: c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.hsc_cm01
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.hsc_cm01	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.hsc_cm01	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -38,8 +38,11 @@
 {
 
-    mpc83xx_regs (NOLOAD) :
+    .mpc83xx_regs (NOLOAD) :
     { 
     IMMRBAR = .;
-    *mpc83xx_regs*(*)
+    mpc83xx_regs*(.text)
+    mpc83xx_regs*(.data)
+    mpc83xx_regs*(.bss)
+    mpc83xx_regs*(*COM*)
     } > mpc83xx_regs
 
Index: c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.mpc8349eamds
===================================================================
--- c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.mpc8349eamds	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.mpc8349eamds	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -41,5 +41,8 @@
     { 
     IMMRBAR = .;
-    *mpc83xx_regs*(*)
+    mpc83xx_regs*(.text)
+    mpc83xx_regs*(.data)
+    mpc83xx_regs*(.bss)
+    mpc83xx_regs*(*COM*)
     } > mpc83xx_regs
 
Index: c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog
===================================================================
--- c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -1,2 +1,8 @@
+2008-05-15	Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
+
+	* irq/irq.c:
+	make sure, that the masking operations in 
+	ICTL and MSR are executed in order
+
 2008-05-14	Joel Sherrill <joel.sherrill@OARcorp.com>
 
Index: c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.c
===================================================================
--- c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.c	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.c	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -473,4 +473,10 @@
       ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = ppc_cached_irq_mask;
     }
+    /* 
+     * make sure, that the masking operations in 
+     * ICTL and MSR are executed in order
+     */
+    asm volatile("sync":::"memory");
+
     _CPU_MSR_GET(msr);
     new_msr = msr | MSR_EE;
@@ -480,4 +486,10 @@
 
     _CPU_MSR_SET(msr);
+
+    /* 
+     * make sure, that the masking operations in 
+     * ICTL and MSR are executed in order
+     */
+    asm volatile("sync":::"memory");
 
     if (cpmIntr)  {
Index: c/src/lib/libbsp/powerpc/mpc8260ads/ChangeLog
===================================================================
--- c/src/lib/libbsp/powerpc/mpc8260ads/ChangeLog	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ c/src/lib/libbsp/powerpc/mpc8260ads/ChangeLog	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -1,2 +1,8 @@
+2008-05-15	Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
+
+	* irq/irq.c:
+	make sure, that the masking operations in 
+	ICTL and MSR are executed in order
+
 2008-05-14	Joel Sherrill <joel.sherrill@OARcorp.com>
 
Index: c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.c
===================================================================
--- c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.c	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.c	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -484,4 +484,10 @@
 			m8260.sipnr_l |= SIU_MaskBit[irq].mask_l;
 
+			/* 
+			 * make sure, that the masking operations in 
+			 * ICTL and MSR are executed in order
+			 */
+			asm volatile("sync":::"memory");
+
 			/* re-enable external exceptions */
 			_CPU_MSR_GET(msr);
@@ -495,4 +501,10 @@
 			_CPU_MSR_SET(msr);
 
+			/* 
+			 * make sure, that the masking operations in 
+			 * ICTL and MSR are executed in order
+			 */
+			asm volatile("sync":::"memory");
+
 			/* restore interrupt masks */
 			m8260.simr_h = old_simr_h;
Index: c/src/lib/libbsp/powerpc/mvme3100/preinstall.am
===================================================================
--- c/src/lib/libbsp/powerpc/mvme3100/preinstall.am	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ c/src/lib/libbsp/powerpc/mvme3100/preinstall.am	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -138,6 +138,7 @@
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vpd.h
 
+if HAS_NETWORKING
 $(PROJECT_INCLUDE)/bsp/if_tsec_pub.h: network/if_tsec_pub.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/if_tsec_pub.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/if_tsec_pub.h
-
+endif
Index: c/src/lib/libbsp/powerpc/mvme5500/preinstall.am
===================================================================
--- c/src/lib/libbsp/powerpc/mvme5500/preinstall.am	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ c/src/lib/libbsp/powerpc/mvme5500/preinstall.am	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -114,21 +114,4 @@
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/VPD.h
 
-if HAS_NETWORKING
-$(PROJECT_INCLUDE)/bsp/GT64260eth.h: network/if_100MHz/GT64260eth.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/GT64260eth.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/GT64260eth.h
-
-$(PROJECT_INCLUDE)/bsp/GT64260ethreg.h: network/if_100MHz/GT64260ethreg.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/GT64260ethreg.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/GT64260ethreg.h
-
-$(PROJECT_INCLUDE)/bsp/if_wmreg.h: network/if_1GHz/if_wmreg.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/if_wmreg.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/if_wmreg.h
-
-$(PROJECT_INCLUDE)/bsp/pcireg.h: network/if_1GHz/pcireg.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/pcireg.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/pcireg.h
-endif
 $(PROJECT_INCLUDE)/bsp/VME.h: ../../shared/vmeUniverse/VME.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/VME.h
@@ -159,4 +142,21 @@
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vme_am_defs.h
 
+if HAS_NETWORKING
+$(PROJECT_INCLUDE)/bsp/GT64260eth.h: network/if_100MHz/GT64260eth.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/GT64260eth.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/GT64260eth.h
+
+$(PROJECT_INCLUDE)/bsp/GT64260ethreg.h: network/if_100MHz/GT64260ethreg.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/GT64260ethreg.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/GT64260ethreg.h
+
+$(PROJECT_INCLUDE)/bsp/if_wmreg.h: network/if_1GHz/if_wmreg.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/if_wmreg.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/if_wmreg.h
+
+$(PROJECT_INCLUDE)/bsp/pcireg.h: network/if_1GHz/pcireg.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/pcireg.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/pcireg.h
+endif
 $(PROJECT_LIB)/rtems_crti.$(OBJEXT): rtems_crti.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_LIB)/rtems_crti.$(OBJEXT)
Index: c/src/lib/libcpu/powerpc/ChangeLog
===================================================================
--- c/src/lib/libcpu/powerpc/ChangeLog	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ c/src/lib/libcpu/powerpc/ChangeLog	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -1,2 +1,13 @@
+2008-05-15	Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
+
+	* mpc83xx/network/tsec.c, mpc83xx/include/mpc83xx.h:
+	added support for RGMII interface and different board
+
+2008-05-15	Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
+
+	* mpc83xx/i2c/mpc83xx_i2cdrv.c, mpc83xx/i2c/mpc83xx_i2cdrv.h,
+	* mpc83xx/spi/mpc83xx_spidrv.c, mpc83xx/spi/mpc83xx_spidrv.h:
+	added base frequency into softc structure
+
 2008-05-14	Till Straumann <strauman@slac.stanford.edu>
 
Index: c/src/lib/libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.c
===================================================================
--- c/src/lib/libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.c	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ c/src/lib/libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.c	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -32,5 +32,5 @@
 | Function:                                                                 |
 \*-------------------------------------------------------------------------*/
-static int mpc83xx_i2c_find_clock_divider
+static rtems_status_code mpc83xx_i2c_find_clock_divider
 (
 /*-------------------------------------------------------------------------*\
@@ -50,4 +50,5 @@
   int i;
   int fdr_val;
+  rtems_status_code sc = RTEMS_SUCCESSFUL;
   struct {
     int divider;
@@ -69,13 +70,21 @@
   };
 
-  for (i = 0, fdr_val = -1; i < sizeof(dividers)/sizeof(dividers[0]); i++) {
-    fdr_val = dividers[i].fdr_val;
-    if (dividers[i].divider >= divider)
-      {
-	break;
-      }
-  }
-  *result = fdr_val;
-  return 0;
+  if (divider <= 0) {
+    sc = RTEMS_INVALID_NUMBER;
+  }
+
+  if (sc == RTEMS_SUCCESSFUL) {
+    sc = RTEMS_INVALID_NUMBER;
+    for (i = 0, fdr_val = -1; i < sizeof(dividers)/sizeof(dividers[0]); i++) {
+      fdr_val = dividers[i].fdr_val;
+      if (dividers[i].divider >= divider)
+	{
+	  sc = RTEMS_SUCCESSFUL;
+	  *result = fdr_val;
+	  break;
+	}
+    }
+  }
+  return sc;
 }
 
@@ -314,5 +323,5 @@
    */
   errval = mpc83xx_i2c_find_clock_divider(&fdr_val,
-					  BSP_CSB_CLK_FRQ/3/100000);
+					  softc_ptr->base_frq/100000);
   if (errval != 0) {
     return errval;
@@ -472,7 +481,4 @@
     }
   }
-  addr_byte = (0xf0 
-	       | ((addr >> 7) & 0x06)
-	       | ((rw) ? 1 : 0));
   /*
    * send (final) byte 
@@ -525,4 +531,8 @@
   softc_ptr->reg_ptr->i2ccr &= ~MPC83XX_I2CCR_MTX;
   softc_ptr->reg_ptr->i2ccr &= ~MPC83XX_I2CCR_TXAK;
+  /*
+   * FIXME: do we need to deactivate TXAK from the start, 
+   * when only one byte is to be received?
+   */
   /*
    * we need a dummy transfer here to start the first read
Index: c/src/lib/libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.h
===================================================================
--- c/src/lib/libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.h	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ c/src/lib/libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.h	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -29,8 +29,9 @@
 
 typedef struct mpc83xx_i2c_softc {
-  m83xxI2CRegisters_t *reg_ptr;
-  int                  initialized;
-  rtems_irq_number     irq_number;
-  rtems_id             irq_sema_id;
+  m83xxI2CRegisters_t *reg_ptr;     /* ptr to HW registers             */
+  int                  initialized; /* TRUE: module is initialized     */
+  rtems_irq_number     irq_number;  /* IRQ number used for this module */
+  uint32_t             base_frq;    /* input frq for baud rate divider */
+  rtems_id             irq_sema_id; /* SEMA used for IRQ signalling    */
 } mpc83xx_i2c_softc_t ;
 
Index: c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h
===================================================================
--- c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -1111,4 +1111,10 @@
 #define OR7_OFF  0x0503C
 
+#define MRPTR_OFF                    0x05084
+#define LSDMR_OFF                    0x05094
+#define LSRT_OFF                     0x050A4
+#define LCRR_OFF                     0x050d4
+
+
 #define CS0_BNDS_OFF       0x02000
 #define CS1_BNDS_OFF       0x02008
@@ -1128,7 +1134,23 @@
 #define DDR_SDRAM_MODE_2_OFF         0x0211C
 #define DDR_SDRAM_MD_CNTL_OFF        0x02120
-#define DDR_SDRAM_MD_ITVL_OFF        0x02124
+#define DDR_SDRAM_INTERVAL_OFF       0x02124
+#define DDR_SDRAM_DATA_INIT_OFF      0x02128
+#define DDRCDR_OFF                   0x0012C
 #define DDR_SDRAM_CLK_CNTL_OFF       0x02130
 #define DDR_SDRAM_INIT_ADDR_OFF      0x02148
+#define DDR_ERR_DISABLE_OFF          0x02E44
+
+/*
+ * some bits in DDR_SDRAM_CFG register
+ */
+#define DDR_SDRAM_CFG_MEM_EN (1 << (31- 0))     /* enable memory        */
+/*
+ * bits in DDR_SDRAM_CFG_2 register
+ */
+#define DDR_SDRAM_CFG_2_D_FRC_SR (1 << (31- 0)) /* force self refresh        */
+#define DDR_SDRAM_CFG_2_D_SR_IE  (1 << (31- 1)) /* self refresh interrupt en */
+#define DDR_SDRAM_CFG_2_D_DLL_RST_DIS  (1 << (31- 2)) /* DLL reset disable   */
+#define DDR_SDRAM_CFG_2_D_DQS_CFG_DIF  (1 << (31- 5)) /* use diff. DQS       */
+#define DDR_SDRAM_CFG_2_D_INIT   (1 << (31-27)) /* Init DRAM with pattern    */
 
 /*
Index: c/src/lib/libcpu/powerpc/mpc83xx/network/tsec.c
===================================================================
--- c/src/lib/libcpu/powerpc/mpc83xx/network/tsec.c	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ c/src/lib/libcpu/powerpc/mpc83xx/network/tsec.c	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -116,5 +116,5 @@
 #define M83xx_IEVENT_TXALL (M83xx_TSEC_IEVENT_GTSC	\
 			    | M83xx_TSEC_IEVENT_TXC 	\
-			    | M83xx_TSEC_IEVENT_TXB 	\
+			    /*| M83xx_TSEC_IEVENT_TXB*/	\
 			    | M83xx_TSEC_IEVENT_TXF )
 
@@ -123,5 +123,5 @@
  */
 #define M83xx_IEVENT_RXALL (M83xx_TSEC_IEVENT_RXC  	\
-			    | M83xx_TSEC_IEVENT_RXB  	\
+			    /* | M83xx_TSEC_IEVENT_RXB */	\
 			    | M83xx_TSEC_IEVENT_GRSC 	\
 			    | M83xx_TSEC_IEVENT_RXF  )
@@ -252,12 +252,12 @@
    */
   reg_ptr->txic = (M83xx_TSEC_TXIC_ICEN
-		   | M83xx_TSEC_TXIC_ICFCT(16)
-		   | M83xx_TSEC_TXIC_ICTT(16));
+		   | M83xx_TSEC_TXIC_ICFCT(2)
+		   | M83xx_TSEC_TXIC_ICTT(32));
   /*
    * init receive interrupt coalescing register
    */
   reg_ptr->rxic = (M83xx_TSEC_RXIC_ICEN
-		   | M83xx_TSEC_RXIC_ICFCT(16)
-		   | M83xx_TSEC_RXIC_ICTT(16));
+		   | M83xx_TSEC_RXIC_ICFCT(2)
+		   | M83xx_TSEC_RXIC_ICTT(32));
   /*
    * init MACCFG1 register
@@ -674,5 +674,5 @@
       BD_ptr->length   = 0;
       BD_ptr->status   = (M83xx_BD_EMPTY 
-			  | M83xx_BD_INTERRUPT 
+			  | M83xx_BD_INTERRUPT
 			  | ((BD_ptr == sc->Rx_Last_BD) 
 			     ? M83xx_BD_WRAP 
@@ -972,5 +972,5 @@
       status = ((M83xx_BD_PAD_CRC | M83xx_BD_TX_CRC)
 		| ((m->m_next == NULL)        
-		   ? M83xx_BD_LAST | M83xx_BD_INTERRUPT 
+		   ? M83xx_BD_LAST | M83xx_BD_INTERRUPT
 		   : 0)
 		| ((CurrBD == sc->Tx_Last_BD) ? M83xx_BD_WRAP : 0));
@@ -1213,5 +1213,5 @@
    * clear error events in IEVENT
    */
-  sc->reg_ptr->tstat = M83xx_IEVENT_ERRALL;
+  sc->reg_ptr->ievent = M83xx_IEVENT_ERRALL;
   /*
    * has Rx been stopped? then restart it
@@ -1547,4 +1547,16 @@
     printf ("\n");
   }
+#if 1 /* print all PHY registers */
+  {
+    int reg;
+    uint32_t reg_val;
+    printf("****** PHY register values****\n");
+    for (reg = 0;reg <= 31;reg++) {
+      mpc83xx_tsec_mdio_read(-1,sc,reg,&reg_val);
+      printf("%02d:0x%04x%c",reg,reg_val,
+	     (((reg % 4) == 3) ? '\n' : ' '));
+    }
+  }
+#endif  
   /*
    * print some statistics
@@ -1714,11 +1726,4 @@
 	return result;
       }
-#ifdef DEBUG
-      /*
-       * test: print current status
-       */
-      rtems_ifmedia2str(media,NULL,0);
-      printf ("\n");
-#endif
     } while (IFM_NONE == IFM_SUBTYPE(media));
   }
@@ -1728,5 +1733,5 @@
    */
   /*
-   * if we are 1000MBit, then switch IF to GMII/byte mode
+   * if we are 1000MBit, then switch IF to byte mode
    */
   if (IFM_1000_T == IFM_SUBTYPE(media)) {
@@ -1739,4 +1744,13 @@
       ((sc->reg_ptr->maccfg2 & ~M83xx_TSEC_MACCFG2_IFMODE_MSK)
        | M83xx_TSEC_MACCFG2_IFMODE_NIB);
+  }
+  /*
+   * if we are 10MBit, then switch rate to 10M
+   */
+  if (IFM_10_T == IFM_SUBTYPE(media)) {
+    sc->reg_ptr->ecntrl &= ~M83xx_TSEC_ECNTRL_R100M;
+  }
+  else {
+    sc->reg_ptr->ecntrl |= M83xx_TSEC_ECNTRL_R100M;
   }
   /*
@@ -1886,4 +1900,13 @@
   }
 
+#if defined(HSC_CM01)
+  /*
+   * for HSC CM01: we need to configure the PHY to use maximum skew adjust
+   */
+  
+  mpc83xx_tsec_mdio_write(-1,sc,31,1);
+  mpc83xx_tsec_mdio_write(-1,sc,28,0xf000);
+  mpc83xx_tsec_mdio_write(-1,sc,31,0);
+#endif
   /*
    * Attach the interface
Index: c/src/lib/libcpu/powerpc/mpc83xx/spi/mpc83xx_spidrv.c
===================================================================
--- c/src/lib/libcpu/powerpc/mpc83xx/spi/mpc83xx_spidrv.c	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ c/src/lib/libcpu/powerpc/mpc83xx/spi/mpc83xx_spidrv.c	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -42,4 +42,5 @@
 \*-------------------------------------------------------------------------*/
  uint32_t baudrate,                      /* desired baudrate               */
+ uint32_t base_frq,                      /* input frequency                */
  uint32_t *spimode                       /* result value                   */
 )
@@ -54,5 +55,5 @@
    * determine clock divider and DIV16 bit
    */
-  divider = (BSP_CSB_CLK_FRQ+baudrate-1)/baudrate;
+  divider = (base_frq+baudrate-1)/baudrate;
   if (divider > 64) {
     tmpmode = MPC83XX_SPIMODE_DIV16;
@@ -587,5 +588,7 @@
    */
   if (rc == RTEMS_SUCCESSFUL) {
-    rc = mpc83xx_spi_baud_to_mode(tfr_mode->baudrate,&spimode_baud);
+    rc = mpc83xx_spi_baud_to_mode(tfr_mode->baudrate,
+				  softc_ptr->base_frq,
+				  &spimode_baud);
   }
   if (rc == RTEMS_SUCCESSFUL) {
Index: c/src/lib/libcpu/powerpc/mpc83xx/spi/mpc83xx_spidrv.h
===================================================================
--- c/src/lib/libcpu/powerpc/mpc83xx/spi/mpc83xx_spidrv.h	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ c/src/lib/libcpu/powerpc/mpc83xx/spi/mpc83xx_spidrv.h	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -33,4 +33,5 @@
   int                  initialized;
   rtems_irq_number     irq_number;
+  uint32_t             base_frq;    /* input frq for baud rate divider */
   rtems_id             irq_sema_id;
   uint32_t             curr_addr; /* current spi address */
Index: c/src/libchip/Makefile.am
===================================================================
--- c/src/libchip/Makefile.am	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ c/src/libchip/Makefile.am	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -75,5 +75,6 @@
 if LIBCHIP
 include_libchip_HEADERS += i2c/i2c-ds1621.h i2c/i2c-2b-eeprom.h \
-                           i2c/spi-flash-m25p40.h
+                           i2c/spi-memdrv.h                     \
+                           i2c/spi-flash-m25p40.h i2c/spi-fram-fm25l256.h
 
 noinst_LIBRARIES += libi2cio.a
@@ -81,5 +82,7 @@
 libi2cio_a_SOURCES  = i2c/i2c-ds1621.c i2c/i2c-2b-eeprom.c \
     i2c/i2c-ds1621.h i2c/i2c-2b-eeprom.h \
-    i2c/spi-flash-m25p40.c i2c/spi-flash-m25p40.h
+    i2c/spi-memdrv.c i2c/spi-memdrv.h \
+    i2c/spi-flash-m25p40.c i2c/spi-flash-m25p40.h \
+    i2c/spi-fram-fm25l256.c i2c/spi-fram-fm25l256.h
 endif
 
Index: c/src/libchip/i2c/spi-flash-m25p40.c
===================================================================
--- c/src/libchip/i2c/spi-flash-m25p40.c	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ c/src/libchip/i2c/spi-flash-m25p40.c	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -16,9 +16,4 @@
 +-----------------------------------------------------------------+
 \*===============================================================*/
-/*
- * FIXME: currently, this driver only supports read/write accesses
- * erase accesses are to be completed
- */
-
 
 #include <rtems.h>
@@ -28,343 +23,38 @@
 #include <rtems/libio.h>
 
-#define FLASH_M25P40_CMD_WREN  0x06
-#define FLASH_M25P40_CMD_WRDIS 0x04
-#define FLASH_M25P40_CMD_RDID  0x9F
-#define FLASH_M25P40_CMD_RDSR  0x05
-#define FLASH_M25P40_CMD_WRSR  0x01
-#define FLASH_M25P40_CMD_READ  0x03
-#define FLASH_M25P40_CMD_PP    0x02  /* page program                       */
-#define FLASH_M25P40_CMD_SE    0xD8  /* sector erase                       */
-#define FLASH_M25P40_CMD_BE    0xC7  /* bulk erase                         */
-#define FLASH_M25P40_CMD_DP    0xB9  /* deep power down                    */
-#define FLASH_M25P40_CMD_RES   0xAB  /* release from deep power down       */
 
-#define M25P40_PAGE_SIZE 256
-#define M25P40_TOTAL_SIZE (512*1024)
-
-const rtems_libi2c_tfr_mode_t spi_flash_m25p40_tfr_mode = {
-  baudrate:      20000000, /* maximum bits per second                   */
-  bits_per_char: 8,        /* how many bits per byte/word/longword?     */
-  lsb_first:      FALSE,   /* FALSE: send MSB first                     */
-  clock_inv:      FALSE,   /* FALSE: non-inverted clock (high active)   */
-  clock_phs:      FALSE    /* FALSE: clock starts in middle of data tfr */
-} ;
-
-/*=========================================================================*\
-| Function:                                                                 |
-\*-------------------------------------------------------------------------*/
-rtems_status_code spi_flash_m25p40_wait_ms
-(
-/*-------------------------------------------------------------------------*\
-| Purpose:                                                                  |
-|   wait a certain interval given in ms                                     |
-+---------------------------------------------------------------------------+
-| Input Parameters:                                                         |
-\*-------------------------------------------------------------------------*/
- int ms                                  /* time to wait in milliseconds   */
-)
-/*-------------------------------------------------------------------------*\
-| Return Value:                                                             |
-|    o = ok or error code                                                   |
-\*=========================================================================*/
-{
-  rtems_status_code          rc = RTEMS_SUCCESSFUL;
-  rtems_interval ticks_per_second;
-
-  rc = rtems_clock_get(RTEMS_CLOCK_GET_TICKS_PER_SECOND,&ticks_per_second);
-  if (rc == RTEMS_SUCCESSFUL) {
-    rc = rtems_task_wake_after(ticks_per_second * ms / 1000);
+static spi_memdrv_t spi_flash_m25p40_rw_drv_t = {
+  {/* public fields */
+  ops:         &spi_memdrv_rw_ops, /* operations of general memdrv */
+  size:        sizeof (spi_flash_m25p40_rw_drv_t),
+  },
+  { /* our private fields */
+  baudrate:             2000000,
+  erase_before_program: TRUE,
+  empty_state:          0xff,
+  page_size:            256, /* programming page size in byte */
+  sector_size:          64*1024, /* erase sector size in byte */
+  mem_size:             512*1024 /* total capacity in byte    */
   }
-  return rc;
-}
-
-/*=========================================================================*\
-| Function:                                                                 |
-\*-------------------------------------------------------------------------*/
-rtems_status_code spi_flash_m25p40_write
-(
-/*-------------------------------------------------------------------------*\
-| Purpose:                                                                  |
-|   write a block of data to flash                                          |
-+---------------------------------------------------------------------------+
-| Input Parameters:                                                         |
-\*-------------------------------------------------------------------------*/
- rtems_device_major_number major,        /* major device number            */
- rtems_device_major_number minor,        /* minor device number            */
- void                      *arg          /* ptr to write argument struct   */
-)
-/*-------------------------------------------------------------------------*\
-| Return Value:                                                             |
-|    o = ok or error code                                                   |
-\*=========================================================================*/
-{
-  rtems_status_code          rc = RTEMS_SUCCESSFUL;
-  rtems_libio_rw_args_t *rwargs = arg;
-  unsigned                  off = rwargs->offset;
-  int                       cnt = rwargs->count;
-  unsigned char            *buf = (unsigned char *)rwargs->buffer;
-  int                bytes_sent = 0;
-  int                  curr_cnt;
-  unsigned char       cmdbuf[4];
-  int                   ret_cnt = 0;
-  /*
-   * check arguments
-   */
-  if (rc == RTEMS_SUCCESSFUL) {
-    if ((cnt <= 0)                      ||
-	(cnt > M25P40_TOTAL_SIZE)       ||
-	(off > (M25P40_TOTAL_SIZE-cnt))) {
-      rc = RTEMS_INVALID_SIZE;
-    }
-    else if (buf == NULL) {
-      rc = RTEMS_INVALID_ADDRESS;
-    }
-  }
-  /*
-   * select device, set transfer mode, address device
-   */
-  if (rc == RTEMS_SUCCESSFUL) {
-    rc = rtems_libi2c_send_start(minor);
-  }
-  /*
-   * set transfer mode
-   */
-  if (rc == RTEMS_SUCCESSFUL) {
-    rc = -rtems_libi2c_ioctl(minor,
-			     RTEMS_LIBI2C_IOCTL_SET_TFRMODE,
-			     &spi_flash_m25p40_tfr_mode);
-  }
-
-  /*
-   * address device
-   */
-  if (rc == RTEMS_SUCCESSFUL) {
-    rc = rtems_libi2c_send_addr(minor,TRUE);
-  }
-
-  /*
-   * send write_enable command
-   */
-  if (rc == RTEMS_SUCCESSFUL) {
-    cmdbuf[0] = FLASH_M25P40_CMD_WREN;
-    ret_cnt = rtems_libi2c_write_bytes(minor,cmdbuf,1);
-    if (ret_cnt < 0) {
-      rc = -ret_cnt;
-    }
-  }
-  /*
-   * terminate transfer
-   */
-  if (rc == RTEMS_SUCCESSFUL) {
-    rc = rtems_libi2c_send_stop(minor);
-  }
-  while ((rc == RTEMS_SUCCESSFUL) && 
-	 (cnt > bytes_sent)) {
-    curr_cnt = cnt;
-    if ((off              / M25P40_PAGE_SIZE) != 
-	((off+curr_cnt+1) / M25P40_PAGE_SIZE)) {
-      curr_cnt = M25P40_PAGE_SIZE - (off % M25P40_PAGE_SIZE);
-    }
-    /*
-     * select device, set transfer mode
-     */
-    if (rc == RTEMS_SUCCESSFUL) {
-      rc = rtems_libi2c_send_start(minor);
-    }
-
-    /*
-     * address device
-     */
-    if (rc == RTEMS_SUCCESSFUL) {
-      rc = rtems_libi2c_send_addr(minor,TRUE);
-    }
-
-    /*
-     * set transfer mode
-     */
-    if (rc == RTEMS_SUCCESSFUL) {
-      rc = -rtems_libi2c_ioctl(minor,
-			       RTEMS_LIBI2C_IOCTL_SET_TFRMODE,
-			       &spi_flash_m25p40_tfr_mode);
-    }
-    /*
-     * send "page program" command and address
-     */
-    if (rc == RTEMS_SUCCESSFUL) {
-      cmdbuf[0] = FLASH_M25P40_CMD_PP;
-      cmdbuf[1] = (off >> 16) & 0xff;
-      cmdbuf[2] = (off >>  8) & 0xff;
-      cmdbuf[3] = (off >>  0) & 0xff;
-      ret_cnt = rtems_libi2c_write_bytes(minor,cmdbuf,4);
-      if (ret_cnt < 0) {
-	rc = -ret_cnt;
-      }
-    }
-    /*
-     * send write data
-     */
-    if (rc == RTEMS_SUCCESSFUL) {
-      ret_cnt = rtems_libi2c_write_bytes(minor,buf,curr_cnt);
-      if (ret_cnt < 0) {
-	rc = -ret_cnt;
-      }
-    }
-    /*
-     * terminate transfer
-     */
-    if (rc == RTEMS_SUCCESSFUL) {
-      rc = rtems_libi2c_send_stop(minor);
-    }
-    /*
-     * wait proper time for data to store: 5ms
-     */
-    if (rc == RTEMS_SUCCESSFUL) {
-      rc = spi_flash_m25p40_wait_ms(5);
-    }
-    /*
-     * adjust bytecount to be sent and pointers
-     */
-    bytes_sent += curr_cnt;
-    off        += curr_cnt;
-    buf        += curr_cnt;
-  }
-  rwargs->bytes_moved = bytes_sent;
-  return rc;
-}
-
-/*=========================================================================*\
-| Function:                                                                 |
-\*-------------------------------------------------------------------------*/
-rtems_status_code spi_flash_m25p40_read
-(
-/*-------------------------------------------------------------------------*\
-| Purpose:                                                                  |
-|   read a block of data from flash                                         |
-+---------------------------------------------------------------------------+
-| Input Parameters:                                                         |
-\*-------------------------------------------------------------------------*/
- rtems_device_major_number major,        /* major device number            */
- rtems_device_major_number minor,        /* minor device number            */
- void                      *arg          /* ptr to read argument struct    */
-)
-/*-------------------------------------------------------------------------*\
-| Return Value:                                                             |
-|    o = ok or error code                                                   |
-\*=========================================================================*/
-{
-  rtems_status_code rc = RTEMS_SUCCESSFUL;
-  rtems_libio_rw_args_t *rwargs = arg;
-  unsigned                  off = rwargs->offset;
-  int                       cnt = rwargs->count;
-  unsigned char            *buf = (unsigned char *)rwargs->buffer;
-  unsigned char       cmdbuf[4];
-  int                   ret_cnt = 0;
-  /*
-   * check arguments
-   */
-  if (rc == RTEMS_SUCCESSFUL) {
-    if ((cnt <= 0)                      ||
-	(cnt > M25P40_TOTAL_SIZE)       ||
-	(off > (M25P40_TOTAL_SIZE-cnt))) {
-      rc = RTEMS_INVALID_SIZE;
-    }
-    else if (buf == NULL) {
-      rc = RTEMS_INVALID_ADDRESS;
-    }
-  }
-  /*
-   * select device, set transfer mode, address device
-   */
-  if (rc == RTEMS_SUCCESSFUL) {
-    rc = rtems_libi2c_send_start(minor);
-  }
-  /*
-   * set transfer mode
-   */
-  if (rc == RTEMS_SUCCESSFUL) {
-    rc = -rtems_libi2c_ioctl(minor,
-			     RTEMS_LIBI2C_IOCTL_SET_TFRMODE,
-			     &spi_flash_m25p40_tfr_mode);
-  }
-  /*
-   * address device
-   */
-  if (rc == RTEMS_SUCCESSFUL) {
-    rc = rtems_libi2c_send_addr(minor,TRUE);
-  }
-
-  if (off >= M25P40_TOTAL_SIZE) {
-    /* 
-     * HACK: beyond size of Flash array? then read status register instead
-     */
-    /*
-     * send read status register command
-     */
-    if (rc == RTEMS_SUCCESSFUL) {
-      cmdbuf[0] = FLASH_M25P40_CMD_RDSR;
-      ret_cnt = rtems_libi2c_write_bytes(minor,cmdbuf,1);
-      if (ret_cnt < 0) {
-	rc = -ret_cnt;
-      }
-    }
-  }
-  else {
-    /*
-     * send read command and address
-     */
-    if (rc == RTEMS_SUCCESSFUL) {
-      cmdbuf[0] = FLASH_M25P40_CMD_READ;
-      cmdbuf[1] = (off >> 16) & 0xff;
-      cmdbuf[2] = (off >>  8) & 0xff;
-      cmdbuf[3] = (off >>  0) & 0xff;
-      ret_cnt = rtems_libi2c_write_bytes(minor,cmdbuf,4);
-      if (ret_cnt < 0) {
-	rc = -ret_cnt;
-      }
-    }
-  }
-  /*
-   * fetch read data 
-   */
-  if (rc == RTEMS_SUCCESSFUL) {
-    ret_cnt = rtems_libi2c_read_bytes (minor,buf,cnt);
-    if (ret_cnt < 0) {
-      rc = -ret_cnt;
-    }
-  }
-    
-  /*
-   * terminate transfer
-   */
-  if (rc == RTEMS_SUCCESSFUL) {
-    rc = rtems_libi2c_send_stop(minor);
-  }
-  rwargs->bytes_moved = (rc == RTEMS_SUCCESSFUL) ? ret_cnt : 0;
-
-  return rc;
-}
-
-static rtems_driver_address_table spi_flash_m25p40_rw_ops = {
-  read_entry:  spi_flash_m25p40_read,
-  write_entry: spi_flash_m25p40_write
-};
-
-static rtems_libi2c_drv_t spi_flash_m25p40_rw_drv_tbl = {
-  ops:         &spi_flash_m25p40_rw_ops,
-  size:        sizeof (spi_flash_m25p40_rw_drv_tbl),
 };
 
 rtems_libi2c_drv_t *spi_flash_m25p40_rw_driver_descriptor = 
-&spi_flash_m25p40_rw_drv_tbl;
+&spi_flash_m25p40_rw_drv_t.libi2c_drv_entry;
 
-static rtems_driver_address_table spi_flash_m25p40_ro_ops = {
-  read_entry:  spi_flash_m25p40_read,
-};
-
-static rtems_libi2c_drv_t spi_flash_m25p40_ro_drv_tbl = {
-  ops:         &spi_flash_m25p40_ro_ops,
-  size:        sizeof (spi_flash_m25p40_ro_drv_tbl),
+static spi_memdrv_t spi_flash_m25p40_ro_drv_t = {
+  {/* public fields */
+  ops:         &spi_memdrv_ro_ops, /* operations of general memdrv */
+  size:        sizeof (spi_flash_m25p40_ro_drv_t),
+  },
+  { /* our private fields */
+  baudrate:             2000000,
+  erase_before_program: TRUE,
+  empty_state:          0xff,
+  page_size:            256, /* programming page size in byte */
+  sector_size:          64*1024, /* erase sector size in byte */
+  mem_size:             512*1024 /* total capacity in byte    */
+  }
 };
 
 rtems_libi2c_drv_t *spi_flash_m25p40_ro_driver_descriptor = 
-&spi_flash_m25p40_ro_drv_tbl;
+&spi_flash_m25p40_ro_drv_t.libi2c_drv_entry;
Index: c/src/libchip/i2c/spi-flash-m25p40.h
===================================================================
--- c/src/libchip/i2c/spi-flash-m25p40.h	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ c/src/libchip/i2c/spi-flash-m25p40.h	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -25,5 +25,5 @@
 #define _LIBCHIP_SPI_FLASH_M25P40_H 
 
-#include <rtems/libi2c.h>
+#include <libchip/spi-memdrv.h>
 
 #ifdef __cplusplus
Index: c/src/libchip/i2c/spi-fram-fm25l256.c
===================================================================
--- c/src/libchip/i2c/spi-fram-fm25l256.c	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
+++ c/src/libchip/i2c/spi-fram-fm25l256.c	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -0,0 +1,60 @@
+/*===============================================================*\
+| Project: SPI driver for FM25L256 like spi fram device           |
++-----------------------------------------------------------------+
+|                    Copyright (c) 2008                           |
+|                    Embedded Brains GmbH                         |
+|                    Obere Lagerstr. 30                           |
+|                    D-82178 Puchheim                             |
+|                    Germany                                      |
+|                    rtems@embedded-brains.de                     |
++-----------------------------------------------------------------+
+| The license and distribution terms for this file may be         |
+| found in the file LICENSE in this distribution or at            |
+|                                                                 |
+| http://www.rtems.com/license/LICENSE.                           |
+|                                                                 |
++-----------------------------------------------------------------+
+\*===============================================================*/
+
+#include <rtems.h>
+#include <rtems/libi2c.h>
+
+#include <libchip/spi-fram-fm25l256.h>
+#include <rtems/libio.h>
+
+
+static spi_memdrv_t spi_fram_fm25l256_rw_drv_t = {
+  {/* public fields */
+  ops:         &spi_memdrv_rw_ops, /* operations of general memdrv */
+  size:        sizeof (spi_fram_fm25l256_rw_drv_t),
+  },
+  { /* our private fields */
+  baudrate:             2000000,
+  erase_before_program: FALSE,
+  empty_state:          0xff,
+  page_size:            32*1024, /* programming page size in byte */
+  sector_size:          1,       /* erase sector size in byte     */
+  mem_size:             32*1024  /* total capacity in byte        */
+  }
+};
+
+rtems_libi2c_drv_t *spi_fram_fm25l256_rw_driver_descriptor = 
+&spi_fram_fm25l256_rw_drv_t.libi2c_drv_entry;
+
+static spi_memdrv_t spi_fram_fm25l256_ro_drv_t = {
+  {/* public fields */
+  ops:         &spi_memdrv_ro_ops, /* operations of general memdrv */
+  size:        sizeof (spi_fram_fm25l256_ro_drv_t),
+  },
+  { /* our private fields */
+  baudrate:             2000000,
+  erase_before_program: FALSE,
+  empty_state:          0xff,
+  page_size:            32*1024, /* programming page size in byte */
+  sector_size:          1,       /* erase sector size in byte     */
+  mem_size:             32*1024  /* total capacity in byte        */
+  }
+};
+
+rtems_libi2c_drv_t *spi_fram_fm25l256_ro_driver_descriptor = 
+&spi_fram_fm25l256_ro_drv_t.libi2c_drv_entry;
Index: c/src/libchip/i2c/spi-fram-fm25l256.h
===================================================================
--- c/src/libchip/i2c/spi-fram-fm25l256.h	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
+++ c/src/libchip/i2c/spi-fram-fm25l256.h	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -0,0 +1,44 @@
+/*===============================================================*\
+| Project: SPI driver for FM25L256 like spi fram device           |
++-----------------------------------------------------------------+
+|                    Copyright (c) 2008                           |
+|                    Embedded Brains GmbH                         |
+|                    Obere Lagerstr. 30                           |
+|                    D-82178 Puchheim                             |
+|                    Germany                                      |
+|                    rtems@embedded-brains.de                     |
++-----------------------------------------------------------------+
+| The license and distribution terms for this file may be         |
+| found in the file LICENSE in this distribution or at            |
+|                                                                 |
+| http://www.rtems.com/license/LICENSE.                           |
+|                                                                 |
++-----------------------------------------------------------------+
+\*===============================================================*/
+/*
+ * FIXME: currently, this driver only supports read/write accesses
+ * erase accesses are to be completed
+ */
+
+
+#ifndef _LIBCHIP_SPI_FRAM_FM25L256_H 
+#define _LIBCHIP_SPI_FRAM_FM25L256_H 
+
+#include <libchip/spi-memdrv.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * pass one of these descriptor pointers to rtems_libi2c_register_drv 
+ */
+extern rtems_libi2c_drv_t *spi_fram_fm25l256_rw_driver_descriptor;
+
+extern rtems_libi2c_drv_t *spi_fram_fm25l256_ro_driver_descriptor;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _LIBCHIP_SPI_FRAM_FM25L256_H */
Index: c/src/libchip/i2c/spi-memdrv.c
===================================================================
--- c/src/libchip/i2c/spi-memdrv.c	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
+++ c/src/libchip/i2c/spi-memdrv.c	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -0,0 +1,445 @@
+/*===============================================================*\
+| Project: SPI driver for spi memory devices                      |
++-----------------------------------------------------------------+
+|                    Copyright (c) 2008                           |
+|                    Embedded Brains GmbH                         |
+|                    Obere Lagerstr. 30                           |
+|                    D-82178 Puchheim                             |
+|                    Germany                                      |
+|                    rtems@embedded-brains.de                     |
++-----------------------------------------------------------------+
+| The license and distribution terms for this file may be         |
+| found in the file LICENSE in this distribution or at            |
+|                                                                 |
+| http://www.rtems.com/license/LICENSE.                           |
+|                                                                 |
++-----------------------------------------------------------------+
+\*===============================================================*/
+/*
+ * FIXME: currently, this driver only supports read/write accesses
+ * erase accesses are to be completed
+ */
+
+
+#include <rtems.h>
+#include <rtems/libi2c.h>
+
+#include <libchip/spi-memdrv.h>
+#include <rtems/libio.h>
+
+#define SPI_MEM_CMD_WREN  0x06
+#define SPI_MEM_CMD_WRDIS 0x04
+#define SPI_MEM_CMD_RDID  0x9F
+#define SPI_MEM_CMD_RDSR  0x05
+#define SPI_MEM_CMD_WRSR  0x01
+#define SPI_MEM_CMD_READ  0x03
+#define SPI_MEM_CMD_PP    0x02  /* page program                       */
+#define SPI_MEM_CMD_SE    0xD8  /* sector erase                       */
+#define SPI_MEM_CMD_BE    0xC7  /* bulk erase                         */
+#define SPI_MEM_CMD_DP    0xB9  /* deep power down                    */
+#define SPI_MEM_CMD_RES   0xAB  /* release from deep power down       */
+
+/*=========================================================================*\
+| Function:                                                                 |
+\*-------------------------------------------------------------------------*/
+rtems_status_code spi_memdrv_minor2param_ptr
+(
+/*-------------------------------------------------------------------------*\
+| Purpose:                                                                  |
+|   translate given minor device number to param pointer                    |
++---------------------------------------------------------------------------+
+| Input Parameters:                                                         |
+\*-------------------------------------------------------------------------*/
+ rtems_device_minor_number minor,                /* minor number of device */
+ spi_memdrv_param_t **param_ptr                  /* ptr to param ptr       */
+)
+/*-------------------------------------------------------------------------*\
+| Return Value:                                                             |
+|    o = ok or error code                                                   |
+\*=========================================================================*/
+{
+  rtems_status_code   rc = RTEMS_SUCCESSFUL;
+  spi_memdrv_t *drv_ptr;
+
+  if (rc == RTEMS_SUCCESSFUL) {
+    rc = -rtems_libi2c_ioctl(minor,
+			     RTEMS_LIBI2C_IOCTL_GET_DRV_T,
+			     &drv_ptr);
+  }
+  if ((rc == RTEMS_SUCCESSFUL) &&
+      (drv_ptr->libi2c_drv_entry.size != sizeof(spi_memdrv_t))) {
+    rc = RTEMS_INVALID_SIZE;
+  }
+  if (rc == RTEMS_SUCCESSFUL) {
+    *param_ptr = &(drv_ptr->spi_memdrv_param);
+  }
+  return rc;
+}
+
+/*=========================================================================*\
+| Function:                                                                 |
+\*-------------------------------------------------------------------------*/
+rtems_status_code spi_memdrv_wait_ms
+(
+/*-------------------------------------------------------------------------*\
+| Purpose:                                                                  |
+|   wait a certain interval given in ms                                     |
++---------------------------------------------------------------------------+
+| Input Parameters:                                                         |
+\*-------------------------------------------------------------------------*/
+ int ms                                  /* time to wait in milliseconds   */
+)
+/*-------------------------------------------------------------------------*\
+| Return Value:                                                             |
+|    o = ok or error code                                                   |
+\*=========================================================================*/
+{
+  rtems_status_code          rc = RTEMS_SUCCESSFUL;
+  rtems_interval ticks_per_second;
+
+  rc = rtems_clock_get(RTEMS_CLOCK_GET_TICKS_PER_SECOND,&ticks_per_second);
+  if (rc == RTEMS_SUCCESSFUL) {
+    rc = rtems_task_wake_after(ticks_per_second * ms / 1000);
+  }
+  return rc;
+}
+
+/*=========================================================================*\
+| Function:                                                                 |
+\*-------------------------------------------------------------------------*/
+rtems_status_code spi_memdrv_write
+(
+/*-------------------------------------------------------------------------*\
+| Purpose:                                                                  |
+|   write a block of data to flash                                          |
++---------------------------------------------------------------------------+
+| Input Parameters:                                                         |
+\*-------------------------------------------------------------------------*/
+ rtems_device_major_number major,        /* major device number            */
+ rtems_device_minor_number minor,        /* minor device number            */
+ void                      *arg          /* ptr to write argument struct   */
+)
+/*-------------------------------------------------------------------------*\
+| Return Value:                                                             |
+|    o = ok or error code                                                   |
+\*=========================================================================*/
+{
+  rtems_status_code          rc = RTEMS_SUCCESSFUL;
+  rtems_libio_rw_args_t *rwargs = arg;
+  unsigned                  off = rwargs->offset;
+  int                       cnt = rwargs->count;
+  unsigned char            *buf = (unsigned char *)rwargs->buffer;
+  int                bytes_sent = 0;
+  int                  curr_cnt;
+  unsigned char       cmdbuf[4];
+  int                   ret_cnt = 0;
+  int                  cmd_size;
+  spi_memdrv_param_t  *mem_param_ptr;
+  rtems_libi2c_tfr_mode_t tfr_mode = {
+  baudrate:      20000000, /* maximum bits per second                   */
+  bits_per_char: 8,        /* how many bits per byte/word/longword?     */
+  lsb_first:      FALSE,   /* FALSE: send MSB first                     */
+  clock_inv:      FALSE,   /* FALSE: non-inverted clock (high active)   */
+  clock_phs:      FALSE    /* FALSE: clock starts in middle of data tfr */
+  } ;
+
+  /*
+   * get mem parameters
+   */
+  if (rc == RTEMS_SUCCESSFUL) {
+    rc = spi_memdrv_minor2param_ptr(minor,&mem_param_ptr);
+  }
+  /*
+   * check arguments
+   */
+  if (rc == RTEMS_SUCCESSFUL) {
+    if ((cnt <= 0)                      ||
+	(cnt > mem_param_ptr->mem_size) ||
+	(off > (mem_param_ptr->mem_size-cnt))) {
+      rc = RTEMS_INVALID_SIZE;
+    }
+    else if (buf == NULL) {
+      rc = RTEMS_INVALID_ADDRESS;
+    }
+  }
+  while ((rc == RTEMS_SUCCESSFUL) && 
+	 (cnt > bytes_sent)) {
+    curr_cnt = cnt;
+    if ((mem_param_ptr->page_size > 0) &&
+	(off              / mem_param_ptr->page_size) != 
+	((off+curr_cnt+1) / mem_param_ptr->page_size)) {
+      curr_cnt = mem_param_ptr->page_size - (off % mem_param_ptr->page_size);
+    }
+    /*
+     * select device, set transfer mode, address device
+     */
+    if (rc == RTEMS_SUCCESSFUL) {
+      rc = rtems_libi2c_send_start(minor);
+    }
+    /*
+     * set transfer mode
+     */
+    if (rc == RTEMS_SUCCESSFUL) {
+      tfr_mode.baudrate = mem_param_ptr->baudrate;
+      rc = -rtems_libi2c_ioctl(minor,
+			       RTEMS_LIBI2C_IOCTL_SET_TFRMODE,
+			       &tfr_mode);
+    }
+    
+    /*
+     * address device
+     */
+    if (rc == RTEMS_SUCCESSFUL) {
+      rc = rtems_libi2c_send_addr(minor,TRUE);
+    }
+
+    /*
+     * send write_enable command
+     */
+    if (rc == RTEMS_SUCCESSFUL) {
+      cmdbuf[0] = SPI_MEM_CMD_WREN;
+      ret_cnt = rtems_libi2c_write_bytes(minor,cmdbuf,1);
+      if (ret_cnt < 0) {
+	rc = -ret_cnt;
+      }
+    }
+    /*
+     * terminate transfer
+     */
+    if (rc == RTEMS_SUCCESSFUL) {
+      rc = rtems_libi2c_send_stop(minor);
+    }
+    /*
+     * select device, set transfer mode
+     */
+    if (rc == RTEMS_SUCCESSFUL) {
+      rc = rtems_libi2c_send_start(minor);
+    }
+
+    /*
+     * address device
+     */
+    if (rc == RTEMS_SUCCESSFUL) {
+      rc = rtems_libi2c_send_addr(minor,TRUE);
+    }
+
+    /*
+     * set transfer mode
+     */
+    if (rc == RTEMS_SUCCESSFUL) {
+      rc = -rtems_libi2c_ioctl(minor,
+			       RTEMS_LIBI2C_IOCTL_SET_TFRMODE,
+			       &tfr_mode);
+    }
+    /*
+     * send "page program" command and address
+     */
+    if (rc == RTEMS_SUCCESSFUL) {
+      cmdbuf[0] = SPI_MEM_CMD_PP;
+      if (mem_param_ptr->mem_size > 256*256) {
+	cmdbuf[1] = (off >> 16) & 0xff;
+	cmdbuf[2] = (off >>  8) & 0xff;
+	cmdbuf[3] = (off >>  0) & 0xff;
+	cmd_size  = 4;
+      }
+      else if (mem_param_ptr->mem_size > 256) {
+	cmdbuf[1] = (off >>  8) & 0xff;
+	cmdbuf[2] = (off >>  0) & 0xff;
+	cmd_size  = 3;
+      }
+      else {
+	cmdbuf[1] = (off >>  0) & 0xff;
+	cmd_size  = 1;
+      }
+
+      ret_cnt = rtems_libi2c_write_bytes(minor,cmdbuf,cmd_size);
+      if (ret_cnt < 0) {
+	rc = -ret_cnt;
+      }
+    }
+    /*
+     * send write data
+     */
+    if (rc == RTEMS_SUCCESSFUL) {
+      ret_cnt = rtems_libi2c_write_bytes(minor,buf,curr_cnt);
+      if (ret_cnt < 0) {
+	rc = -ret_cnt;
+      }
+    }
+    /*
+     * terminate transfer
+     */
+    if (rc == RTEMS_SUCCESSFUL) {
+      rc = rtems_libi2c_send_stop(minor);
+    }
+    /*
+     * wait proper time for data to store: 5ms
+     * FIXME: select proper interval or poll, until device is finished
+     */
+    if (rc == RTEMS_SUCCESSFUL) {
+      rc = spi_memdrv_wait_ms(5);
+    }
+    /*
+     * adjust bytecount to be sent and pointers
+     */
+    bytes_sent += curr_cnt;
+    off        += curr_cnt;
+    buf        += curr_cnt;
+  }
+  rwargs->bytes_moved = bytes_sent;
+  return rc;
+}
+
+/*=========================================================================*\
+| Function:                                                                 |
+\*-------------------------------------------------------------------------*/
+rtems_status_code spi_memdrv_read
+(
+/*-------------------------------------------------------------------------*\
+| Purpose:                                                                  |
+|   read a block of data from flash                                         |
++---------------------------------------------------------------------------+
+| Input Parameters:                                                         |
+\*-------------------------------------------------------------------------*/
+ rtems_device_major_number major,        /* major device number            */
+ rtems_device_minor_number minor,        /* minor device number            */
+ void                      *arg          /* ptr to read argument struct    */
+)
+/*-------------------------------------------------------------------------*\
+| Return Value:                                                             |
+|    o = ok or error code                                                   |
+\*=========================================================================*/
+{
+  rtems_status_code rc = RTEMS_SUCCESSFUL;
+  rtems_libio_rw_args_t *rwargs = arg;
+  unsigned                  off = rwargs->offset;
+  int                       cnt = rwargs->count;
+  unsigned char            *buf = (unsigned char *)rwargs->buffer;
+  unsigned char         cmdbuf[4];
+  int                   ret_cnt = 0;
+  int                  cmd_size;
+  spi_memdrv_param_t  *mem_param_ptr;
+  rtems_libi2c_tfr_mode_t tfr_mode = {
+  baudrate:      20000000, /* maximum bits per second                   */
+  bits_per_char: 8,        /* how many bits per byte/word/longword?     */
+  lsb_first:      FALSE,   /* FALSE: send MSB first                     */
+  clock_inv:      FALSE,   /* FALSE: non-inverted clock (high active)   */
+  clock_phs:      FALSE    /* FALSE: clock starts in middle of data tfr */
+  } ;
+
+  /*
+   * get mem parameters
+   */
+  if (rc == RTEMS_SUCCESSFUL) {
+    rc = spi_memdrv_minor2param_ptr(minor,&mem_param_ptr);
+  }
+  /*
+   * check arguments
+   */
+  if (rc == RTEMS_SUCCESSFUL) {
+    if ((cnt <= 0)                      ||
+	(cnt > mem_param_ptr->mem_size) ||
+	(off > (mem_param_ptr->mem_size-cnt))) {
+      rc = RTEMS_INVALID_SIZE;
+    }
+    else if (buf == NULL) {
+      rc = RTEMS_INVALID_ADDRESS;
+    }
+  }
+  /*
+   * select device, set transfer mode, address device
+   */
+  if (rc == RTEMS_SUCCESSFUL) {
+    rc = rtems_libi2c_send_start(minor);
+  }
+  /*
+   * set transfer mode
+   */
+  if (rc == RTEMS_SUCCESSFUL) {
+    tfr_mode.baudrate = mem_param_ptr->baudrate;
+    rc = -rtems_libi2c_ioctl(minor,
+			     RTEMS_LIBI2C_IOCTL_SET_TFRMODE,
+			     &tfr_mode);
+  }
+  /*
+   * address device
+   */
+  if (rc == RTEMS_SUCCESSFUL) {
+    rc = rtems_libi2c_send_addr(minor,TRUE);
+  }
+
+  if (off >= mem_param_ptr->mem_size) {
+    /* 
+     * HACK: beyond size of memory array? then read status register instead
+     */
+    /*
+     * send read status register command
+     */
+    if (rc == RTEMS_SUCCESSFUL) {
+      cmdbuf[0] = SPI_MEM_CMD_RDSR;
+      ret_cnt = rtems_libi2c_write_bytes(minor,cmdbuf,1);
+      if (ret_cnt < 0) {
+	rc = -ret_cnt;
+      }
+    }
+  }
+  else {
+    /*
+     * send read command and address
+     */
+    if (rc == RTEMS_SUCCESSFUL) {
+      cmdbuf[0] = SPI_MEM_CMD_READ;
+      if (mem_param_ptr->mem_size > 256*256) {
+	cmdbuf[1] = (off >> 16) & 0xff;
+	cmdbuf[2] = (off >>  8) & 0xff;
+	cmdbuf[3] = (off >>  0) & 0xff;
+	cmd_size  = 4;
+      }
+      else if (mem_param_ptr->mem_size > 256) {
+	cmdbuf[1] = (off >>  8) & 0xff;
+	cmdbuf[2] = (off >>  0) & 0xff;
+	cmd_size  = 3;
+      }
+      else {
+	cmdbuf[1] = (off >>  0) & 0xff;
+	cmd_size  = 1;
+      }
+      ret_cnt = rtems_libi2c_write_bytes(minor,cmdbuf,cmd_size);
+      if (ret_cnt < 0) {
+	rc = -ret_cnt;
+      }
+    }
+  }
+  /*
+   * fetch read data 
+   */
+  if (rc == RTEMS_SUCCESSFUL) {
+    ret_cnt = rtems_libi2c_read_bytes (minor,buf,cnt);
+    if (ret_cnt < 0) {
+      rc = -ret_cnt;
+    }
+  }
+    
+  /*
+   * terminate transfer
+   */
+  if (rc == RTEMS_SUCCESSFUL) {
+    rc = rtems_libi2c_send_stop(minor);
+  }
+  rwargs->bytes_moved = (rc == RTEMS_SUCCESSFUL) ? ret_cnt : 0;
+
+  return rc;
+}
+
+/*
+ * driver operation tables
+ */
+rtems_driver_address_table spi_memdrv_rw_ops = {
+  read_entry:  spi_memdrv_read,
+  write_entry: spi_memdrv_write
+};
+
+rtems_driver_address_table spi_memdrv_ro_ops = {
+  read_entry:  spi_memdrv_read,
+};
+
Index: c/src/libchip/i2c/spi-memdrv.h
===================================================================
--- c/src/libchip/i2c/spi-memdrv.h	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
+++ c/src/libchip/i2c/spi-memdrv.h	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -0,0 +1,90 @@
+/*===============================================================*\
+| Project: SPI driver for spi memory devices                      |
++-----------------------------------------------------------------+
+|                    Copyright (c) 2008                           |
+|                    Embedded Brains GmbH                         |
+|                    Obere Lagerstr. 30                           |
+|                    D-82178 Puchheim                             |
+|                    Germany                                      |
+|                    rtems@embedded-brains.de                     |
++-----------------------------------------------------------------+
+| The license and distribution terms for this file may be         |
+| found in the file LICENSE in this distribution or at            |
+|                                                                 |
+| http://www.rtems.com/license/LICENSE.                           |
+|                                                                 |
++-----------------------------------------------------------------+
+\*===============================================================*/
+
+
+#ifndef _LIBCHIP_SPI_MEMDRV_H 
+#define _LIBCHIP_SPI_MEMDRV_H 
+
+#include <rtems/libi2c.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*=========================================================================*\
+| Function:                                                                 |
+\*-------------------------------------------------------------------------*/
+rtems_status_code spi_memdrv_write
+(
+/*-------------------------------------------------------------------------*\
+| Purpose:                                                                  |
+|   write a block of data to memory                                         |
++---------------------------------------------------------------------------+
+| Input Parameters:                                                         |
+\*-------------------------------------------------------------------------*/
+ rtems_device_major_number major,        /* major device number            */
+ rtems_device_major_number minor,        /* minor device number            */
+ void                      *arg          /* ptr to write argument struct   */
+ );
+/*-------------------------------------------------------------------------*\
+| Return Value:                                                             |
+|    o = ok or error code                                                   |
+\*=========================================================================*/
+
+/*=========================================================================*\
+| Function:                                                                 |
+\*-------------------------------------------------------------------------*/
+rtems_status_code spi_memdrv_read
+(
+/*-------------------------------------------------------------------------*\
+| Purpose:                                                                  |
+|   read a block of data from memory                                        |
++---------------------------------------------------------------------------+
+| Input Parameters:                                                         |
+\*-------------------------------------------------------------------------*/
+ rtems_device_major_number major,        /* major device number            */
+ rtems_device_major_number minor,        /* minor device number            */
+ void                      *arg          /* ptr to read argument struct    */
+ );
+/*-------------------------------------------------------------------------*\
+| Return Value:                                                             |
+|    o = ok or error code                                                   |
+\*=========================================================================*/
+
+  typedef struct {
+    uint32_t baudrate;           /* tfr rate, bits per second     */
+    boolean  erase_before_program;
+    uint32_t empty_state;        /* value of erased cells         */
+    uint32_t page_size;          /* programming page size in byte */
+    uint32_t sector_size;        /* erase sector size in byte     */
+    uint32_t mem_size            /* total capacity in byte        */
+  } spi_memdrv_param_t;
+
+  typedef struct {
+    rtems_libi2c_drv_t  libi2c_drv_entry;  /* general i2c/spi params */
+    spi_memdrv_param_t  spi_memdrv_param;  /* private parameters     */
+  } spi_memdrv_t;
+
+  extern rtems_driver_address_table spi_memdrv_rw_ops;
+  extern rtems_driver_address_table spi_memdrv_ro_ops;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _LIBCHIP_SPI_MEMDRV_H */
Index: c/src/libchip/preinstall.am
===================================================================
--- c/src/libchip/preinstall.am	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ c/src/libchip/preinstall.am	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -126,7 +126,15 @@
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/libchip/i2c-2b-eeprom.h
 
+$(PROJECT_INCLUDE)/libchip/spi-memdrv.h: i2c/spi-memdrv.h $(PROJECT_INCLUDE)/libchip/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libchip/spi-memdrv.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libchip/spi-memdrv.h
+
 $(PROJECT_INCLUDE)/libchip/spi-flash-m25p40.h: i2c/spi-flash-m25p40.h $(PROJECT_INCLUDE)/libchip/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libchip/spi-flash-m25p40.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/libchip/spi-flash-m25p40.h
+
+$(PROJECT_INCLUDE)/libchip/spi-fram-fm25l256.h: i2c/spi-fram-fm25l256.h $(PROJECT_INCLUDE)/libchip/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libchip/spi-fram-fm25l256.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/libchip/spi-fram-fm25l256.h
 endif
 if LIBCHIP
Index: cpukit/ChangeLog
===================================================================
--- cpukit/ChangeLog	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ cpukit/ChangeLog	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -1,2 +1,7 @@
+2008-05-15	Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
+
+	* libi2c/libi2c.h, libi2c/libi2c.h: added interface to query
+	driver private data
+
 2008-05-13	Eric Norum: <norume@aps.anl.gov>
 
Index: cpukit/libi2c/libi2c.c
===================================================================
--- cpukit/libi2c/libi2c.c	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ cpukit/libi2c/libi2c.c	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -577,9 +577,7 @@
   int sc = 0;
   void *args;
+  boolean is_started = FALSE;
   DECL_CHECKED_BH (busno, bush, minor, -)
-
-    if (not_started (busno))
-    return -RTEMS_NOT_OWNER_OF_RESOURCE;
-
+    
   va_start(ap, cmd);
   args = va_arg(ap, void *);
@@ -590,5 +588,15 @@
      */
     
+  case RTEMS_LIBI2C_IOCTL_GET_DRV_T:
+    /*
+     * query driver table entry
+     */
+    *(rtems_libi2c_drv_t **)args = (drvs[MINOR2DRV(minor)-1].drv);
+    break;
+
   case RTEMS_LIBI2C_IOCTL_START_TFM_READ_WRITE:
+    if (not_started (busno))
+      return -RTEMS_NOT_OWNER_OF_RESOURCE;
+
     /*
      * address device, then set transfer mode and perform read_write transfer
@@ -599,4 +607,5 @@
     if (sc == 0) {
       sc = rtems_libi2c_send_start (minor);
+      is_started = (sc == 0);
     }
     /*
@@ -618,4 +627,7 @@
 	 &((rtems_libi2c_tfm_read_write_t *)args)->rd_wr);
     }
+    if ((sc < 0) && (is_started)) {
+      rtems_libi2c_send_stop (minor);
+    }
     break;
   default:
@@ -623,7 +635,5 @@
     break;
   }
-  if (sc < 0)
-    rtems_libi2c_send_stop (minor);
-  return sc;
+    return sc;
 }
 
Index: cpukit/libi2c/libi2c.h
===================================================================
--- cpukit/libi2c/libi2c.h	(revision 8ac748c1bfcb931c9e511cafbd1edbba14beb586)
+++ cpukit/libi2c/libi2c.h	(revision 42bf1b9f13d9269d9a98de4bdc1a11365865ef42)
@@ -414,6 +414,17 @@
  */
 
-/*
- * arguemtn data structures for IOCTLs defined above
+#define RTEMS_LIBI2C_IOCTL_GET_DRV_T 4
+/*
+ * retval = rtems_libi2c_ioctl(rtems_device_minor_number minor,
+ *                             RTEMS_LIBI2C_IOCTL_GET_DRV_T,
+ *                             const rtems_libi2c_drv_t *drv_t_ptr);
+ * 
+ * This call allows the a high-level driver to query its driver table entry,
+ * including its private data appended to it during creation of the entry
+ * 
+ */
+
+/*
+ * argument data structures for IOCTLs defined above
  */
 typedef struct {
