Changeset 42bf1b9 in rtems


Ignore:
Timestamp:
May 15, 2008, 3:10:38 PM (12 years ago)
Author:
Thomas Doerfler <Thomas.Doerfler@…>
Branches:
4.10, 4.11, 4.9, master
Children:
e0abba9
Parents:
8ac748c
Message:

adapted gen83xx to new board

Files:
5 added
39 edited

Legend:

Unmodified
Added
Removed
  • c/src/ChangeLog

    r8ac748c r42bf1b9  
     12008-05-15      Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
     2
     3        * libchip/i2c/spi-flash-m25p40.c, libchip/i2c/spi-flash-m25p40.h,
     4        * libchip/i2c/spi-fram-fm25l256.c, libchip/i2c/spi-fram-fm25l256.h,
     5        * libchip/i2c/spi-memdrv.c, libchip/i2c/spi-memdrv.h,
     6        * libchip/Makefile.am:
     7        derived a generic spi memory driver from spi-flash-m25p40,
     8        added descriptor for fram fm25l256
     9
    1102008-05-07      Till Straumann <strauman@slac.stanford.edu>
    211
  • c/src/lib/libbsp/arm/edb7312/preinstall.am

    r8ac748c r42bf1b9  
    6969PREINSTALL_FILES += $(PROJECT_INCLUDE)/irq.h
    7070
     71$(PROJECT_INCLUDE)/irq.h: irq/irq.h $(PROJECT_INCLUDE)/$(dirstamp)
     72        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/irq.h
     73PREINSTALL_FILES += $(PROJECT_INCLUDE)/irq.h
     74
  • c/src/lib/libbsp/arm/nds/preinstall.am

    r8ac748c r42bf1b9  
    1 ##
    2 ## $Id$
    3 ##
     1## Automatically generated by ampolish3 - Do not edit
    42
    53if AMPOLISH3
     
    3937PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h
    4038
     39$(PROJECT_INCLUDE)/tm27.h: include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp)
     40        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h
     41PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h
     42
    4143$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
    4244        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
     
    4749PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h
    4850
    49 $(PROJECT_INCLUDE)/tm27.h: include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp)
    50         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h
    51 PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h
    52 
    5351$(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
    5452        $(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT)
     
    5957PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds
    6058
     59$(PROJECT_INCLUDE)/rtems/$(dirstamp):
     60        @$(MKDIR_P) $(PROJECT_INCLUDE)/rtems
     61        @: > $(PROJECT_INCLUDE)/rtems/$(dirstamp)
     62PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp)
     63
     64$(PROJECT_INCLUDE)/rtems/fb.h: fb/fb.h $(PROJECT_INCLUDE)/rtems/$(dirstamp)
     65        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/fb.h
     66PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/fb.h
     67
     68$(PROJECT_INCLUDE)/rtems/touchscreen.h: touchscreen/touchscreen.h $(PROJECT_INCLUDE)/rtems/$(dirstamp)
     69        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/touchscreen.h
     70PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/touchscreen.h
     71
     72$(PROJECT_INCLUDE)/rtems/sound.h: sound/sound.h $(PROJECT_INCLUDE)/rtems/$(dirstamp)
     73        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/sound.h
     74PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/sound.h
     75
    6176$(PROJECT_INCLUDE)/irq.h: irq/irq.h $(PROJECT_INCLUDE)/$(dirstamp)
    6277        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/irq.h
    6378PREINSTALL_FILES += $(PROJECT_INCLUDE)/irq.h
     79
     80$(PROJECT_INCLUDE)/libnds/$(dirstamp):
     81        @$(MKDIR_P) $(PROJECT_INCLUDE)/libnds
     82        @: > $(PROJECT_INCLUDE)/libnds/$(dirstamp)
     83PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libnds/$(dirstamp)
     84
     85$(PROJECT_INCLUDE)/libnds/gbfs.h: libnds/include/gbfs.h $(PROJECT_INCLUDE)/libnds/$(dirstamp)
     86        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/gbfs.h
     87PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/gbfs.h
     88
     89$(PROJECT_INCLUDE)/libnds/nds.h: libnds/include/nds.h $(PROJECT_INCLUDE)/libnds/$(dirstamp)
     90        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds.h
     91PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds.h
     92
     93$(PROJECT_INCLUDE)/libnds/nds/$(dirstamp):
     94        @$(MKDIR_P) $(PROJECT_INCLUDE)/libnds/nds
     95        @: > $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
     96PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
     97
     98$(PROJECT_INCLUDE)/libnds/nds/memory.h: libnds/include/nds/memory.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
     99        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/memory.h
     100PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/memory.h
     101
     102$(PROJECT_INCLUDE)/libnds/nds/system.h: libnds/include/nds/system.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
     103        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/system.h
     104PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/system.h
     105
     106$(PROJECT_INCLUDE)/libnds/nds/bios.h: libnds/include/nds/bios.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
     107        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/bios.h
     108PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/bios.h
     109
     110$(PROJECT_INCLUDE)/libnds/nds/registers_alt.h: libnds/include/nds/registers_alt.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
     111        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/registers_alt.h
     112PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/registers_alt.h
     113
     114$(PROJECT_INCLUDE)/libnds/nds/interrupts.h: libnds/include/nds/interrupts.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
     115        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/interrupts.h
     116PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/interrupts.h
     117
     118$(PROJECT_INCLUDE)/libnds/nds/card.h: libnds/include/nds/card.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
     119        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/card.h
     120PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/card.h
     121
     122$(PROJECT_INCLUDE)/libnds/nds/ipc.h: libnds/include/nds/ipc.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
     123        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/ipc.h
     124PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/ipc.h
     125
     126$(PROJECT_INCLUDE)/libnds/nds/timers.h: libnds/include/nds/timers.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
     127        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/timers.h
     128PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/timers.h
     129
     130$(PROJECT_INCLUDE)/libnds/nds/dma.h: libnds/include/nds/dma.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
     131        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/dma.h
     132PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/dma.h
     133
     134$(PROJECT_INCLUDE)/libnds/nds/reload.h: libnds/include/nds/reload.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
     135        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/reload.h
     136PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/reload.h
     137
     138$(PROJECT_INCLUDE)/libnds/nds/jtypes.h: libnds/include/nds/jtypes.h $(PROJECT_INCLUDE)/libnds/nds/$(dirstamp)
     139        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/jtypes.h
     140PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/jtypes.h
     141
     142$(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp):
     143        @$(MKDIR_P) $(PROJECT_INCLUDE)/libnds/nds/arm9
     144        @: > $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
     145PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
     146
     147$(PROJECT_INCLUDE)/libnds/nds/arm9/ndsmotion.h: libnds/include/nds/arm9/ndsmotion.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
     148        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/ndsmotion.h
     149PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/ndsmotion.h
     150
     151$(PROJECT_INCLUDE)/libnds/nds/arm9/pcx.h: libnds/include/nds/arm9/pcx.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
     152        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/pcx.h
     153PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/pcx.h
     154
     155$(PROJECT_INCLUDE)/libnds/nds/arm9/input.h: libnds/include/nds/arm9/input.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
     156        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/input.h
     157PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/input.h
     158
     159$(PROJECT_INCLUDE)/libnds/nds/arm9/math.h: libnds/include/nds/arm9/math.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
     160        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/math.h
     161PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/math.h
     162
     163$(PROJECT_INCLUDE)/libnds/nds/arm9/console.h: libnds/include/nds/arm9/console.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
     164        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/console.h
     165PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/console.h
     166
     167$(PROJECT_INCLUDE)/libnds/nds/arm9/sprite.h: libnds/include/nds/arm9/sprite.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
     168        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/sprite.h
     169PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/sprite.h
     170
     171$(PROJECT_INCLUDE)/libnds/nds/arm9/videoGL.h: libnds/include/nds/arm9/videoGL.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
     172        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/videoGL.h
     173PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/videoGL.h
     174
     175$(PROJECT_INCLUDE)/libnds/nds/arm9/cache.h: libnds/include/nds/arm9/cache.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
     176        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/cache.h
     177PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/cache.h
     178
     179$(PROJECT_INCLUDE)/libnds/nds/arm9/image.h: libnds/include/nds/arm9/image.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
     180        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/image.h
     181PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/image.h
     182
     183$(PROJECT_INCLUDE)/libnds/nds/arm9/trig_lut.h: libnds/include/nds/arm9/trig_lut.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
     184        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/trig_lut.h
     185PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/trig_lut.h
     186
     187$(PROJECT_INCLUDE)/libnds/nds/arm9/video.h: libnds/include/nds/arm9/video.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
     188        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/video.h
     189PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/video.h
     190
     191$(PROJECT_INCLUDE)/libnds/nds/arm9/exceptions.h: libnds/include/nds/arm9/exceptions.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
     192        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/exceptions.h
     193PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/exceptions.h
     194
     195$(PROJECT_INCLUDE)/libnds/nds/arm9/rumble.h: libnds/include/nds/arm9/rumble.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
     196        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/rumble.h
     197PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/rumble.h
     198
     199$(PROJECT_INCLUDE)/libnds/nds/arm9/background.h: libnds/include/nds/arm9/background.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
     200        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/background.h
     201PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/background.h
     202
     203$(PROJECT_INCLUDE)/libnds/nds/arm9/boxtest.h: libnds/include/nds/arm9/boxtest.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
     204        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/boxtest.h
     205PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/boxtest.h
     206
     207$(PROJECT_INCLUDE)/libnds/nds/arm9/postest.h: libnds/include/nds/arm9/postest.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
     208        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/postest.h
     209PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/postest.h
     210
     211$(PROJECT_INCLUDE)/libnds/nds/arm9/sound.h: libnds/include/nds/arm9/sound.h $(PROJECT_INCLUDE)/libnds/nds/arm9/$(dirstamp)
     212        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm9/sound.h
     213PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm9/sound.h
     214
     215$(PROJECT_INCLUDE)/libnds/nds/arm7/$(dirstamp):
     216        @$(MKDIR_P) $(PROJECT_INCLUDE)/libnds/nds/arm7
     217        @: > $(PROJECT_INCLUDE)/libnds/nds/arm7/$(dirstamp)
     218PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libnds/nds/arm7/$(dirstamp)
     219
     220$(PROJECT_INCLUDE)/libnds/nds/arm7/serial.h: libnds/include/nds/arm7/serial.h $(PROJECT_INCLUDE)/libnds/nds/arm7/$(dirstamp)
     221        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm7/serial.h
     222PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm7/serial.h
     223
     224$(PROJECT_INCLUDE)/libnds/nds/arm7/audio.h: libnds/include/nds/arm7/audio.h $(PROJECT_INCLUDE)/libnds/nds/arm7/$(dirstamp)
     225        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm7/audio.h
     226PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm7/audio.h
     227
     228$(PROJECT_INCLUDE)/libnds/nds/arm7/clock.h: libnds/include/nds/arm7/clock.h $(PROJECT_INCLUDE)/libnds/nds/arm7/$(dirstamp)
     229        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm7/clock.h
     230PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm7/clock.h
     231
     232$(PROJECT_INCLUDE)/libnds/nds/arm7/touch.h: libnds/include/nds/arm7/touch.h $(PROJECT_INCLUDE)/libnds/nds/arm7/$(dirstamp)
     233        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libnds/nds/arm7/touch.h
     234PREINSTALL_FILES += $(PROJECT_INCLUDE)/libnds/nds/arm7/touch.h
     235
     236$(PROJECT_LIB)/coproc.bin: coproc.bin $(PROJECT_LIB)/$(dirstamp)
     237        $(INSTALL_DATA) $< $(PROJECT_LIB)/coproc.bin
     238TMPINSTALL_FILES += $(PROJECT_LIB)/coproc.bin
     239
  • c/src/lib/libbsp/bfin/eZKit533/preinstall.am

    r8ac748c r42bf1b9  
    3737PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h
    3838
    39 $(PROJECT_INCLUDE)/cplb.h: include/cplb.h $(PROJECT_INCLUDE)/$(dirstamp)
    40         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/cplb.h
    41 PREINSTALL_FILES += $(PROJECT_INCLUDE)/cplb.h
    42 
    4339$(PROJECT_INCLUDE)/tm27.h: include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp)
    4440        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h
  • c/src/lib/libbsp/powerpc/gen83xx/ChangeLog

    r8ac748c r42bf1b9  
     12008-05-15      Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
     2
     3        * network/network.c, start/start.S:
     4        add support for different board
     5
     62008-05-15      Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
     7
     8        * irq/ipic.c:
     9        make sure, that the masking operations in
     10        ICTL and MSR are executed in order
     11
     122008-05-15      Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
     13
     14        * include/bsp.h, startup/bspstart.c,
     15        * console/console.c, console/config.c:
     16        derived module input frequencies from internal bus clock during
     17        start time
     18
     192008-05-15      Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
     20
     21        * spi/spi_init.c:
     22        added base frequency into softc structure, added fm25l256 driver
     23
     242008-05-15      Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
     25
     26        * i2c/i2c_init.c:
     27        added base frequency into softc structure
     28
     292008-05-15      Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
     30
     31        * include/bsp.h, include/hwreg_vals.h, ./Makefile.am:
     32        moved HW register settings from bsp.h to hwreg_vals.h
     33
    1342008-05-14      Joel Sherrill <joel.sherrill@OARcorp.com>
    235
  • c/src/lib/libbsp/powerpc/gen83xx/Makefile.am

    r8ac748c r42bf1b9  
    4646
    4747include_bsp_HEADERS = ./irq/irq.h \
     48    ./include/hwreg_vals.h        \
    4849    ../../powerpc/shared/vectors/vectors.h
     50
    4951vectors_SOURCES = ../../powerpc/shared/vectors/vectors.h \
    5052    ../../powerpc/shared/vectors/vectors_init.c \
  • c/src/lib/libbsp/powerpc/gen83xx/console/config.c

    r8ac748c r42bf1b9  
    106106                NULL,                           /* getData */
    107107                NULL,                           /* setData */
    108                 BSP_CSB_CLK_FRQ,                /* ulClock */
     108                0,                              /* ulClock (filled in init) */
    109109                0                               /* ulIntVector */
    110         },
    111         {
     110        }
     111#if BSP_USE_UART2
     112        ,{
    112113                "/dev/ttyS1",                   /* sDeviceName */
    113114                SERIAL_NS16550,                 /* deviceType */
     
    125126                NULL,                           /* getData */
    126127                NULL,                           /* setData */
    127                 BSP_CSB_CLK_FRQ,                /* ulClock */
     128                0,                              /* ulClock (filled in init) */
    128129                0                               /* ulIntVector */
    129130        }
     131#endif
    130132};
    131133
  • c/src/lib/libbsp/powerpc/gen83xx/console/console.c

    r8ac748c r42bf1b9  
    174174  {
    175175    /*
     176     * transfer the real internal bus frequency into the
     177     * console port table
     178     */
     179    Console_Port_Tbl[minor].ulClock = BSP_bus_frequency;
     180    /*
    176181     * First perform the configuration dependant probe, then the
    177182     * device dependant probe
  • c/src/lib/libbsp/powerpc/gen83xx/i2c/i2c_init.c

    r8ac748c r42bf1b9  
    3232      reg_ptr:   &mpc83xx.i2c[0],
    3333      initialized: FALSE,
    34       irq_number:  BSP_IPIC_IRQ_I2C1
     34      irq_number :  BSP_IPIC_IRQ_I2C1,
     35      base_frq   : 0 /* will be set during initiailization */
    3536    }
    3637  },
     
    4445      reg_ptr:   &mpc83xx.i2c[1],
    4546      initialized: FALSE,
    46       irq_number:  BSP_IPIC_IRQ_I2C2
     47      irq_number :  BSP_IPIC_IRQ_I2C2,
     48      base_frq   : 0 /* will be set during initiailization */
    4749    }
    4850  }
     
    8284
    8385  /*
     86   * update input frequency of I2c modules into descriptor
     87   */
     88  /*
     89   * I2C1 is clocked with TSEC 1
     90   */
     91  if (((mpc83xx.clk.sccr >> (31-1)) & 0x03) > 0) {
     92    mpc83xx_i2c_bus_tbl[0].softc.base_frq =
     93      (BSP_bus_frequency
     94       /((mpc83xx.clk.sccr >> (31-1)) & 0x03));
     95  }
     96
     97  mpc83xx_i2c_bus_tbl[1].softc.base_frq = BSP_bus_frequency;
     98  /*
    8499   * register first I2C bus
    85100   */
     
    99114  }
    100115  i2c2_busno = ret_code;
     116
    101117  /*
    102118   * register EEPROM to bus 1, Address 0x50
     
    108124    return -ret_code;
    109125  }
     126
    110127  /*
    111128   * FIXME: register RTC driver, when available
  • c/src/lib/libbsp/powerpc/gen83xx/include/bsp.h

    r8ac748c r42bf1b9  
    2121#define __GEN83xx_BSP_h
    2222
    23 /*
    24  * distinguish board characteristics
    25  */
    26 /*
    27  * for Freescale MPC8349 EAMDS
    28  */
    29 #if defined(MPC8349EAMDS)
    30 /*
    31  * two DUART channels supported
    32  */
    33 #define GEN83xx_DUART_AVAIL_MASK 0x03
    34 
    35 /* we need the low level initialization in start.S*/
    36 #define NEED_LOW_LEVEL_INIT
    37 /*
    38  * clocking infos
    39  */
    40 #define BSP_CLKIN_FRQ 66000000L
    41 #define BSP_SYSPLL_MF 4 /* FIXME: derive from clock register */
    42 
    43 /*
    44  * Reset configuration words
    45  */
    46 #define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 |    \
    47                           RCWLR_DDRCM_1_1  |    \
    48                           RCWLR_SPMF(4)    |    \
    49                           RCWLR_COREPLL(4))
    50 
    51 #define RESET_CONF_WRD_H (RCWHR_PCI_HOST     |  \
    52                           RCWHR_PCI_32       |  \
    53                           RCWHR_PCI1ARB_EN   |  \
    54                           RCWHR_PCI2ARB_EN   |  \
    55                           RCWHR_CORE_EN      |  \
    56                           RCWHR_BMS_LOW      |  \
    57                           RCWHR_BOOTSEQ_NONE |  \
    58                           RCWHR_SW_DIS       |  \
    59                           RCWHR_ROMLOC_LB16  |  \
    60                           RCWHR_TSEC1M_GMII  |  \
    61                           RCWHR_TSEC2M_GMII  |  \
    62                           RCWHR_ENDIAN_BIG   |  \
    63                           RCWHR_LALE_NORM    |  \
    64                           RCWHR_LDP_PAR)
    65 /*
    66  * for JPK HSC_CM01
    67  */
    68 #elif defined(HSC_CM01)
    69 /*
    70  * one DUART channel (UART1) supported
    71  */
    72 #define GEN83xx_DUART_AVAIL_MASK 0x01
    73 
    74 /* we need the low level initialization in start.S*/
    75 #define NEED_LOW_LEVEL_INIT
    76 /*
    77  * clocking infos
    78  */
    79 #define BSP_CLKIN_FRQ 66000000L
    80 #define BSP_SYSPLL_MF 4 /* FIXME: derive from clock register */
    81 
    82 /*
    83  * Reset configuration words
    84  */
    85 #define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 |    \
    86                           RCWLR_DDRCM_1_1  |    \
    87                           RCWLR_SPMF(4)    |    \
    88                           RCWLR_COREPLL(4))
    89 
    90 #define RESET_CONF_WRD_H (RCWHR_PCI_HOST     |  \
    91                           RCWHR_PCI_32       |  \
    92                           RCWHR_PCI1ARB_EN   |  \
    93                           RCWHR_PCI2ARB_EN   |  \
    94                           RCWHR_CORE_EN      |  \
    95                           RCWHR_BMS_LOW      |  \
    96                           RCWHR_BOOTSEQ_NONE |  \
    97                           RCWHR_SW_DIS       |  \
    98                           RCWHR_ROMLOC_LB16  |  \
    99                           RCWHR_TSEC1M_RGMII |  \
    100                           RCWHR_TSEC2M_GMII  |  \
    101                           RCWHR_ENDIAN_BIG   |  \
    102                           RCWHR_LALE_NORM    |  \
    103                           RCWHR_LDP_PAR)
    104 #else
    105 #error "board type not defined"
    106 #endif
    107 
    108 /*
    109  * for JPK HSC_CM01 and freescale MPC8349EAMDS
    110  */
    111 #if defined(MPC8349EAMDS) || defined(HSC_CM01)
    112 /*
    113  * address range definitions
    114  */
    115 /* ROM definitions (8 MB, mirrored multiple times) */
    116 #define ROM_START       0xFE000000
    117 #define ROM_SIZE        0x02000000
    118 #define ROM_END         (ROM_START+ROM_SIZE-1)
    119 #define BOOT_START      ROM_START
    120 #define BOOT_END        ROM_END
    121 
    122 /* SDRAM definitions (256 MB) */
    123 #define RAM_START       0x00000000
    124 #define RAM_SIZE        0x10000000
    125 #define RAM_END         (RAM_START+RAM_SIZE-1)
    126 
    127 
    128 /* working internal memory map base address */
    129 #define IMMRBAR         0xE0000000
    130 
    131 /*
    132  * working values for various registers, used in start/start.S
    133  */
    134 /*
    135  * Local Access Windows
    136  * FIXME: decode bit settings
    137  */
    138 #define LBLAWBAR0_VAL  0xFE000000
    139 #define LBLAWAR0_VAL   0x80000016
    140 #define LBLAWBAR1_VAL  0xF8000000
    141 #define LBLAWAR1_VAL   0x8000000E
    142 #define LBLAWBAR2_VAL  0xF0000000
    143 #define LBLAWAR2_VAL   0x80000019
    144 #define DDRLAWBAR0_VAL 0x00000000
    145 #define DDRLAWAR0_VAL  0x8000001B
    146 /*
    147  * Local Bus (Memory) Controller
    148  * FIXME: decode bit settings
    149  */
    150 #define BR0_VAL 0xFE001001
    151 #define OR0_VAL 0xFF806FF7
    152 #define BR1_VAL 0xF8000801
    153 #define OR1_VAL 0xFFFFE8F0
    154 #define BR2_VAL 0xF0001861
    155 #define OR2_VAL 0xFC006901
    156 /*
    157  * SDRAM registers
    158  * FIXME: decode bit settings
    159  */
    160 #define MRPTR_VAL 0x20000000
    161 #define LSRT_VAL  0x32000000
    162 #define LSDMR_VAL 0x4062D733
    163 #define LCRR_VAL  0x80000004
    164 
    165 /*
    166  * DDR-SDRAM registers
    167  * FIXME: decode bit settings
    168  */
    169 #define CS2_BNDS_VAL                 0x00000007
    170 #define CS3_BNDS_VAL                 0x0008000F
    171 #define CS2_CONFIG_VAL               0x80000101
    172 #define CS3_CONFIG_VAL               0x80000101
    173 #define TIMING_CFG_1_VAL             0x36333321
    174 #define TIMING_CFG_2_VAL             0x00000800
    175 #define DDR_SDRAM_CFG_VAL            0xC2000000
    176 #define DDR_SDRAM_MODE_VAL           0x00000022
    177 #define DDR_SDRAM_INTTVL_VAL         0x045B0100
    178 #define DDR_SDRAM_CLK_CNTL_VAL       0x00000000
    179 
    180 #else
    181 #error "board type not defined"
    182 #endif
     23#include <bsp/hwreg_vals.h>
    18324
    18425#ifndef ASM
     
    24788#define PRINTK_MINOR BSP_UART1_MINOR
    24889
     90#if defined(MPC8249EAMDS)
     91#define BSP_USE_UART2 TRUE
     92#else
     93#define BSP_USE_UART2 FALSE
     94#endif
     95
    24996#define SINGLE_CHAR_MODE
    25097#define UARTS_USE_TERMIOS_INT   1
     
    261108 *   (int) ((float)(_value) / ((XLB_CLOCK/1000000 * 0.1) / 4.0))
    262109 */
    263 #define BSP_CSB_CLK_FRQ (BSP_CLKIN_FRQ * BSP_SYSPLL_MF)
     110
     111extern unsigned int BSP_bus_frequency;
    264112#define BSP_Convert_decrementer( _value ) \
    265   (int) (((_value) * 4000) / (BSP_CSB_CLK_FRQ/10000))
     113  (int) (((_value) * 4000) / (BSP_bus_frequency/10000))
    266114
    267115/*
     
    275123#define RTEMS_BSP_NETWORK_DRIVER_NAME2  "tsec2"
    276124
     125#if defined(MPC8349EAMDS)
    277126/*
    278127 * i2c EEPROM device name
     
    286135#define RTEMS_BSP_SPI_FLASH_DEVICE_NAME "flash"
    287136#define RTEMS_BSP_SPI_FLASH_DEVICE_PATH "/dev/spi.flash"
     137#endif /* defined(MPC8349EAMDS) */
     138
     139#if defined(HSC_CM01)
     140/*
     141 * i2c EEPROM device name
     142 */
     143#define RTEMS_BSP_I2C_EEPROM_DEVICE_NAME "eeprom"
     144#define RTEMS_BSP_I2C_EEPROM_DEVICE_PATH "/dev/i2c1.eeprom"
     145
     146/*
     147 * SPI FRAM device name
     148 */
     149#define RTEMS_BSP_SPI_FRAM_DEVICE_NAME "fram"
     150#define RTEMS_BSP_SPI_FRAM_DEVICE_PATH "/dev/spi.fram"
     151#endif /* defined(HSC_CM01) */
    288152
    289153#ifdef __cplusplus
  • c/src/lib/libbsp/powerpc/gen83xx/irq/ipic.c

    r8ac748c r42bf1b9  
    273273    mpc83xx.ipic.semsr    &= mask_ptr->semsr_mask   ;
    274274    mpc83xx.ipic.sermr    &= mask_ptr->sermr_mask   ;
     275
     276    /*
     277     * make sure, that the masking operations in
     278     * ICTL and MSR are executed in order
     279     */
     280    asm volatile("sync":::"memory");
     281   
    275282    /*
    276283     * reenable msr_ee
     
    294301     */
    295302    _CPU_MSR_SET(msr_save);
     303
     304    /*
     305     * make sure, that the masking operations in
     306     * ICTL and MSR are executed in order
     307     */
     308    asm volatile("sync":::"memory");
     309
    296310    /*
    297311     * restore initial masks
  • c/src/lib/libbsp/powerpc/gen83xx/network/network.c

    r8ac748c r42bf1b9  
    2727#include <stdio.h>
    2828
    29 #define TSEC_BITRATE 1000
    3029#define TSEC_IFMODE_RGMII 0
    3130#define TSEC_IFMODE_GMII  1
     31
     32#if defined(MPC8349EAMDS)
     33#define TSEC_IFMODE TSEC_IFMODE_GMII
     34#endif
     35
     36#if defined(HSC_CM01)
    3237#define TSEC_IFMODE TSEC_IFMODE_RGMII
     38#endif
    3339
    3440/*=========================================================================*\
     
    6268  }
    6369  if (attaching) {
     70#if (TSEC_IFMODE==TSEC_IFMODE_GMII)
    6471    if (unitNumber == 1) {
    6572      /*
     
    7481                               |                         0x0000001f);
    7582    }
    76   }
    77   if (unitNumber == 2) {
     83    if (unitNumber == 2) {
     84      /*
     85       * init port registers (GPIO2DIR) for TSEC2
     86       */
     87      mpc83xx.gpio[0].gpdir = ((mpc83xx.gpio[0].gpdir & ~0x000FFFFF)
     88                               |                         0x00087881);
     89    }
     90#endif
     91#if (TSEC_IFMODE==TSEC_IFMODE_RGMII)
     92
    7893    /*
    79      * init port registers (GPIO2DIR) for TSEC2
     94     * Nothing special needed for TSEC1 operation
    8095     */
    81     mpc83xx.gpio[0].gpdir = ((mpc83xx.gpio[0].gpdir & ~0x000FFFFF)
    82                              |                         0x00087881);
     96#endif   
    8397  }
    8498  /*
  • c/src/lib/libbsp/powerpc/gen83xx/preinstall.am

    r8ac748c r42bf1b9  
    8282PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
    8383
     84$(PROJECT_INCLUDE)/bsp/hwreg_vals.h: ./include/hwreg_vals.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     85        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/hwreg_vals.h
     86PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/hwreg_vals.h
     87
    8488$(PROJECT_INCLUDE)/bsp/vectors.h: ../../powerpc/shared/vectors/vectors.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    8589        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vectors.h
  • c/src/lib/libbsp/powerpc/gen83xx/spi/spi_init.c

    r8ac748c r42bf1b9  
    2222#include <bsp.h>
    2323#if defined(MPC8349EAMDS)
    24 #include <libchip/i2c-2b-eeprom.h>
    2524#include <libchip/spi-flash-m25p40.h>
     25#endif
     26#if defined(HSC_CM01)
     27#include <libchip/spi-fram-fm25l256.h>
    2628#endif
    2729
     
    190192    reg_ptr:     &mpc83xx.spi,
    191193    initialized: FALSE,
    192     irq_number:  BSP_IPIC_IRQ_SPI
     194    irq_number:  BSP_IPIC_IRQ_SPI,
     195    base_frq  :  0 /* filled in during init */
    193196  }
    194197};
     
    248251  mpc83xx.gpio[0].gpdr  &= ~(0xf << (31-27));
    249252#endif
     253  /*
     254   * update base frequency in spi descriptor
     255   */
     256  bsp_spi_bus_desc.softc.base_frq = BSP_bus_frequency;
     257
    250258  /*
    251259   * register SPI bus
     
    257265  }
    258266  spi_busno = ret_code;
    259   /*
    260    * register M25P40 Flash, when available
    261    */
    262 #if defined(MPC8349EAMDS)
     267#if defined(MPC8349EAMDS)
     268  /*
     269   * register M25P40 Flash
     270   */
    263271  ret_code = rtems_libi2c_register_drv(RTEMS_BSP_SPI_FLASH_DEVICE_NAME,
    264272                                       spi_flash_m25p40_rw_driver_descriptor,
     
    268276  }
    269277#endif
     278#if defined(HSC_CM01)
     279  /*
     280   * register FM25L256 FRAM
     281   */
     282  ret_code = rtems_libi2c_register_drv(RTEMS_BSP_SPI_FRAM_DEVICE_NAME,
     283                                       spi_fram_fm25l256_rw_driver_descriptor,
     284                                       spi_busno,0x02);
     285  if (ret_code < 0) {
     286    return -ret_code;
     287  }
     288#endif
    270289  /*
    271290   * FIXME: further drivers, when available
  • c/src/lib/libbsp/powerpc/gen83xx/start/start.S

    r8ac748c r42bf1b9  
    8686.extern MBAR   
    8787
     88#if defined(RESET_CONF_WRD_L)
    8889.section ".resconf","ax"
    8990PUBLIC_VAR (reset_conf_words)
     
    9899        REP8( .byte ((RESET_CONF_WRD_H >>  8) & 0xff))
    99100        REP8( .byte ((RESET_CONF_WRD_H >>  0) & 0xff))
     101#endif
    100102
    101103.section ".vectors","ax"
     
    146148        */
    147149        /*
    148          * FIXME:       
    149150         * we start from 0x100, so ROM is currently mapped to
    150151         * 0x00000000..
     
    224225        SET_IMM_REGW r31,r30,OR3_OFF,OR3_VAL
    225226#endif
     227       
    226228        /*
    227229         * ROM startup: init SDRAM access window
     
    240242#endif
    241243        /*
     244         * ROM startup: init refresh interval
     245         */
     246#ifdef MRPTR_VAL
     247        SET_IMM_REGW r31,r30,MRPTR_OFF,MRPTR_VAL
     248#endif 
     249        /*
    242250         * ROM startup: init SDRAM
    243251         */
     252#ifdef LSRT_VAL
     253        SET_IMM_REGW r31,r30, LSRT_OFF, LSRT_VAL
     254#endif
     255#ifdef LSDMR_VAL
     256        SET_IMM_REGW r31,r30, LSDMR_OFF, LSDMR_VAL
     257#endif
    244258#ifdef CS0_BNDS_VAL
    245259        SET_IMM_REGW r31,r30,CS0_BNDS_OFF,CS0_BNDS_VAL
     
    278292        SET_IMM_REGW r31,r30,TIMING_CFG_2_OFF,TIMING_CFG_2_VAL
    279293#endif
    280 #ifdef DDR_SDRAM_CFG_VAL
    281         SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_OFF,DDR_SDRAM_CFG_VAL
     294#ifdef DDRCDR_VAL
     295        SET_IMM_REGW r31,r30,DDRCDR_OFF,DDRCDR_VAL
    282296#endif
    283297#ifdef DDR_SDRAM_CFG_2_VAL
     
    299313        SET_IMM_REGW r31,r30,DDR_SDRAM_CLK_CNTL_OFF,DDR_SDRAM_CLK_CNTL_VAL
    300314#endif
     315#ifdef DDR_SDRAM_CFG_2_VAL
     316        SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_2_OFF,DDR_SDRAM_CFG_2_VAL|DDR_SDRAM_CFG_2_D_INIT
     317#endif
     318
     319#ifdef DDR_ERR_DISABLE_VAL
     320        /*
     321         * disable detect of RAM errors
     322         */
     323        SET_IMM_REGW r31,r30,DDR_ERR_DISABLE_OFF,DDR_ERR_DISABLE_VAL
     324#endif
     325#ifdef DDR_SDRAM_DATA_INIT_VAL
     326        /*
     327         * set this value to initialize memory
     328         */
     329        SET_IMM_REGW r31,r30,DDR_SDRAM_DATA_INIT_OFF,DDR_SDRAM_DATA_INIT_VAL
     330#endif
    301331#ifdef DDR_SDRAM_INIT_ADDR_VAL
    302332        SET_IMM_REGW r31,r30,DDR_SDRAM_INIT_ADDR_OFF,DDR_SDRAM_INIT_ADDR_VAL
    303333#endif
    304         /*
    305          * FIXME: ROM startup: perform mode set commands etc for SDRAM
    306          */
    307         /*
    308          * ROM startup: copy code to SDRAM
    309          */
    310         LA      r30, _text_start  /* get start address of text section in RAM */
    311         add     r30, r20, r30    /* get start address of text section in ROM (add reloc offset) */
    312         LA      r29, _text_start /* get start address of text section in RAM */
    313         LA      r28, _text_size  /* get size of RAM image */
    314         bl      copy_image      /* copy text section from ROM to RAM location */
    315        
    316         /*
    317          * FIXME: ROM startup: copy data to SDRAM
    318          */
    319         LA      r30, _data_start /* get start address of data section in RAM */
    320         add     r30, r20, r30    /* get start address of data section in ROM (add reloc offset) */
    321         LA      r29, _data_start /* get start address of data section in RAM */
    322         LA      r28, _data_size  /* get size of RAM image */
    323         bl      copy_image       /* copy initialized data section from ROM to RAM location */
     334#ifdef DDR_SDRAM_CFG_VAL
     335        /*
     336         * config DDR SDRAM
     337         */
     338        SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_OFF,DDR_SDRAM_CFG_VAL & ~DDR_SDRAM_CFG_MEM_EN
     339        /*
     340         * FIXME: wait 200us
     341         */
     342        /*
     343         * enable  DDR SDRAM
     344         */
     345        SET_IMM_REGW r31,r30,DDR_SDRAM_CFG_OFF,DDR_SDRAM_CFG_VAL | DDR_SDRAM_CFG_MEM_EN
     346        /*
     347         * wait, until DDR_SDRAM_CFG_2_D_INIT is cleared
     348         */
     3491:      lwz r30,DDR_SDRAM_CFG_2_OFF(r31)
     350        andi. r30,r30,DDR_SDRAM_CFG_2_D_INIT
     351        bne 1b
     352#endif
     353#ifdef DDR_ERR_DISABLE_VAL2
     354        /*
     355         * enable detect of some RAM errors
     356         */
     357        SET_IMM_REGW r31,r30,DDR_ERR_DISABLE_OFF,DDR_ERR_DISABLE_VAL2
     358#endif
     359#ifdef DDR_SDRAM_INTERVAL_VAL
     360        /*
     361         * set the refresh interval
     362         */
     363        SET_IMM_REGW r31,r30,DDR_SDRAM_INTERVAL_OFF,DDR_SDRAM_INTERVAL_VAL
     364#endif
     365start_rom_skip:
     366        /*
     367         * determine current execution address offset
     368         */
     369        bl start_rom_skip1
     370start_rom_skip1:
     371        mflr r20
     372        LA   r30,start_rom_skip1
     373        sub. r20,r20,r30       
     374        /*
     375         * execution address offset == 0?
     376         * then do not relocate code and data
     377         */
     378        beq  start_code_in_ram
     379        /*
     380         * ROM or relocatable startup: copy startup code to SDRAM
     381         */
     382        /* get start address of text section in RAM */
     383        LA      r29, _text_start 
     384        /* get start address of text section in ROM (add reloc offset) */
     385        add     r30, r20, r29   
     386        /* get size of startup code */
     387        LA      r28, end_reloc_startup
     388        LA      r31, _text_start
     389        sub     28,r28,r31
     390        /* copy startup code from ROM to RAM location */
     391        bl      copy_image     
     392       
    324393        /*
    325394         * ROM startup: jump to code copy in  SDRAM
    326395         */
    327         LA      r29, start_code_in_ram /* get compile time address of label */
     396        /* get compile time address of label */
     397        LA      r29, copy_rest_of_text
    328398        mtlr    r29
    329399        blr                     /* now further execution RAM */
     400copy_rest_of_text:     
     401#ifdef LCRR_VAL
     402        SET_IMM_REGW r31,r30,LCRR_OFF,LCRR_VAL
     403#endif
     404        /*
     405         * ROM or relocatable startup: copy rest of code to SDRAM
     406         */
     407        /* get start address of rest of code in RAM */
     408        LA      r29, end_reloc_startup
     409        /* get start address of text section in ROM (add reloc offset) */
     410        add     r30, r20, r29   
     411        /* get size of rest of code */
     412        LA      r28, _text_start
     413        LA      r31, _text_size
     414        add     r28,r28,r31
     415        sub     r28,r28,r29
     416        bl      copy_image      /* copy text section from ROM to RAM location */
     417       
     418        /*
     419         * ROM or relocatable startup: copy data to SDRAM
     420         */
     421        /* get start address of data section in RAM */
     422        LA      r29, _data_start
     423        /* get start address of data section in ROM (add reloc offset) */
     424        add     r30, r20, r29   
     425        /* get size of RAM image */
     426        LA      r28, _data_size 
     427        /* copy initialized data section from ROM to RAM location */
     428        bl      copy_image       
    330429
    331430start_code_in_ram:     
    332431
    333 start_rom_skip:
    334432        /*
    335433         * ROM/RAM startup: clear bss in SDRAM
     
    418516clr_mem_end:
    419517        blr                                     /* return */
     518end_reloc_startup:
  • c/src/lib/libbsp/powerpc/gen83xx/startup/bspstart.c

    r8ac748c r42bf1b9  
    4949 * BSP_time_base_divisor = TB ticks per millisecond/BSP_bus_frequency
    5050 */
    51 unsigned int BSP_bus_frequency = BSP_CSB_CLK_FRQ;
     51unsigned int BSP_bus_frequency;
    5252unsigned int BSP_time_base_divisor = 4000;  /* 4 bus clicks per TB click */
    5353
     
    189189
    190190  /*
     191   * this is evaluated during runtime, so it should be ok to set it
     192   * before we initialize the drivers
     193   */
     194  BSP_bus_frequency   = BSP_CLKIN_FRQ * BSP_SYSPLL_MF / BSP_SYSPLL_CKID;
     195  /*
    191196   *  initialize the device driver parameters
    192197   */
    193   bsp_clicks_per_usec        = (BSP_CSB_CLK_FRQ/1000000);
     198  bsp_clicks_per_usec = (BSP_bus_frequency/1000000);
    194199
    195200  /*
  • c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds

    r8ac748c r42bf1b9  
    4444    {
    4545    IMMRBAR = .;
    46     *mpc83xx_regs*(*)
     46    mpc83xx_regs*(.text)
     47    mpc83xx_regs*(.data)
     48    mpc83xx_regs*(.bss)
     49    mpc83xx_regs*(*COM*)
    4750    } > mpc83xx_regs
    4851
  • c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.hsc_cm01

    r8ac748c r42bf1b9  
    3838{
    3939
    40     mpc83xx_regs (NOLOAD) :
     40    .mpc83xx_regs (NOLOAD) :
    4141    {
    4242    IMMRBAR = .;
    43     *mpc83xx_regs*(*)
     43    mpc83xx_regs*(.text)
     44    mpc83xx_regs*(.data)
     45    mpc83xx_regs*(.bss)
     46    mpc83xx_regs*(*COM*)
    4447    } > mpc83xx_regs
    4548
  • c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.mpc8349eamds

    r8ac748c r42bf1b9  
    4141    {
    4242    IMMRBAR = .;
    43     *mpc83xx_regs*(*)
     43    mpc83xx_regs*(.text)
     44    mpc83xx_regs*(.data)
     45    mpc83xx_regs*(.bss)
     46    mpc83xx_regs*(*COM*)
    4447    } > mpc83xx_regs
    4548
  • c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog

    r8ac748c r42bf1b9  
     12008-05-15      Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
     2
     3        * irq/irq.c:
     4        make sure, that the masking operations in
     5        ICTL and MSR are executed in order
     6
    172008-05-14      Joel Sherrill <joel.sherrill@OARcorp.com>
    28
  • c/src/lib/libbsp/powerpc/mbx8xx/irq/irq.c

    r8ac748c r42bf1b9  
    473473      ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = ppc_cached_irq_mask;
    474474    }
     475    /*
     476     * make sure, that the masking operations in
     477     * ICTL and MSR are executed in order
     478     */
     479    asm volatile("sync":::"memory");
     480
    475481    _CPU_MSR_GET(msr);
    476482    new_msr = msr | MSR_EE;
     
    480486
    481487    _CPU_MSR_SET(msr);
     488
     489    /*
     490     * make sure, that the masking operations in
     491     * ICTL and MSR are executed in order
     492     */
     493    asm volatile("sync":::"memory");
    482494
    483495    if (cpmIntr)  {
  • c/src/lib/libbsp/powerpc/mpc8260ads/ChangeLog

    r8ac748c r42bf1b9  
     12008-05-15      Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
     2
     3        * irq/irq.c:
     4        make sure, that the masking operations in
     5        ICTL and MSR are executed in order
     6
    172008-05-14      Joel Sherrill <joel.sherrill@OARcorp.com>
    28
  • c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq.c

    r8ac748c r42bf1b9  
    484484                        m8260.sipnr_l |= SIU_MaskBit[irq].mask_l;
    485485
     486                        /*
     487                         * make sure, that the masking operations in
     488                         * ICTL and MSR are executed in order
     489                         */
     490                        asm volatile("sync":::"memory");
     491
    486492                        /* re-enable external exceptions */
    487493                        _CPU_MSR_GET(msr);
     
    495501                        _CPU_MSR_SET(msr);
    496502
     503                        /*
     504                         * make sure, that the masking operations in
     505                         * ICTL and MSR are executed in order
     506                         */
     507                        asm volatile("sync":::"memory");
     508
    497509                        /* restore interrupt masks */
    498510                        m8260.simr_h = old_simr_h;
  • c/src/lib/libbsp/powerpc/mvme3100/preinstall.am

    r8ac748c r42bf1b9  
    138138PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vpd.h
    139139
     140if HAS_NETWORKING
    140141$(PROJECT_INCLUDE)/bsp/if_tsec_pub.h: network/if_tsec_pub.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    141142        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/if_tsec_pub.h
    142143PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/if_tsec_pub.h
    143 
     144endif
  • c/src/lib/libbsp/powerpc/mvme5500/preinstall.am

    r8ac748c r42bf1b9  
    114114PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/VPD.h
    115115
    116 if HAS_NETWORKING
    117 $(PROJECT_INCLUDE)/bsp/GT64260eth.h: network/if_100MHz/GT64260eth.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    118         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/GT64260eth.h
    119 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/GT64260eth.h
    120 
    121 $(PROJECT_INCLUDE)/bsp/GT64260ethreg.h: network/if_100MHz/GT64260ethreg.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    122         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/GT64260ethreg.h
    123 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/GT64260ethreg.h
    124 
    125 $(PROJECT_INCLUDE)/bsp/if_wmreg.h: network/if_1GHz/if_wmreg.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    126         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/if_wmreg.h
    127 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/if_wmreg.h
    128 
    129 $(PROJECT_INCLUDE)/bsp/pcireg.h: network/if_1GHz/pcireg.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    130         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/pcireg.h
    131 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/pcireg.h
    132 endif
    133116$(PROJECT_INCLUDE)/bsp/VME.h: ../../shared/vmeUniverse/VME.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    134117        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/VME.h
     
    159142PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vme_am_defs.h
    160143
     144if HAS_NETWORKING
     145$(PROJECT_INCLUDE)/bsp/GT64260eth.h: network/if_100MHz/GT64260eth.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     146        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/GT64260eth.h
     147PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/GT64260eth.h
     148
     149$(PROJECT_INCLUDE)/bsp/GT64260ethreg.h: network/if_100MHz/GT64260ethreg.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     150        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/GT64260ethreg.h
     151PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/GT64260ethreg.h
     152
     153$(PROJECT_INCLUDE)/bsp/if_wmreg.h: network/if_1GHz/if_wmreg.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     154        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/if_wmreg.h
     155PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/if_wmreg.h
     156
     157$(PROJECT_INCLUDE)/bsp/pcireg.h: network/if_1GHz/pcireg.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     158        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/pcireg.h
     159PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/pcireg.h
     160endif
    161161$(PROJECT_LIB)/rtems_crti.$(OBJEXT): rtems_crti.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
    162162        $(INSTALL_DATA) $< $(PROJECT_LIB)/rtems_crti.$(OBJEXT)
  • c/src/lib/libcpu/powerpc/ChangeLog

    r8ac748c r42bf1b9  
     12008-05-15      Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
     2
     3        * mpc83xx/network/tsec.c, mpc83xx/include/mpc83xx.h:
     4        added support for RGMII interface and different board
     5
     62008-05-15      Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
     7
     8        * mpc83xx/i2c/mpc83xx_i2cdrv.c, mpc83xx/i2c/mpc83xx_i2cdrv.h,
     9        * mpc83xx/spi/mpc83xx_spidrv.c, mpc83xx/spi/mpc83xx_spidrv.h:
     10        added base frequency into softc structure
     11
    1122008-05-14      Till Straumann <strauman@slac.stanford.edu>
    213
  • c/src/lib/libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.c

    r8ac748c r42bf1b9  
    3232| Function:                                                                 |
    3333\*-------------------------------------------------------------------------*/
    34 static int mpc83xx_i2c_find_clock_divider
     34static rtems_status_code mpc83xx_i2c_find_clock_divider
    3535(
    3636/*-------------------------------------------------------------------------*\
     
    5050  int i;
    5151  int fdr_val;
     52  rtems_status_code sc = RTEMS_SUCCESSFUL;
    5253  struct {
    5354    int divider;
     
    6970  };
    7071
    71   for (i = 0, fdr_val = -1; i < sizeof(dividers)/sizeof(dividers[0]); i++) {
    72     fdr_val = dividers[i].fdr_val;
    73     if (dividers[i].divider >= divider)
    74       {
    75         break;
    76       }
    77   }
    78   *result = fdr_val;
    79   return 0;
     72  if (divider <= 0) {
     73    sc = RTEMS_INVALID_NUMBER;
     74  }
     75
     76  if (sc == RTEMS_SUCCESSFUL) {
     77    sc = RTEMS_INVALID_NUMBER;
     78    for (i = 0, fdr_val = -1; i < sizeof(dividers)/sizeof(dividers[0]); i++) {
     79      fdr_val = dividers[i].fdr_val;
     80      if (dividers[i].divider >= divider)
     81        {
     82          sc = RTEMS_SUCCESSFUL;
     83          *result = fdr_val;
     84          break;
     85        }
     86    }
     87  }
     88  return sc;
    8089}
    8190
     
    314323   */
    315324  errval = mpc83xx_i2c_find_clock_divider(&fdr_val,
    316                                           BSP_CSB_CLK_FRQ/3/100000);
     325                                          softc_ptr->base_frq/100000);
    317326  if (errval != 0) {
    318327    return errval;
     
    472481    }
    473482  }
    474   addr_byte = (0xf0
    475                | ((addr >> 7) & 0x06)
    476                | ((rw) ? 1 : 0));
    477483  /*
    478484   * send (final) byte
     
    525531  softc_ptr->reg_ptr->i2ccr &= ~MPC83XX_I2CCR_MTX;
    526532  softc_ptr->reg_ptr->i2ccr &= ~MPC83XX_I2CCR_TXAK;
     533  /*
     534   * FIXME: do we need to deactivate TXAK from the start,
     535   * when only one byte is to be received?
     536   */
    527537  /*
    528538   * we need a dummy transfer here to start the first read
  • c/src/lib/libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.h

    r8ac748c r42bf1b9  
    2929
    3030typedef struct mpc83xx_i2c_softc {
    31   m83xxI2CRegisters_t *reg_ptr;
    32   int                  initialized;
    33   rtems_irq_number     irq_number;
    34   rtems_id             irq_sema_id;
     31  m83xxI2CRegisters_t *reg_ptr;     /* ptr to HW registers             */
     32  int                  initialized; /* TRUE: module is initialized     */
     33  rtems_irq_number     irq_number;  /* IRQ number used for this module */
     34  uint32_t             base_frq;    /* input frq for baud rate divider */
     35  rtems_id             irq_sema_id; /* SEMA used for IRQ signalling    */
    3536} mpc83xx_i2c_softc_t ;
    3637
  • c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h

    r8ac748c r42bf1b9  
    11111111#define OR7_OFF  0x0503C
    11121112
     1113#define MRPTR_OFF                    0x05084
     1114#define LSDMR_OFF                    0x05094
     1115#define LSRT_OFF                     0x050A4
     1116#define LCRR_OFF                     0x050d4
     1117
     1118
    11131119#define CS0_BNDS_OFF       0x02000
    11141120#define CS1_BNDS_OFF       0x02008
     
    11281134#define DDR_SDRAM_MODE_2_OFF         0x0211C
    11291135#define DDR_SDRAM_MD_CNTL_OFF        0x02120
    1130 #define DDR_SDRAM_MD_ITVL_OFF        0x02124
     1136#define DDR_SDRAM_INTERVAL_OFF       0x02124
     1137#define DDR_SDRAM_DATA_INIT_OFF      0x02128
     1138#define DDRCDR_OFF                   0x0012C
    11311139#define DDR_SDRAM_CLK_CNTL_OFF       0x02130
    11321140#define DDR_SDRAM_INIT_ADDR_OFF      0x02148
     1141#define DDR_ERR_DISABLE_OFF          0x02E44
     1142
     1143/*
     1144 * some bits in DDR_SDRAM_CFG register
     1145 */
     1146#define DDR_SDRAM_CFG_MEM_EN (1 << (31- 0))     /* enable memory        */
     1147/*
     1148 * bits in DDR_SDRAM_CFG_2 register
     1149 */
     1150#define DDR_SDRAM_CFG_2_D_FRC_SR (1 << (31- 0)) /* force self refresh        */
     1151#define DDR_SDRAM_CFG_2_D_SR_IE  (1 << (31- 1)) /* self refresh interrupt en */
     1152#define DDR_SDRAM_CFG_2_D_DLL_RST_DIS  (1 << (31- 2)) /* DLL reset disable   */
     1153#define DDR_SDRAM_CFG_2_D_DQS_CFG_DIF  (1 << (31- 5)) /* use diff. DQS       */
     1154#define DDR_SDRAM_CFG_2_D_INIT   (1 << (31-27)) /* Init DRAM with pattern    */
    11331155
    11341156/*
  • c/src/lib/libcpu/powerpc/mpc83xx/network/tsec.c

    r8ac748c r42bf1b9  
    116116#define M83xx_IEVENT_TXALL (M83xx_TSEC_IEVENT_GTSC      \
    117117                            | M83xx_TSEC_IEVENT_TXC     \
    118                             | M83xx_TSEC_IEVENT_TXB     \
     118                            /*| M83xx_TSEC_IEVENT_TXB*/ \
    119119                            | M83xx_TSEC_IEVENT_TXF )
    120120
     
    123123 */
    124124#define M83xx_IEVENT_RXALL (M83xx_TSEC_IEVENT_RXC       \
    125                             | M83xx_TSEC_IEVENT_RXB     \
     125                            /* | M83xx_TSEC_IEVENT_RXB */       \
    126126                            | M83xx_TSEC_IEVENT_GRSC    \
    127127                            | M83xx_TSEC_IEVENT_RXF  )
     
    252252   */
    253253  reg_ptr->txic = (M83xx_TSEC_TXIC_ICEN
    254                    | M83xx_TSEC_TXIC_ICFCT(16)
    255                    | M83xx_TSEC_TXIC_ICTT(16));
     254                   | M83xx_TSEC_TXIC_ICFCT(2)
     255                   | M83xx_TSEC_TXIC_ICTT(32));
    256256  /*
    257257   * init receive interrupt coalescing register
    258258   */
    259259  reg_ptr->rxic = (M83xx_TSEC_RXIC_ICEN
    260                    | M83xx_TSEC_RXIC_ICFCT(16)
    261                    | M83xx_TSEC_RXIC_ICTT(16));
     260                   | M83xx_TSEC_RXIC_ICFCT(2)
     261                   | M83xx_TSEC_RXIC_ICTT(32));
    262262  /*
    263263   * init MACCFG1 register
     
    674674      BD_ptr->length   = 0;
    675675      BD_ptr->status   = (M83xx_BD_EMPTY
    676                           | M83xx_BD_INTERRUPT 
     676                          | M83xx_BD_INTERRUPT
    677677                          | ((BD_ptr == sc->Rx_Last_BD)
    678678                             ? M83xx_BD_WRAP
     
    972972      status = ((M83xx_BD_PAD_CRC | M83xx_BD_TX_CRC)
    973973                | ((m->m_next == NULL)       
    974                    ? M83xx_BD_LAST | M83xx_BD_INTERRUPT 
     974                   ? M83xx_BD_LAST | M83xx_BD_INTERRUPT
    975975                   : 0)
    976976                | ((CurrBD == sc->Tx_Last_BD) ? M83xx_BD_WRAP : 0));
     
    12131213   * clear error events in IEVENT
    12141214   */
    1215   sc->reg_ptr->tstat = M83xx_IEVENT_ERRALL;
     1215  sc->reg_ptr->ievent = M83xx_IEVENT_ERRALL;
    12161216  /*
    12171217   * has Rx been stopped? then restart it
     
    15471547    printf ("\n");
    15481548  }
     1549#if 1 /* print all PHY registers */
     1550  {
     1551    int reg;
     1552    uint32_t reg_val;
     1553    printf("****** PHY register values****\n");
     1554    for (reg = 0;reg <= 31;reg++) {
     1555      mpc83xx_tsec_mdio_read(-1,sc,reg,&reg_val);
     1556      printf("%02d:0x%04x%c",reg,reg_val,
     1557             (((reg % 4) == 3) ? '\n' : ' '));
     1558    }
     1559  }
     1560#endif 
    15491561  /*
    15501562   * print some statistics
     
    17141726        return result;
    17151727      }
    1716 #ifdef DEBUG
    1717       /*
    1718        * test: print current status
    1719        */
    1720       rtems_ifmedia2str(media,NULL,0);
    1721       printf ("\n");
    1722 #endif
    17231728    } while (IFM_NONE == IFM_SUBTYPE(media));
    17241729  }
     
    17281733   */
    17291734  /*
    1730    * if we are 1000MBit, then switch IF to GMII/byte mode
     1735   * if we are 1000MBit, then switch IF to byte mode
    17311736   */
    17321737  if (IFM_1000_T == IFM_SUBTYPE(media)) {
     
    17391744      ((sc->reg_ptr->maccfg2 & ~M83xx_TSEC_MACCFG2_IFMODE_MSK)
    17401745       | M83xx_TSEC_MACCFG2_IFMODE_NIB);
     1746  }
     1747  /*
     1748   * if we are 10MBit, then switch rate to 10M
     1749   */
     1750  if (IFM_10_T == IFM_SUBTYPE(media)) {
     1751    sc->reg_ptr->ecntrl &= ~M83xx_TSEC_ECNTRL_R100M;
     1752  }
     1753  else {
     1754    sc->reg_ptr->ecntrl |= M83xx_TSEC_ECNTRL_R100M;
    17411755  }
    17421756  /*
     
    18861900  }
    18871901
     1902#if defined(HSC_CM01)
     1903  /*
     1904   * for HSC CM01: we need to configure the PHY to use maximum skew adjust
     1905   */
     1906 
     1907  mpc83xx_tsec_mdio_write(-1,sc,31,1);
     1908  mpc83xx_tsec_mdio_write(-1,sc,28,0xf000);
     1909  mpc83xx_tsec_mdio_write(-1,sc,31,0);
     1910#endif
    18881911  /*
    18891912   * Attach the interface
  • c/src/lib/libcpu/powerpc/mpc83xx/spi/mpc83xx_spidrv.c

    r8ac748c r42bf1b9  
    4242\*-------------------------------------------------------------------------*/
    4343 uint32_t baudrate,                      /* desired baudrate               */
     44 uint32_t base_frq,                      /* input frequency                */
    4445 uint32_t *spimode                       /* result value                   */
    4546)
     
    5455   * determine clock divider and DIV16 bit
    5556   */
    56   divider = (BSP_CSB_CLK_FRQ+baudrate-1)/baudrate;
     57  divider = (base_frq+baudrate-1)/baudrate;
    5758  if (divider > 64) {
    5859    tmpmode = MPC83XX_SPIMODE_DIV16;
     
    587588   */
    588589  if (rc == RTEMS_SUCCESSFUL) {
    589     rc = mpc83xx_spi_baud_to_mode(tfr_mode->baudrate,&spimode_baud);
     590    rc = mpc83xx_spi_baud_to_mode(tfr_mode->baudrate,
     591                                  softc_ptr->base_frq,
     592                                  &spimode_baud);
    590593  }
    591594  if (rc == RTEMS_SUCCESSFUL) {
  • c/src/lib/libcpu/powerpc/mpc83xx/spi/mpc83xx_spidrv.h

    r8ac748c r42bf1b9  
    3333  int                  initialized;
    3434  rtems_irq_number     irq_number;
     35  uint32_t             base_frq;    /* input frq for baud rate divider */
    3536  rtems_id             irq_sema_id;
    3637  uint32_t             curr_addr; /* current spi address */
  • c/src/libchip/Makefile.am

    r8ac748c r42bf1b9  
    7575if LIBCHIP
    7676include_libchip_HEADERS += i2c/i2c-ds1621.h i2c/i2c-2b-eeprom.h \
    77                            i2c/spi-flash-m25p40.h
     77                           i2c/spi-memdrv.h                     \
     78                           i2c/spi-flash-m25p40.h i2c/spi-fram-fm25l256.h
    7879
    7980noinst_LIBRARIES += libi2cio.a
     
    8182libi2cio_a_SOURCES  = i2c/i2c-ds1621.c i2c/i2c-2b-eeprom.c \
    8283    i2c/i2c-ds1621.h i2c/i2c-2b-eeprom.h \
    83     i2c/spi-flash-m25p40.c i2c/spi-flash-m25p40.h
     84    i2c/spi-memdrv.c i2c/spi-memdrv.h \
     85    i2c/spi-flash-m25p40.c i2c/spi-flash-m25p40.h \
     86    i2c/spi-fram-fm25l256.c i2c/spi-fram-fm25l256.h
    8487endif
    8588
  • c/src/libchip/i2c/spi-flash-m25p40.c

    r8ac748c r42bf1b9  
    1616+-----------------------------------------------------------------+
    1717\*===============================================================*/
    18 /*
    19  * FIXME: currently, this driver only supports read/write accesses
    20  * erase accesses are to be completed
    21  */
    22 
    2318
    2419#include <rtems.h>
     
    2823#include <rtems/libio.h>
    2924
    30 #define FLASH_M25P40_CMD_WREN  0x06
    31 #define FLASH_M25P40_CMD_WRDIS 0x04
    32 #define FLASH_M25P40_CMD_RDID  0x9F
    33 #define FLASH_M25P40_CMD_RDSR  0x05
    34 #define FLASH_M25P40_CMD_WRSR  0x01
    35 #define FLASH_M25P40_CMD_READ  0x03
    36 #define FLASH_M25P40_CMD_PP    0x02  /* page program                       */
    37 #define FLASH_M25P40_CMD_SE    0xD8  /* sector erase                       */
    38 #define FLASH_M25P40_CMD_BE    0xC7  /* bulk erase                         */
    39 #define FLASH_M25P40_CMD_DP    0xB9  /* deep power down                    */
    40 #define FLASH_M25P40_CMD_RES   0xAB  /* release from deep power down       */
    4125
    42 #define M25P40_PAGE_SIZE 256
    43 #define M25P40_TOTAL_SIZE (512*1024)
    44 
    45 const rtems_libi2c_tfr_mode_t spi_flash_m25p40_tfr_mode = {
    46   baudrate:      20000000, /* maximum bits per second                   */
    47   bits_per_char: 8,        /* how many bits per byte/word/longword?     */
    48   lsb_first:      FALSE,   /* FALSE: send MSB first                     */
    49   clock_inv:      FALSE,   /* FALSE: non-inverted clock (high active)   */
    50   clock_phs:      FALSE    /* FALSE: clock starts in middle of data tfr */
    51 } ;
    52 
    53 /*=========================================================================*\
    54 | Function:                                                                 |
    55 \*-------------------------------------------------------------------------*/
    56 rtems_status_code spi_flash_m25p40_wait_ms
    57 (
    58 /*-------------------------------------------------------------------------*\
    59 | Purpose:                                                                  |
    60 |   wait a certain interval given in ms                                     |
    61 +---------------------------------------------------------------------------+
    62 | Input Parameters:                                                         |
    63 \*-------------------------------------------------------------------------*/
    64  int ms                                  /* time to wait in milliseconds   */
    65 )
    66 /*-------------------------------------------------------------------------*\
    67 | Return Value:                                                             |
    68 |    o = ok or error code                                                   |
    69 \*=========================================================================*/
    70 {
    71   rtems_status_code          rc = RTEMS_SUCCESSFUL;
    72   rtems_interval ticks_per_second;
    73 
    74   rc = rtems_clock_get(RTEMS_CLOCK_GET_TICKS_PER_SECOND,&ticks_per_second);
    75   if (rc == RTEMS_SUCCESSFUL) {
    76     rc = rtems_task_wake_after(ticks_per_second * ms / 1000);
     26static spi_memdrv_t spi_flash_m25p40_rw_drv_t = {
     27  {/* public fields */
     28  ops:         &spi_memdrv_rw_ops, /* operations of general memdrv */
     29  size:        sizeof (spi_flash_m25p40_rw_drv_t),
     30  },
     31  { /* our private fields */
     32  baudrate:             2000000,
     33  erase_before_program: TRUE,
     34  empty_state:          0xff,
     35  page_size:            256, /* programming page size in byte */
     36  sector_size:          64*1024, /* erase sector size in byte */
     37  mem_size:             512*1024 /* total capacity in byte    */
    7738  }
    78   return rc;
    79 }
    80 
    81 /*=========================================================================*\
    82 | Function:                                                                 |
    83 \*-------------------------------------------------------------------------*/
    84 rtems_status_code spi_flash_m25p40_write
    85 (
    86 /*-------------------------------------------------------------------------*\
    87 | Purpose:                                                                  |
    88 |   write a block of data to flash                                          |
    89 +---------------------------------------------------------------------------+
    90 | Input Parameters:                                                         |
    91 \*-------------------------------------------------------------------------*/
    92  rtems_device_major_number major,        /* major device number            */
    93  rtems_device_major_number minor,        /* minor device number            */
    94  void                      *arg          /* ptr to write argument struct   */
    95 )
    96 /*-------------------------------------------------------------------------*\
    97 | Return Value:                                                             |
    98 |    o = ok or error code                                                   |
    99 \*=========================================================================*/
    100 {
    101   rtems_status_code          rc = RTEMS_SUCCESSFUL;
    102   rtems_libio_rw_args_t *rwargs = arg;
    103   unsigned                  off = rwargs->offset;
    104   int                       cnt = rwargs->count;
    105   unsigned char            *buf = (unsigned char *)rwargs->buffer;
    106   int                bytes_sent = 0;
    107   int                  curr_cnt;
    108   unsigned char       cmdbuf[4];
    109   int                   ret_cnt = 0;
    110   /*
    111    * check arguments
    112    */
    113   if (rc == RTEMS_SUCCESSFUL) {
    114     if ((cnt <= 0)                      ||
    115         (cnt > M25P40_TOTAL_SIZE)       ||
    116         (off > (M25P40_TOTAL_SIZE-cnt))) {
    117       rc = RTEMS_INVALID_SIZE;
    118     }
    119     else if (buf == NULL) {
    120       rc = RTEMS_INVALID_ADDRESS;
    121     }
    122   }
    123   /*
    124    * select device, set transfer mode, address device
    125    */
    126   if (rc == RTEMS_SUCCESSFUL) {
    127     rc = rtems_libi2c_send_start(minor);
    128   }
    129   /*
    130    * set transfer mode
    131    */
    132   if (rc == RTEMS_SUCCESSFUL) {
    133     rc = -rtems_libi2c_ioctl(minor,
    134                              RTEMS_LIBI2C_IOCTL_SET_TFRMODE,
    135                              &spi_flash_m25p40_tfr_mode);
    136   }
    137 
    138   /*
    139    * address device
    140    */
    141   if (rc == RTEMS_SUCCESSFUL) {
    142     rc = rtems_libi2c_send_addr(minor,TRUE);
    143   }
    144 
    145   /*
    146    * send write_enable command
    147    */
    148   if (rc == RTEMS_SUCCESSFUL) {
    149     cmdbuf[0] = FLASH_M25P40_CMD_WREN;
    150     ret_cnt = rtems_libi2c_write_bytes(minor,cmdbuf,1);
    151     if (ret_cnt < 0) {
    152       rc = -ret_cnt;
    153     }
    154   }
    155   /*
    156    * terminate transfer
    157    */
    158   if (rc == RTEMS_SUCCESSFUL) {
    159     rc = rtems_libi2c_send_stop(minor);
    160   }
    161   while ((rc == RTEMS_SUCCESSFUL) &&
    162          (cnt > bytes_sent)) {
    163     curr_cnt = cnt;
    164     if ((off              / M25P40_PAGE_SIZE) !=
    165         ((off+curr_cnt+1) / M25P40_PAGE_SIZE)) {
    166       curr_cnt = M25P40_PAGE_SIZE - (off % M25P40_PAGE_SIZE);
    167     }
    168     /*
    169      * select device, set transfer mode
    170      */
    171     if (rc == RTEMS_SUCCESSFUL) {
    172       rc = rtems_libi2c_send_start(minor);
    173     }
    174 
    175     /*
    176      * address device
    177      */
    178     if (rc == RTEMS_SUCCESSFUL) {
    179       rc = rtems_libi2c_send_addr(minor,TRUE);
    180     }
    181 
    182     /*
    183      * set transfer mode
    184      */
    185     if (rc == RTEMS_SUCCESSFUL) {
    186       rc = -rtems_libi2c_ioctl(minor,
    187                                RTEMS_LIBI2C_IOCTL_SET_TFRMODE,
    188                                &spi_flash_m25p40_tfr_mode);
    189     }
    190     /*
    191      * send "page program" command and address
    192      */
    193     if (rc == RTEMS_SUCCESSFUL) {
    194       cmdbuf[0] = FLASH_M25P40_CMD_PP;
    195       cmdbuf[1] = (off >> 16) & 0xff;
    196       cmdbuf[2] = (off >>  8) & 0xff;
    197       cmdbuf[3] = (off >>  0) & 0xff;
    198       ret_cnt = rtems_libi2c_write_bytes(minor,cmdbuf,4);
    199       if (ret_cnt < 0) {
    200         rc = -ret_cnt;
    201       }
    202     }
    203     /*
    204      * send write data
    205      */
    206     if (rc == RTEMS_SUCCESSFUL) {
    207       ret_cnt = rtems_libi2c_write_bytes(minor,buf,curr_cnt);
    208       if (ret_cnt < 0) {
    209         rc = -ret_cnt;
    210       }
    211     }
    212     /*
    213      * terminate transfer
    214      */
    215     if (rc == RTEMS_SUCCESSFUL) {
    216       rc = rtems_libi2c_send_stop(minor);
    217     }
    218     /*
    219      * wait proper time for data to store: 5ms
    220      */
    221     if (rc == RTEMS_SUCCESSFUL) {
    222       rc = spi_flash_m25p40_wait_ms(5);
    223     }
    224     /*
    225      * adjust bytecount to be sent and pointers
    226      */
    227     bytes_sent += curr_cnt;
    228     off        += curr_cnt;
    229     buf        += curr_cnt;
    230   }
    231   rwargs->bytes_moved = bytes_sent;
    232   return rc;
    233 }
    234 
    235 /*=========================================================================*\
    236 | Function:                                                                 |
    237 \*-------------------------------------------------------------------------*/
    238 rtems_status_code spi_flash_m25p40_read
    239 (
    240 /*-------------------------------------------------------------------------*\
    241 | Purpose:                                                                  |
    242 |   read a block of data from flash                                         |
    243 +---------------------------------------------------------------------------+
    244 | Input Parameters:                                                         |
    245 \*-------------------------------------------------------------------------*/
    246  rtems_device_major_number major,        /* major device number            */
    247  rtems_device_major_number minor,        /* minor device number            */
    248  void                      *arg          /* ptr to read argument struct    */
    249 )
    250 /*-------------------------------------------------------------------------*\
    251 | Return Value:                                                             |
    252 |    o = ok or error code                                                   |
    253 \*=========================================================================*/
    254 {
    255   rtems_status_code rc = RTEMS_SUCCESSFUL;
    256   rtems_libio_rw_args_t *rwargs = arg;
    257   unsigned                  off = rwargs->offset;
    258   int                       cnt = rwargs->count;
    259   unsigned char            *buf = (unsigned char *)rwargs->buffer;
    260   unsigned char       cmdbuf[4];
    261   int                   ret_cnt = 0;
    262   /*
    263    * check arguments
    264    */
    265   if (rc == RTEMS_SUCCESSFUL) {
    266     if ((cnt <= 0)                      ||
    267         (cnt > M25P40_TOTAL_SIZE)       ||
    268         (off > (M25P40_TOTAL_SIZE-cnt))) {
    269       rc = RTEMS_INVALID_SIZE;
    270     }
    271     else if (buf == NULL) {
    272       rc = RTEMS_INVALID_ADDRESS;
    273     }
    274   }
    275   /*
    276    * select device, set transfer mode, address device
    277    */
    278   if (rc == RTEMS_SUCCESSFUL) {
    279     rc = rtems_libi2c_send_start(minor);
    280   }
    281   /*
    282    * set transfer mode
    283    */
    284   if (rc == RTEMS_SUCCESSFUL) {
    285     rc = -rtems_libi2c_ioctl(minor,
    286                              RTEMS_LIBI2C_IOCTL_SET_TFRMODE,
    287                              &spi_flash_m25p40_tfr_mode);
    288   }
    289   /*
    290    * address device
    291    */
    292   if (rc == RTEMS_SUCCESSFUL) {
    293     rc = rtems_libi2c_send_addr(minor,TRUE);
    294   }
    295 
    296   if (off >= M25P40_TOTAL_SIZE) {
    297     /*
    298      * HACK: beyond size of Flash array? then read status register instead
    299      */
    300     /*
    301      * send read status register command
    302      */
    303     if (rc == RTEMS_SUCCESSFUL) {
    304       cmdbuf[0] = FLASH_M25P40_CMD_RDSR;
    305       ret_cnt = rtems_libi2c_write_bytes(minor,cmdbuf,1);
    306       if (ret_cnt < 0) {
    307         rc = -ret_cnt;
    308       }
    309     }
    310   }
    311   else {
    312     /*
    313      * send read command and address
    314      */
    315     if (rc == RTEMS_SUCCESSFUL) {
    316       cmdbuf[0] = FLASH_M25P40_CMD_READ;
    317       cmdbuf[1] = (off >> 16) & 0xff;
    318       cmdbuf[2] = (off >>  8) & 0xff;
    319       cmdbuf[3] = (off >>  0) & 0xff;
    320       ret_cnt = rtems_libi2c_write_bytes(minor,cmdbuf,4);
    321       if (ret_cnt < 0) {
    322         rc = -ret_cnt;
    323       }
    324     }
    325   }
    326   /*
    327    * fetch read data
    328    */
    329   if (rc == RTEMS_SUCCESSFUL) {
    330     ret_cnt = rtems_libi2c_read_bytes (minor,buf,cnt);
    331     if (ret_cnt < 0) {
    332       rc = -ret_cnt;
    333     }
    334   }
    335    
    336   /*
    337    * terminate transfer
    338    */
    339   if (rc == RTEMS_SUCCESSFUL) {
    340     rc = rtems_libi2c_send_stop(minor);
    341   }
    342   rwargs->bytes_moved = (rc == RTEMS_SUCCESSFUL) ? ret_cnt : 0;
    343 
    344   return rc;
    345 }
    346 
    347 static rtems_driver_address_table spi_flash_m25p40_rw_ops = {
    348   read_entry:  spi_flash_m25p40_read,
    349   write_entry: spi_flash_m25p40_write
    350 };
    351 
    352 static rtems_libi2c_drv_t spi_flash_m25p40_rw_drv_tbl = {
    353   ops:         &spi_flash_m25p40_rw_ops,
    354   size:        sizeof (spi_flash_m25p40_rw_drv_tbl),
    35539};
    35640
    35741rtems_libi2c_drv_t *spi_flash_m25p40_rw_driver_descriptor =
    358 &spi_flash_m25p40_rw_drv_tbl;
     42&spi_flash_m25p40_rw_drv_t.libi2c_drv_entry;
    35943
    360 static rtems_driver_address_table spi_flash_m25p40_ro_ops = {
    361   read_entry:  spi_flash_m25p40_read,
    362 };
    363 
    364 static rtems_libi2c_drv_t spi_flash_m25p40_ro_drv_tbl = {
    365   ops:         &spi_flash_m25p40_ro_ops,
    366   size:        sizeof (spi_flash_m25p40_ro_drv_tbl),
     44static spi_memdrv_t spi_flash_m25p40_ro_drv_t = {
     45  {/* public fields */
     46  ops:         &spi_memdrv_ro_ops, /* operations of general memdrv */
     47  size:        sizeof (spi_flash_m25p40_ro_drv_t),
     48  },
     49  { /* our private fields */
     50  baudrate:             2000000,
     51  erase_before_program: TRUE,
     52  empty_state:          0xff,
     53  page_size:            256, /* programming page size in byte */
     54  sector_size:          64*1024, /* erase sector size in byte */
     55  mem_size:             512*1024 /* total capacity in byte    */
     56  }
    36757};
    36858
    36959rtems_libi2c_drv_t *spi_flash_m25p40_ro_driver_descriptor =
    370 &spi_flash_m25p40_ro_drv_tbl;
     60&spi_flash_m25p40_ro_drv_t.libi2c_drv_entry;
  • c/src/libchip/i2c/spi-flash-m25p40.h

    r8ac748c r42bf1b9  
    2525#define _LIBCHIP_SPI_FLASH_M25P40_H
    2626
    27 #include <rtems/libi2c.h>
     27#include <libchip/spi-memdrv.h>
    2828
    2929#ifdef __cplusplus
  • c/src/libchip/preinstall.am

    r8ac748c r42bf1b9  
    126126PREINSTALL_FILES += $(PROJECT_INCLUDE)/libchip/i2c-2b-eeprom.h
    127127
     128$(PROJECT_INCLUDE)/libchip/spi-memdrv.h: i2c/spi-memdrv.h $(PROJECT_INCLUDE)/libchip/$(dirstamp)
     129        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libchip/spi-memdrv.h
     130PREINSTALL_FILES += $(PROJECT_INCLUDE)/libchip/spi-memdrv.h
     131
    128132$(PROJECT_INCLUDE)/libchip/spi-flash-m25p40.h: i2c/spi-flash-m25p40.h $(PROJECT_INCLUDE)/libchip/$(dirstamp)
    129133        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libchip/spi-flash-m25p40.h
    130134PREINSTALL_FILES += $(PROJECT_INCLUDE)/libchip/spi-flash-m25p40.h
     135
     136$(PROJECT_INCLUDE)/libchip/spi-fram-fm25l256.h: i2c/spi-fram-fm25l256.h $(PROJECT_INCLUDE)/libchip/$(dirstamp)
     137        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libchip/spi-fram-fm25l256.h
     138PREINSTALL_FILES += $(PROJECT_INCLUDE)/libchip/spi-fram-fm25l256.h
    131139endif
    132140if LIBCHIP
  • cpukit/ChangeLog

    r8ac748c r42bf1b9  
     12008-05-15      Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
     2
     3        * libi2c/libi2c.h, libi2c/libi2c.h: added interface to query
     4        driver private data
     5
    162008-05-13      Eric Norum: <norume@aps.anl.gov>
    27
  • cpukit/libi2c/libi2c.c

    r8ac748c r42bf1b9  
    577577  int sc = 0;
    578578  void *args;
     579  boolean is_started = FALSE;
    579580  DECL_CHECKED_BH (busno, bush, minor, -)
    580 
    581     if (not_started (busno))
    582     return -RTEMS_NOT_OWNER_OF_RESOURCE;
    583 
     581   
    584582  va_start(ap, cmd);
    585583  args = va_arg(ap, void *);
     
    590588     */
    591589   
     590  case RTEMS_LIBI2C_IOCTL_GET_DRV_T:
     591    /*
     592     * query driver table entry
     593     */
     594    *(rtems_libi2c_drv_t **)args = (drvs[MINOR2DRV(minor)-1].drv);
     595    break;
     596
    592597  case RTEMS_LIBI2C_IOCTL_START_TFM_READ_WRITE:
     598    if (not_started (busno))
     599      return -RTEMS_NOT_OWNER_OF_RESOURCE;
     600
    593601    /*
    594602     * address device, then set transfer mode and perform read_write transfer
     
    599607    if (sc == 0) {
    600608      sc = rtems_libi2c_send_start (minor);
     609      is_started = (sc == 0);
    601610    }
    602611    /*
     
    618627         &((rtems_libi2c_tfm_read_write_t *)args)->rd_wr);
    619628    }
     629    if ((sc < 0) && (is_started)) {
     630      rtems_libi2c_send_stop (minor);
     631    }
    620632    break;
    621633  default:
     
    623635    break;
    624636  }
    625   if (sc < 0)
    626     rtems_libi2c_send_stop (minor);
    627   return sc;
     637    return sc;
    628638}
    629639
  • cpukit/libi2c/libi2c.h

    r8ac748c r42bf1b9  
    414414 */
    415415
    416 /*
    417  * arguemtn data structures for IOCTLs defined above
     416#define RTEMS_LIBI2C_IOCTL_GET_DRV_T 4
     417/*
     418 * retval = rtems_libi2c_ioctl(rtems_device_minor_number minor,
     419 *                             RTEMS_LIBI2C_IOCTL_GET_DRV_T,
     420 *                             const rtems_libi2c_drv_t *drv_t_ptr);
     421 *
     422 * This call allows the a high-level driver to query its driver table entry,
     423 * including its private data appended to it during creation of the entry
     424 *
     425 */
     426
     427/*
     428 * argument data structures for IOCTLs defined above
    418429 */
    419430typedef struct {
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