Changeset 42b6dd2a in rtems


Ignore:
Timestamp:
May 5, 2009, 4:24:04 PM (10 years ago)
Author:
Jennifer Averett <Jennifer.Averett@…>
Branches:
4.10, 4.11, master
Children:
3776348f
Parents:
3c4d2451
Message:

2009-05-05 Jennifer Averett <jennifer.averett@…>

  • Makefile.am, configure.ac, preinstall.am, PCI_bus/PCI.c, PCI_bus/PCI.h, PCI_bus/flash.c, PCI_bus/universe.c, console/85c30.c, console/85c30.h, console/console.c, console/consolebsp.h, console/tbl85c30.c, include/bsp.h, include/gen2.h, include/irq-config.h, include/tm27.h, irq/FPGA.c, irq/irq.h, irq/irq_init.c, start/start.S, startup/Hwr_init.c, startup/bspstart.c, startup/linkcmds, timer/timer.c, tod/tod.c, vme/VMEConfig.h: Updated and tested with latest interrupt source. Modified with latest memory allocation, but this needs testing.
  • irq/no_pic.c: New file.
Location:
c/src/lib/libbsp/powerpc/score603e
Files:
1 added
27 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/score603e/ChangeLog

    r3c4d2451 r42b6dd2a  
     12009-05-05      Jennifer Averett <jennifer.averett@OARcorp.com>
     2
     3        * Makefile.am, configure.ac, preinstall.am, PCI_bus/PCI.c,
     4        PCI_bus/PCI.h, PCI_bus/flash.c, PCI_bus/universe.c, console/85c30.c,
     5        console/85c30.h, console/console.c, console/consolebsp.h,
     6        console/tbl85c30.c, include/bsp.h, include/gen2.h,
     7        include/irq-config.h, include/tm27.h, irq/FPGA.c, irq/irq.h,
     8        irq/irq_init.c, start/start.S, startup/Hwr_init.c,
     9        startup/bspstart.c, startup/linkcmds, timer/timer.c, tod/tod.c,
     10        vme/VMEConfig.h: Updated and tested with latest interrupt source.
     11        Modified with latest memory allocation, but this needs testing.
     12        * irq/no_pic.c: New file.
     13
    1142009-04-28      Chris Johns <chrisj@rtems.org>
    215
  • c/src/lib/libbsp/powerpc/score603e/Makefile.am

    r3c4d2451 r42b6dd2a  
    66
    77include $(top_srcdir)/../../../../automake/compile.am
    8 
    9 include_bspdir = $(includedir)/bsp
     8include $(top_srcdir)/../../bsp.am
    109
    1110dist_project_lib_DATA = bsp_specs
     
    1817DISTCLEANFILES = include/bspopts.h
    1918
     19include_bspdir = $(includedir)/bsp
     20
    2021include_HEADERS += ../../shared/tod.h
    2122include_HEADERS += ../../shared/include/coverhd.h include/gen2.h
     
    2425dist_project_lib_DATA += startup/linkcmds
    2526
    26 noinst_LIBRARIES = libbspstart.a
    27 libbspstart_a_SOURCES = start/start.S
    28 project_lib_DATA = start.$(OBJEXT)
     27startup_SOURCES = ../../shared/bspclean.c ../../shared/bsplibc.c \
     28    startup/bspstart.c ../../powerpc/shared/startup/bspgetworkarea.c \
     29    ../../shared/bsppost.c  \
     30    ../../shared/bootcard.c ../../shared/bsppretaskinghook.c \
     31    startup/Hwr_init.c \
     32    ../../powerpc/shared/startup/sbrk.c ../../shared/gnatinstallhandler.c \
     33    ../../powerpc/shared/showbats.c
    2934
    30 libbspstart_a_SOURCES += ../../powerpc/shared/start/rtems_crti.S
    31 project_lib_DATA += rtems_crti.$(OBJEXT)
    32 
    33 noinst_LIBRARIES += libbsp.a
    34 libbsp_a_SOURCES =
    35 
    36 # startup
    37 libbsp_a_SOURCES += ../../shared/bspclean.c ../../shared/bsplibc.c \
    38     startup/bspstart.c ../../powerpc/shared/startup/bspgetworkarea.c \
    39     ../../powerpc/shared/startup/sbrk.c ../../shared/bootcard.c \
    40     startup/Hwr_init.c startup/genpvec.c ../../shared/gnatinstallhandler.c \
    41     ../../powerpc/shared/showbats.c \
    42     ../../shared/bsppretaskinghook.c
    43 
    44 # pclock
    45 libbsp_a_SOURCES += ../../powerpc/shared/clock/p_clock.c
    46 # console
    47 libbsp_a_SOURCES += console/85c30.c console/85c30.h console/console.c \
     35pclock_SOURCES = ../../powerpc/shared/clock/p_clock.c
     36console_SOURCES = console/85c30.c console/85c30.h console/console.c \
    4837    console/tbl85c30.c console/consolebsp.h
    4938
    5039include_bsp_HEADERS = ../../powerpc/shared/pci/pci.h \
    51     PCI_bus/PCI.h ../../powerpc/shared/residual/residual.h \
    52     ../../powerpc/shared/residual/pnp.h \
    53     ../../powerpc/shared/console/consoleIo.h \
    54     ../../shared/include/irq-generic.h include/irq-config.h
    55 # pci
    56 libbsp_a_SOURCES += ../../powerpc/shared/pci/pci.c \
     40        PCI_bus/PCI.h \
     41        ../../powerpc/shared/residual/residual.h \
     42        ../../powerpc/shared/residual/pnp.h \
     43        ../../powerpc/shared/console/consoleIo.h
     44
     45pci_SOURCES = PCI_bus/flash.c ../../powerpc/shared/pci/pci.c \
    5746    ../../powerpc/shared/pci/pcifinddevice.c  PCI_bus/PCI.c  PCI_bus/universe.c
    5847
    5948include_bsp_HEADERS += irq/irq.h \
    60     ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/ppc_exc_bspsupp.h \
    61     ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h
    62 # irq
    63 libbsp_a_SOURCES += include/irq-config.h irq/FPGA.c irq/irq.c  \
    64     ../../shared/src/irq-generic.c ../../powerpc/shared/irq/irq_asm.S
     49        ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/ppc_exc_bspsupp.h \
     50        ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h \
     51        ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h
    6552
    66 include_bsp_HEADERS += ../../powerpc/shared/vectors/vectors.h
    67 # vectors
    68 libbsp_a_SOURCES += ../../powerpc/shared/vectors/vectors_init.c \
    69     ../../powerpc/shared/vectors/vectors.S
     53irq_SOURCES =  irq/no_pic.c irq/irq_init.c \
     54    irq/FPGA.c
    7055
    71 include_bsp_HEADERS += ../../shared/vmeUniverse/vmeUniverse.h \
    72     ../../shared/vmeUniverse/vme_am_defs.h \
    73     ../../shared/vmeUniverse/VME.h \
    74     vme/VMEConfig.h \
    75     ../../powerpc/shared/motorola/motorola.h \
    76     ../../shared/vmeUniverse/vmeUniverseDMA.h\
    77     ../../shared/vmeUniverse/bspVmeDmaList.h\
    78     ../../shared/vmeUniverse/VMEDMA.h
    79 # vme
    80 libbsp_a_SOURCES += \
    81     ../../shared/vmeUniverse/bspVmeDmaList.c \
    82     ../../shared/vmeUniverse/vme_am_defs.h \
    83         ../shared/vme/vmeconfig.c
     56vectors_SOURCES =
     57
     58EXTRA_DIST = start/start.S
     59start.$(OBJEXT): start/start.S
     60        $(CPPASCOMPILE) -o $@ -c $<
     61project_lib_DATA = start.$(OBJEXT)
     62
     63EXTRA_DIST += ../../powerpc/shared/start/rtems_crti.S
     64rtems_crti.$(OBJEXT): ../../powerpc/shared/start/rtems_crti.S
     65        $(CPPASCOMPILE) -o $@ -c $<
     66project_lib_DATA += rtems_crti.$(OBJEXT)
     67
     68noinst_LIBRARIES = libbsp.a
     69libbsp_a_SOURCES = $(pclock_SOURCES) $(console_SOURCES) $(irq_SOURCES) \
     70    $(pci_SOURCES) $(vectors_SOURCES) $(startup_SOURCES)
    8471
    8572libbsp_a_LIBADD = \
     
    8976    ../../../libcpu/@RTEMS_CPU@/mpc6xx/clock.rel \
    9077    ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
     78    ../../../libcpu/@RTEMS_CPU@/@exceptions@/irq_bspsupport.rel \
    9179    ../../../libcpu/@RTEMS_CPU@/@exceptions@/raw_exception.rel \
    9280     ../../../libcpu/@RTEMS_CPU@/mpc6xx/mmu.rel \
  • c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.c

    r3c4d2451 r42b6dd2a  
    11/*
    2  *  COPYRIGHT (c) 1989-2008
     2 *
     3 *  COPYRIGHT (c) 1989-2009.
    34 *  On-Line Applications Research Corporation (OAR).
    4  * 
     5 *
    56 *  The license and distribution terms for this file may be
    67 *  found in the file LICENSE in this distribution or at
  • c/src/lib/libbsp/powerpc/score603e/PCI_bus/PCI.h

    r3c4d2451 r42b6dd2a  
    1 /*
     1/*  PCI.h
     2 *
    23 *  This include file contains prototypes for chips attached to the
    34 *  PCI bus.
    45 *
    5  *  COPYRIGHT (c) 1989-2008.
     6 *  COPYRIGHT (c) 1989-2009.
    67 *  On-Line Applications Research Corporation (OAR).
    78 *
    8  *  The license and distribution terms for this file may in
    9  *  the file LICENSE in this distribution or at
     9 *  The license and distribution terms for this file may be
     10 *  found in the file LICENSE in this distribution or at
    1011 *  http://www.rtems.com/license/LICENSE.
    1112 *
    12  *  $Id$
     13 *  $Id:
    1314 */
    14 
    1515#ifndef __PCI_h
    1616#define __PCI_h
  • c/src/lib/libbsp/powerpc/score603e/PCI_bus/flash.c

    r3c4d2451 r42b6dd2a  
    11/*
    22 *
    3  *  COPYRIGHT (c) 1989-2008
     3 *  COPYRIGHT (c) 1989-2009.
    44 *  On-Line Applications Research Corporation (OAR).
    5  * 
     5 *
    66 *  The license and distribution terms for this file may be
    77 *  found in the file LICENSE in this distribution or at
     
    1414#include <assert.h>
    1515#include <stdio.h>
     16#include <inttypes.h>
    1617
    1718#include <bsp.h>
     19#include <bsp/irq.h>
    1820#include "PCI.h"
     21
    1922/*PAGE
    2023 *
     
    3538}
    3639
    37 unsigned int SCORE603e_FLASH_verify_enable()
     40unsigned int SCORE603e_FLASH_verify_enable( void )
    3841{
    3942  volatile uint8_t         *Ctrl_Status_Register =
     
    7881  value = Read_pci_device_register(  reg );
    7982  if (value != pci_value) {
    80     printf("Error PCI %x wrote %x read %x\n", reg, pci_value, value);
     83    printf("Error PCI 0x%2"PRIX8" wrote 0x%8"PRIX32" read %8"PRIX32"\n", reg, pci_value, value);
    8184  }
    8285  return RTEMS_SUCCESSFUL;
  • c/src/lib/libbsp/powerpc/score603e/PCI_bus/universe.c

    r3c4d2451 r42b6dd2a  
    11/*
    2  *  COPYRIGHT (c) 1989-2008
     2 *  COPYRIGHT (c) 1989-2009.
    33 *  On-Line Applications Research Corporation (OAR).
    4  * 
     4 *
    55 *  The license and distribution terms for this file may be
    66 *  found in the file LICENSE in this distribution or at
     
    230230 * Gets the VME base address
    231231 */
    232 uint32_t         get_vme_base_address ()
     232uint32_t         get_vme_base_address (void)
    233233{
    234234  volatile uint32_t         temp;
     
    239239}
    240240
    241 uint32_t         get_vme_slave_size()
     241uint32_t         get_vme_slave_size(void)
    242242{
    243243  volatile uint32_t         temp;
  • c/src/lib/libbsp/powerpc/score603e/configure.ac

    r3c4d2451 r42b6dd2a  
    3838[whether using console interrupts])
    3939
    40 RTEMS_BSPOPTS_SET([HAS_PMC_PSC8],[*],[1])
     40RTEMS_BSPOPTS_SET([HAS_PMC_PSC8],[*],[0])
    4141RTEMS_BSPOPTS_HELP([HAS_PMC_PSC8],
    4242[whether has a PSC8 PMC board attached to PMC slot])
     
    7070AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
    7171
    72 BSP_BOOTCARD_OPTIONS
    73 
    7472# Explicitly list all Makefiles here
    7573AC_CONFIG_FILES([Makefile])
  • c/src/lib/libbsp/powerpc/score603e/console/85c30.c

    r3c4d2451 r42b6dd2a  
    55 *  Currently only polled mode is supported.
    66 *
    7  *  COPYRIGHT (c) 1989-2008.
     7 *  COPYRIGHT (c) 1989-2009.
    88 *  On-Line Applications Research Corporation (OAR).
    99 *
     
    1111 *  found in the file LICENSE in this distribution or at
    1212 *  http://www.rtems.com/license/LICENSE.
    13  *
     13 * 
    1414 *  $Id$
    1515 */
     
    130130  uint16_t                baud_constant;
    131131
    132 printk("initialize_85c30_port start\n");
    133 
    134132  Setup = Port->Protocol;
    135133  ctrl  = Port->ctrl;
     
    156154   *  Set Write Register 2 to contain the interrupt vector
    157155   */
    158 printk("initialize_85c30_port 2, %d\n", Port->Chip->vector );
    159156  Write_85c30_register( ctrl, 2, Port->Chip->vector );
    160157#endif
     
    163160   *  Set Write Register 3 to disable the Receiver
    164161   */
    165 printk("initialize_85c30_port 0x03, 0x00\n");
    166162  Write_85c30_register( ctrl, 0x03, 0x00 );
    167163
     
    169165   *  Set Write Register 5 to disable the Transmitter
    170166   */
    171 printk("initialize_85c30_port 5, 0x00\n");
    172167  Write_85c30_register( ctrl, 5, 0x00 );
    173168
     
    179174   *  Set Write Register 9 to disable all interrupt sources
    180175   */
    181 printk("initialize_85c30_port 9, 0x00\n");
    182176  Write_85c30_register( ctrl, 9, 0x00 );
    183177
     
    185179   *  Set Write Register 10 for simple Asynchronous operation
    186180   */
    187 printk("initialize_85c30_port 0x0a, 0x00\n");
    188181  Write_85c30_register( ctrl, 0x0a, 0x00 );
    189182
     
    193186   * as the output source for TRxC pin via register 11
    194187   */
    195 printk("initialize_85c30_port 0x0b, 0x56\n");
    196188  Write_85c30_register( ctrl, 0x0b, 0x56 );
    197189
     
    203195   * baud rate will be equilvalent to 9600, via register 12.
    204196   */
    205 printk("initialize_85c30_port 0x0c, 0x%x\n", value & 0xff);
    206197  Write_85c30_register( ctrl, 0x0c, value & 0xff );
    207198
     
    210201   * Setup the upper 8 bits time constants = 0
    211202   */
    212 printk("initialize_85c30_port 0x0d, 0x%x\n", value>>8);
    213203  Write_85c30_register( ctrl, 0x0d, value>>8 );
    214204
     
    219209   * SCC's PCLK input via register 14.
    220210   */
    221 printk("initialize_85c30_port 0x0e, 0x07\n");
    222211  Write_85c30_register( ctrl, 0x0e, 0x07 );
    223212
     
    235224  value = value | Char_size_85c30[ Setup->read_char_bits ].read_setup;
    236225
    237 printk("initialize_85c30_port 0x03, 0x%x\n", value);
    238226  Write_85c30_register( ctrl, 0x03, value );
    239227
     
    250238  value = 0x8a;
    251239  value = value |  Char_size_85c30[ Setup->write_char_bits ].write_setup;
    252 printk("initialize_85c30_port 0x05, 0x%x\n", value);
    253240  Write_85c30_register( ctrl, 0x05, value );
    254241
     
    257244   * via register 0
    258245   */
    259 printk("initialize_85c30_port 0x00, 0xf0\n");
    260246   Write_85c30_register( ctrl, 0x00, 0xf0 );
    261247
     
    264250   *  Set Write Register 1 to interrupt on Rx characters or special condition.
    265251   */
    266 printk("initialize_85c30_port 1, 0x10\n");
    267252  Write_85c30_register( ctrl, 1, 0x10 );
    268253#endif
     
    272257   */
    273258
    274 printk("initialize_85c30_port 15, 0x00\n");
    275259  Write_85c30_register( ctrl, 15, 0x00 );
    276260
     
    278262   *  Set the Command Register to Reset Ext/STATUS.
    279263   */
    280 printk("initialize_85c30_port 0x00, 0x10\n");
    281264  Write_85c30_register( ctrl, 0x00, 0x10 );
    282265
     
    289272   *    Enables Tx interrupt.
    290273   */
    291 printk("initialize_85c30_port 1, 0x16\n");
    292274  Write_85c30_register( ctrl, 1, 0x16 );
    293275
     
    296278   *  Changed from 0 to a
    297279   */
    298 printk("initialize_85c30_port 9, 0x0A\n");
    299280  Write_85c30_register( ctrl, 9, 0x0A );
    300281
     
    304285   *  Issue reset highest Interrupt Under Service (IUS) command.
    305286   */
    306 printk("initialize_85c30_port STATUS_REGISTER, 0X38\n");
    307287  Write_85c30_register( Port->ctrl, STATUS_REGISTER, 0x38 );
    308288
    309289#endif
    310290
    311 printk("initialize_85c30_port end of method\n");
    312291}
    313292
  • c/src/lib/libbsp/powerpc/score603e/console/85c30.h

    r3c4d2451 r42b6dd2a  
    1 /*
     1/*  85c30.h
     2 *
    23 *  This include file contains z85c30 chip information.
    34 *
    4  *  COPYRIGHT (c) 1989-2008.
     5 *  COPYRIGHT (c) 1989-2009.
    56 *  On-Line Applications Research Corporation (OAR).
    67 *
    7  *  The license and distribution terms for this file may in
    8  *  the file LICENSE in this distribution or at
     8 *  The license and distribution terms for this file may be
     9 *  found in the file LICENSE in this distribution or at
    910 *  http://www.rtems.com/license/LICENSE.
    1011 *
  • c/src/lib/libbsp/powerpc/score603e/console/console.c

    r3c4d2451 r42b6dd2a  
    66 *  Currently only polled mode is supported.
    77 *
    8  *  COPYRIGHT (c) 1989-2008.
     8 *  COPYRIGHT (c) 1989-2009.
    99 *  On-Line Applications Research Corporation (OAR).
    1010 *
     
    182182  int                        port, chip, p0,p1;
    183183
    184 printk("console_initialize start\n");
    185 
    186184  /*
    187185   * initialize the termio interface.
     
    208206 */
    209207#if ( INITIALIZE_COM_PORTS )
    210 
    211208  /*
    212209   * Force to perform a hardware reset w/o
     
    240237  for (port=1; port<NUM_Z85C30_PORTS; port++) {
    241238   chip = port >> 1;
    242 printk("console_initialize initialize_85c30_port %d\n", port);
    243239    initialize_85c30_port( &Ports_85C30[port] );
    244240  }
    245241
    246242#if CONSOLE_USE_INTERRUPTS
    247 printk("console_initialize console_initialize_interrupts\n");
    248243  console_initialize_interrupts();
    249244#endif
    250245
    251 printk("console_initialize end\n");
    252246  return RTEMS_SUCCESSFUL;
    253247}
     
    421415    rtems_interrupt_disable( isrlevel );
    422416    outbyte_polled_85c30( csr, '\r' );
     417    asm volatile("isync");
    423418    rtems_interrupt_enable( isrlevel );
    424     asm volatile("isync");
    425419  }
    426420
    427421  rtems_interrupt_disable( isrlevel );
    428422  outbyte_polled_85c30( csr, c );
     423  asm volatile("isync");
    429424  rtems_interrupt_enable( isrlevel );
    430425}
  • c/src/lib/libbsp/powerpc/score603e/console/consolebsp.h

    r3c4d2451 r42b6dd2a  
    1 /*
     1/*  consolebsp.h
     2 *
    23 *  This include file contains all console driver definations
    34 *
    4  *  COPYRIGHT (c) 1989-2008.
     5 *  COPYRIGHT (c) 1989-2009.
    56 *  On-Line Applications Research Corporation (OAR).
    67 *
    7  *  The license and distribution terms for this file may in
    8  *  the file LICENSE in this distribution or at
     8 *  The license and distribution terms for this file may be
     9 *  found in the file LICENSE in this distribution or at
    910 *  http://www.rtems.com/license/LICENSE.
    1011 *
  • c/src/lib/libbsp/powerpc/score603e/console/tbl85c30.c

    r3c4d2451 r42b6dd2a  
    33 *  used by the console driver.
    44 *
    5  *  COPYRIGHT (c) 1989-2008.
     5 *  COPYRIGHT (c) 1989-2009.
    66 *  On-Line Applications Research Corporation (OAR).
    77 *
     
    1515#include "consolebsp.h"
    1616#include <bsp.h>
     17#include <bsp/irq.h>
    1718
    1819#define CONSOLE_DEFAULT_BAUD_RATE            9600
  • c/src/lib/libbsp/powerpc/score603e/include/bsp.h

    r3c4d2451 r42b6dd2a  
    1 /*
     1/*  bsp.h
     2 *
    23 *  This include file contains all board IO definitions.
    34 *
    4  *  COPYRIGHT (c) 1989-2008.
     5 *  COPYRIGHT (c) 1989-2009.
    56 *  On-Line Applications Research Corporation (OAR).
    67 *
    7  *  The license and distribution terms for this file may in
    8  *  the file LICENSE in this distribution or at
     8 *  The license and distribution terms for this file may be
     9 *  found in the file LICENSE in this distribution or at
    910 *  http://www.rtems.com/license/LICENSE.
    1011 *
     
    1819extern "C" {
    1920#endif
     21
     22#define BSP_ZERO_WORKSPACE_AUTOMATICALLY TRUE
    2023
    2124#include <bspopts.h>
     
    3538#define CONFIGURE_NUMBER_OF_TERMIOS_PORTS (4 + 4)
    3639#else
    37 /* XXXXX FIX THIS */
    38 #error "MUST HAVE PSC8 SET FOR BOEING CODE"
    3940#define CONFIGURE_NUMBER_OF_TERMIOS_PORTS (4)
    4041#endif
     
    5556
    5657#include <gen2.h>
     58#include <bsp/irq.h>
    5759
    5860/*
     
    8183
    8284
     85/* Constants */
     86
     87/*
     88 *  Device Driver Table Entries
     89 */
     90
     91/*
     92 * NOTE: Use the standard Console driver entry
     93 */
     94
     95/*
     96 * NOTE: Use the standard Clock driver entry
     97 */
     98
    8399/*
    84100 *  Information placed in the linkcmds file.
    85101 */
    86102
    87 extern void *RAM_END;
    88 extern void *end;
     103extern int   RAM_START;
     104extern int   RAM_END;
     105extern int   RAM_SIZE;
     106
     107extern int   PROM_START;
     108extern int   PROM_END;
     109extern int   PROM_SIZE;
    89110
    90111extern int   CLOCK_SPEED;
    91112extern int   CPU_PPC_CLICKS_PER_MS;
    92113
     114extern int   end;        /* last address in the program */
     115
    93116/*
    94117 * Total RAM available
    95118 */
    96 extern unsigned int BSP_mem_size;
     119extern int        end;        /* last address in the program */
     120extern int        RAM_END;
     121extern uint32_t   BSP_mem_size;
     122
     123
     124/*
     125 * How many libio files we want
     126 */
     127
     128#define BSP_LIBIO_MAX_FDS       20
    97129
    98130/* functions */
    99131
    100132/*
    101  * genvec.c
     133 *
    102134 */
    103135rtems_isr_entry  set_EE_vector(
     
    141173);
    142174
     175void mask_irq(
     176  uint16_t         irq_idx
     177);
     178
    143179void init_irq_data_register();
    144180
  • c/src/lib/libbsp/powerpc/score603e/include/gen2.h

    r3c4d2451 r42b6dd2a  
    1 /*
     1/*  Gen2.h
     2 *
    23 *  This include file contains all Generation 2 board addreses
    34 *
    4  *  COPYRIGHT (c) 1989-2008.
     5 *  COPYRIGHT (c) 1989-2009.
    56 *  On-Line Applications Research Corporation (OAR).
    67 *
    7  *  The license and distribution terms for this file may in
    8  *  the file LICENSE in this distribution or at
     8 *  The license and distribution terms for this file may be
     9 *  found in the file LICENSE in this distribution or at
    910 *  http://www.rtems.com/license/LICENSE.
    1011 *
     
    178179 */
    179180
    180 /*
    181  * First Score Unique IRQ
    182  */
    183 #define Score_IRQ_First ( PPC_IRQ_LAST +  1 )
    184 
    185 /*
    186  * The Following Are part of a Score603e FPGA.
    187  */
    188 #define SCORE603E_IRQ00   ( Score_IRQ_First +  0 )
    189 #define SCORE603E_IRQ01   ( Score_IRQ_First +  1 )
    190 #define SCORE603E_IRQ02   ( Score_IRQ_First +  2 )
    191 #define SCORE603E_IRQ03   ( Score_IRQ_First +  3 )
    192 #define SCORE603E_IRQ04   ( Score_IRQ_First +  4 )
    193 #define SCORE603E_IRQ05   ( Score_IRQ_First +  5 )
    194 #define SCORE603E_IRQ06   ( Score_IRQ_First +  6 )
    195 #define SCORE603E_IRQ07   ( Score_IRQ_First +  7 )
    196 #define SCORE603E_IRQ08   ( Score_IRQ_First +  8 )
    197 #define SCORE603E_IRQ09   ( Score_IRQ_First +  9 )
    198 #define SCORE603E_IRQ10   ( Score_IRQ_First + 10 )
    199 #define SCORE603E_IRQ11   ( Score_IRQ_First + 11 )
    200 #define SCORE603E_IRQ12   ( Score_IRQ_First + 12 )
    201 #define SCORE603E_IRQ13   ( Score_IRQ_First + 13 )
    202 #define SCORE603E_IRQ14   ( Score_IRQ_First + 14 )
    203 #define SCORE603E_IRQ15   ( Score_IRQ_First + 15 )
    204 
    205 #define SCORE603E_TIMER1_IRQ           SCORE603E_IRQ00
    206 #define SCORE603E_TIMER2_IRQ           SCORE603E_IRQ01
    207 #define SCORE603E_TIMER3_IRQ           SCORE603E_IRQ02
    208 #define SCORE603E_85C30_1_IRQ          SCORE603E_IRQ03
    209 #define SCORE603E_85C30_0_IRQ          SCORE603E_IRQ04
    210 #define SCORE603E_RTC_IRQ              SCORE603E_IRQ05
    211 #define SCORE603E_PCI_IRQ_0            SCORE603E_IRQ06
    212 #define SCORE603E_PCI_IRQ_1            SCORE603E_IRQ07
    213 #define SCORE603E_PCI_IRQ_2            SCORE603E_IRQ08
    214 #define SCORE603E_PCI_IRQ_3            SCORE603E_IRQ09
    215 #define SCORE603E_UNIVERSE_IRQ         SCORE603E_IRQ10
    216 #define SCORE603E_1553_IRQ             SCORE603E_IRQ11
    217 #define SCORE603E_MAIL_BOX_IRQ_0       SCORE603E_IRQ12
    218 #define SCORE603E_MAIL_BOX_IRQ_1       SCORE603E_IRQ13
    219 #define SCORE603E_MAIL_BOX_IRQ_2       SCORE603E_IRQ14
    220 #define SCORE603E_MAIL_BOX_IRQ_3       SCORE603E_IRQ15
    221 
    222 /*
    223  * The Score FPGA maps all interrupts comming from the PMC card to
    224  * the FPGA interrupt SCORE603E_PCI_IRQ_0 the PMC status word must be
    225  * read to indicate which interrupt was chained to the FPGA.
    226  */
    227 #define SCORE603E_IRQ16   ( Score_IRQ_First + 16 )
    228 #define SCORE603E_IRQ17   ( Score_IRQ_First + 17 )
    229 #define SCORE603E_IRQ18   ( Score_IRQ_First + 18 )
    230 #define SCORE603E_IRQ19   ( Score_IRQ_First + 19 )
    231 
    232 /*
    233  * IRQ'a read from the PMC card
    234  */
    235 #define SCORE603E_85C30_4_IRQ          SCORE603E_IRQ16    /* SCC 422-1 */
    236 #define SCORE603E_85C30_2_IRQ          SCORE603E_IRQ17    /* SCC 232-1 */
    237 #define SCORE603E_85C30_5_IRQ          SCORE603E_IRQ18    /* SCC 422-2 */
    238 #define SCORE603E_85C30_3_IRQ          SCORE603E_IRQ19    /* SCC 232-2 */
    239 
    240 #define MAX_BOARD_IRQS                 SCORE603E_IRQ19
    241181
    242182/*
     
    264204  (int) (((_value) * 4000) / 6667)
    265205
    266 #endif
    267 
    268206#ifdef __cplusplus
    269207}
    270208#endif
     209
     210#endif
     211
  • c/src/lib/libbsp/powerpc/score603e/include/irq-config.h

    r3c4d2451 r42b6dd2a  
    55 *
    66 * @brief BSP interrupt support configuration.
     7 *
     8 * $Id$
    79 */
    810
  • c/src/lib/libbsp/powerpc/score603e/include/tm27.h

    r3c4d2451 r42b6dd2a  
    11/*
    22 *  tm27.h
     3 *
     4 *  COPYRIGHT (c) 1989-2009.
     5 *  On-Line Applications Research Corporation (OAR).
    36 *
    47 *  The license and distribution terms for this file may be
  • c/src/lib/libbsp/powerpc/score603e/irq/FPGA.c

    r3c4d2451 r42b6dd2a  
    11/*  FPGA.c -- Bridge for second and subsequent generations
    22 *
    3  *  COPYRIGHT (c) 1989-2008.
     3 *  COPYRIGHT (c) 1989-2009.
    44 *  On-Line Applications Research Corporation (OAR).
    55 *
    6  *  The license and distribution terms for this file may in
    7  *  the file LICENSE in this distribution or at
     6 *  The license and distribution terms for this file may be
     7 *  found in the file LICENSE in this distribution or at
    88 *  http://www.rtems.com/license/LICENSE.
    99 *
     
    1212
    1313#include <bsp.h>
     14#include <bsp/irq.h>
    1415#include <string.h>
    1516#include <fcntl.h>
    1617#include <assert.h>
    1718
     19#include <rtems/libio.h>
     20#include <rtems/libcsupport.h>
    1821#include <rtems/bspIo.h>
    1922
     
    2629   *       change anything.
    2730   */
    28   printk("initialize_PCI_bridge: \n");
    2931}
    3032
     
    3335)
    3436{
    35   uint16_t          *loc;
     37  volatile uint16_t   *loc;
    3638
    3739  loc = (uint16_t*)SCORE603E_FPGA_MASK_DATA;
     
    4042}
    4143
    42 uint16_t         get_irq_mask(voi)
     44uint16_t get_irq_mask( void )
    4345{
    44   uint16_t          *loc;
    45   uint16_t          value;
     46  volatile uint16_t  *loc;
     47  uint16_t            value;
    4648
    4749  loc =  (uint16_t*)SCORE603E_FPGA_MASK_DATA;
     
    5052
    5153  return value;
     54}
     55
     56void mask_irq(
     57  uint16_t         irq_idx
     58)
     59{
     60  uint16_t         value;
     61  uint32_t         mask_idx = irq_idx;
     62
     63  value = get_irq_mask();
     64
     65#if (HAS_PMC_PSC8)
     66  switch (irq_idx + Score_IRQ_First ) {
     67    case SCORE603E_85C30_4_IRQ:
     68    case SCORE603E_85C30_2_IRQ:
     69    case SCORE603E_85C30_5_IRQ:
     70    case SCORE603E_85C30_3_IRQ:
     71      mask_idx = SCORE603E_PCI_IRQ_0 - Score_IRQ_First;
     72      break;
     73    default:
     74      break;
     75  }
     76#endif
     77
     78  value |= (0x1 << mask_idx);
     79  set_irq_mask( value );
    5280}
    5381
     
    99127)
    100128{
    101   uint16_t            status_word = irq;
     129  uint16_t   status_word = irq;
    102130
    103131  status_word = (*BSP_PMC_STATUS_ADDRESS);
     
    138166  uint16_t            irq;
    139167
     168
    140169  irq = (*SCORE603E_FPGA_VECT_DATA);
    141 
     170  Processor_Synchronize();
    142171  if ((irq & 0xffff0) != 0x10) {
    143     printk( "ERROR:: no irq data\n");
     172    printk( "read_and_clear_irq:: ERROR==>no irq data 0x%x\n", irq);
    144173    return (irq | 0x80);
    145174  }
    146175
    147176  irq &=0xf;
    148 
     177  irq += Score_IRQ_First;
    149178  return irq;
    150179}
  • c/src/lib/libbsp/powerpc/score603e/irq/irq.h

    r3c4d2451 r42b6dd2a  
    1 /*
     1/* irq.h
     2 *
    23 *  This include file describe the data structure and the functions implemented
    34 *  by RTEMS to write interrupt handlers.
    4  *
    5  *  Copyright (C) 1999 valette@crf.canon.fr
    65 *
    76 *  This code is heavilly inspired by the public specification of STREAM V2
    87 *  that can be found at :
    98 *
    10  *      <http://www.chorus.com/Documentation/index.html> by following
     9 *  <http://www.chorus.com/Documentation/index.html> by following
    1110 *  the STREAM API Specification Document link.
    1211 *
     12 *  COPYRIGHT (c) 1989-2009.
     13 *  On-Line Applications Research Corporation (OAR).
     14 *
    1315 *  The license and distribution terms for this file may be
    14  *  found in found in the file LICENSE in this distribution or at
     16 *  found in the file LICENSE in this distribution or at
    1517 *  http://www.rtems.com/license/LICENSE.
    1618 *
     
    2426#include <rtems/irq.h>
    2527
    26 /*
    27  * 8259 edge/level control definitions at VIA
    28  */
    29 #define ISA8259_M_ELCR          0x4d0
    30 #define ISA8259_S_ELCR          0x4d1
    31 
    32 #define ELCRS_INT15_LVL         0x80
    33 #define ELCRS_INT14_LVL         0x40
    34 #define ELCRS_INT13_LVL         0x20
    35 #define ELCRS_INT12_LVL         0x10
    36 #define ELCRS_INT11_LVL         0x08
    37 #define ELCRS_INT10_LVL         0x04
    38 #define ELCRS_INT9_LVL          0x02
    39 #define ELCRS_INT8_LVL          0x01
    40 #define ELCRM_INT7_LVL          0x80
    41 #define ELCRM_INT6_LVL          0x40
    42 #define ELCRM_INT5_LVL          0x20
    43 #define ELCRM_INT4_LVL          0x10
    44 #define ELCRM_INT3_LVL          0x8
    45 #define ELCRM_INT2_LVL          0x4
    46 #define ELCRM_INT1_LVL          0x2
    47 #define ELCRM_INT0_LVL          0x1
    48 
    49     /* PIC's command and mask registers */
    50 #define PIC_MASTER_COMMAND_IO_PORT              0x20    /* Master PIC command register */
    51 #define PIC_SLAVE_COMMAND_IO_PORT               0xa0    /* Slave PIC command register */
    52 #define PIC_MASTER_IMR_IO_PORT                  0x21    /* Master PIC Interrupt Mask Register */
    53 #define PIC_SLAVE_IMR_IO_PORT                   0xa1    /* Slave PIC Interrupt Mask Register */
    54 
    55     /* Command for specific EOI (End Of Interrupt): Interrupt acknowledge */
    56 #define PIC_EOSI        0x60    /* End of Specific Interrupt (EOSI) */
    57 #define SLAVE_PIC_EOSI  0x62    /* End of Specific Interrupt (EOSI) for cascade */
    58 #define PIC_EOI         0x20    /* Generic End of Interrupt (EOI) */
    59 
    6028#ifndef ASM
    6129
     
    6331extern "C" {
    6432#endif
     33
    6534
    6635/*
     
    7443#define BSP_ISA_IRQ_LOWEST_OFFSET       (0)
    7544#define BSP_ISA_IRQ_MAX_OFFSET          (BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1)
     45
    7646/*
    7747 * PCI IRQ handlers related definitions
    78  * CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE
    7948 */
    8049#define BSP_PCI_IRQ_NUMBER              (16)
    8150#define BSP_PCI_IRQ_LOWEST_OFFSET       (BSP_ISA_IRQ_NUMBER)
    8251#define BSP_PCI_IRQ_MAX_OFFSET          (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1)
     52
     53/*
     54 * PMC IRQ
     55 */
     56#define BSP_PMC_IRQ_NUMBER              (4)
     57#define BSP_PMC_IRQ_LOWEST_OFFSET       (BSP_PCI_IRQ_MAX_OFFSET + 1)
     58#define BSP_PMC_IRQ_MAX_OFFSET          (BSP_PMC_IRQ_LOWEST_OFFSET + BSP_PMC_IRQ_NUMBER - 1)
     59
     60
    8361/*
    8462 * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt
     
    8664 */
    8765#define BSP_PROCESSOR_IRQ_NUMBER        (1)
    88 #define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET + 1)
     66#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PMC_IRQ_MAX_OFFSET + 1)
    8967#define BSP_PROCESSOR_IRQ_MAX_OFFSET    (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1)
     68
    9069/* Misc vectors for OPENPIC irqs (IPI, timers)
    9170 */
     
    9978#define BSP_LOWEST_OFFSET               (BSP_ISA_IRQ_LOWEST_OFFSET)
    10079#define BSP_MAX_OFFSET                  (BSP_MISC_IRQ_MAX_OFFSET)
    101 /*
    102  * Some ISA IRQ symbolic name definition
    103  */
    104 #define BSP_ISA_PERIODIC_TIMER          (0)
    105 #define BSP_ISA_KEYBOARD                (1)
    106 #define BSP_ISA_UART_COM2_IRQ           (3)
    107 #define BSP_ISA_UART_COM1_IRQ           (4)
    108 #define BSP_ISA_RT_TIMER1               (8)
    109 #define BSP_ISA_RT_TIMER3               (10)
    110 /*
    111  * Some PCI IRQ symbolic name definition
    112  */
    113 #define BSP_PCI_IRQ0                    (BSP_PCI_IRQ_LOWEST_OFFSET)
    114 #define BSP_PCI_ISA_BRIDGE_IRQ          (BSP_PCI_IRQ0)
    115 
    116 #if defined(mvme2100)
    117 #define BSP_DEC21143_IRQ                (BSP_PCI_IRQ_LOWEST_OFFSET + 1)
    118 #define BSP_PMC_PCMIP_TYPE1_SLOT0_IRQ   (BSP_PCI_IRQ_LOWEST_OFFSET + 2)
    119 #define BSP_PCMIP_TYPE1_SLOT1_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 3)
    120 #define BSP_PCMIP_TYPE2_SLOT0_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 4)
    121 #define BSP_PCMIP_TYPE2_SLOT1_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 5)
    122 #define BSP_PCI_INTA_UNIVERSE_LINT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 7)
    123 #define BSP_PCI_INTB_UNIVERSE_LINT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 8)
    124 #define BSP_PCI_INTC_UNIVERSE_LINT2_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 9)
    125 #define BSP_PCI_INTD_UNIVERSE_LINT3_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 10)
    126 #define BSP_UART_COM1_IRQ               (BSP_PCI_IRQ_LOWEST_OFFSET + 13)
    127 #define BSP_FRONT_PANEL_ABORT_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 14)
    128 #define BSP_RTC_IRQ                     (BSP_PCI_IRQ_LOWEST_OFFSET + 15)
    129 #else
    130 #define BSP_UART_COM1_IRQ               BSP_ISA_UART_COM1_IRQ
    131 #define BSP_UART_COM2_IRQ               BSP_ISA_UART_COM2_IRQ
    132 #endif
    13380
    13481/*
     
    13784#define BSP_DECREMENTER                 (BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
    13885
     86/*
     87 * First Score Unique IRQ
     88 */
     89#define Score_IRQ_First ( BSP_PCI_IRQ_LOWEST_OFFSET )
    13990
    14091/*
    141  * Type definition for RTEMS managed interrupts
     92 * The Following Are part of a Score603e FPGA.
    14293 */
    143 typedef unsigned short rtems_i8259_masks;
     94#define SCORE603E_IRQ00   ( Score_IRQ_First +  0 )
     95#define SCORE603E_IRQ01   ( Score_IRQ_First +  1 )
     96#define SCORE603E_IRQ02   ( Score_IRQ_First +  2 )
     97#define SCORE603E_IRQ03   ( Score_IRQ_First +  3 )
     98#define SCORE603E_IRQ04   ( Score_IRQ_First +  4 )
     99#define SCORE603E_IRQ05   ( Score_IRQ_First +  5 )
     100#define SCORE603E_IRQ06   ( Score_IRQ_First +  6 )
     101#define SCORE603E_IRQ07   ( Score_IRQ_First +  7 )
     102#define SCORE603E_IRQ08   ( Score_IRQ_First +  8 )
     103#define SCORE603E_IRQ09   ( Score_IRQ_First +  9 )
     104#define SCORE603E_IRQ10   ( Score_IRQ_First + 10 )
     105#define SCORE603E_IRQ11   ( Score_IRQ_First + 11 )
     106#define SCORE603E_IRQ12   ( Score_IRQ_First + 12 )
     107#define SCORE603E_IRQ13   ( Score_IRQ_First + 13 )
     108#define SCORE603E_IRQ14   ( Score_IRQ_First + 14 )
     109#define SCORE603E_IRQ15   ( Score_IRQ_First + 15 )
    144110
    145 extern  volatile rtems_i8259_masks i8259s_cache;
    146 
    147 /*-------------------------------------------------------------------------+
    148 | Function Prototypes.
    149 +--------------------------------------------------------------------------*/
    150 /*
    151  * ------------------------ Intel 8259 (or emulation) Mngt Routines -------
    152  */
    153 void BSP_i8259s_init(void);
     111#define SCORE603E_TIMER1_IRQ           SCORE603E_IRQ00
     112#define SCORE603E_TIMER2_IRQ           SCORE603E_IRQ01
     113#define SCORE603E_TIMER3_IRQ           SCORE603E_IRQ02
     114#define SCORE603E_85C30_1_IRQ          SCORE603E_IRQ03
     115#define SCORE603E_85C30_0_IRQ          SCORE603E_IRQ04
     116#define SCORE603E_RTC_IRQ              SCORE603E_IRQ05
     117#define SCORE603E_PCI_IRQ_0            SCORE603E_IRQ06
     118#define SCORE603E_PCI_IRQ_1            SCORE603E_IRQ07
     119#define SCORE603E_PCI_IRQ_2            SCORE603E_IRQ08
     120#define SCORE603E_PCI_IRQ_3            SCORE603E_IRQ09
     121#define SCORE603E_UNIVERSE_IRQ         SCORE603E_IRQ10
     122#define SCORE603E_1553_IRQ             SCORE603E_IRQ11
     123#define SCORE603E_MAIL_BOX_IRQ_0       SCORE603E_IRQ12
     124#define SCORE603E_MAIL_BOX_IRQ_1       SCORE603E_IRQ13
     125#define SCORE603E_MAIL_BOX_IRQ_2       SCORE603E_IRQ14
     126#define SCORE603E_MAIL_BOX_IRQ_3       SCORE603E_IRQ15
    154127
    155128/*
    156  * function to disable a particular irq at 8259 level. After calling
    157  * this function, even if the device asserts the interrupt line it will
    158  * not be propagated further to the processor
    159  *
    160  * RETURNS: 1/0 if the interrupt was enabled/disabled originally or
    161  *          a value < 0 on error.
     129 * The Score FPGA maps all interrupts comming from the PMC card to
     130 * the FPGA interrupt SCORE603E_PCI_IRQ_0 the PMC status word must be
     131 * read to indicate which interrupt was chained to the FPGA.
    162132 */
    163 int BSP_irq_disable_at_i8259s        (const rtems_irq_number irqLine);
     133#define SCORE603E_IRQ16   ( Score_IRQ_First + 16 )
     134#define SCORE603E_IRQ17   ( Score_IRQ_First + 17 )
     135#define SCORE603E_IRQ18   ( Score_IRQ_First + 18 )
     136#define SCORE603E_IRQ19   ( Score_IRQ_First + 19 )
     137
    164138/*
    165  * function to enable a particular irq at 8259 level. After calling
    166  * this function, if the device asserts the interrupt line it will
    167  * be propagated further to the processor
     139 * IRQ'a read from the PMC card
    168140 */
    169 int BSP_irq_enable_at_i8259s            (const rtems_irq_number irqLine);
    170 /*
    171  * function to acknowledge a particular irq at 8259 level. After calling
    172  * this function, if a device asserts an enabled interrupt line it will
    173  * be propagated further to the processor. Mainly usefull for people
    174  * writing raw handlers as this is automagically done for RTEMS managed
    175  * handlers.
    176  */
    177 int BSP_irq_ack_at_i8259s               (const rtems_irq_number irqLine);
    178 /*
    179  * function to check if a particular irq is enabled at 8259 level. After calling
    180  */
    181 int BSP_irq_enabled_at_i8259s           (const rtems_irq_number irqLine);
     141#define SCORE603E_85C30_4_IRQ          SCORE603E_IRQ16    /* SCC 422-1 */
     142#define SCORE603E_85C30_2_IRQ          SCORE603E_IRQ17    /* SCC 232-1 */
     143#define SCORE603E_85C30_5_IRQ          SCORE603E_IRQ18    /* SCC 422-2 */
     144#define SCORE603E_85C30_3_IRQ          SCORE603E_IRQ19    /* SCC 232-2 */
    182145
    183 extern void BSP_rtems_irq_mng_init(unsigned cpuId);
    184 extern void BSP_i8259s_init(void);
    185 
    186 /* Stuff in irq_supp.h should eventually go into <rtems/irq.h> */
    187 /* #include <bsp/irq_supp.h> */
     146#define MAX_BOARD_IRQS                 SCORE603E_IRQ19
    188147
    189148#ifdef __cplusplus
    190 };
     149}
    191150#endif
    192151
  • c/src/lib/libbsp/powerpc/score603e/irq/irq_init.c

    r3c4d2451 r42b6dd2a  
    1 /*
     1/* irq_init.c
     2 *
    23 *  This file contains the implementation of rtems initialization
    34 *  related to interrupt handling.
     
    2223#include <bsp/pci.h>
    2324#include <bsp/residual.h>
    24 #include <bsp/openpic.h>
    2525#include <bsp/irq.h>
    2626#include <bsp.h>
    2727#include <libcpu/raw_exception.h>
    28 #include <bsp/motorola.h>
    2928#include <rtems/bspIo.h>
    3029
    3130#define SHOW_ISA_PCI_BRIDGE_SETTINGS 1
    3231#define SCAN_PCI_PRINT               1
    33 #define TRACE_IRQ_INIT               1
     32#define TRACE_IRQ_INIT               0
    3433
    3534typedef struct {
     
    4039
    4140pci_isa_bridge_device* via_82c586 = 0;
    42 static pci_isa_bridge_device bridge;
    4341
    4442extern unsigned int external_exception_vector_prolog_code_size[];
     
    4745extern void decrementer_exception_vector_prolog_code(void);
    4846
    49 /*
    50  * default on/off function
    51  */
    52 static void nop_func(void){}
    53 /*
    54  * default isOn function
    55  */
    56 static int not_connected(void) {return 0;}
    57 /*
    58  * default possible isOn function
    59  */
    60 static int connected(void) {return 1;}
     47static void IRQ_Default_rtems_irq_hdl( rtems_irq_hdl_param ptr ) {}
     48static void IRQ_Default_rtems_irq_enable (const struct __rtems_irq_connect_data__ *ptr){}
     49static void IRQ_Default_rtems_irq_disable(const struct __rtems_irq_connect_data__ *ptr){}
     50static int  IRQ_Default_rtems_irq_is_enabled(const struct __rtems_irq_connect_data__ *ptr){ return 1; }
    6151
    6252static rtems_irq_connect_data           rtemsIrq[BSP_IRQ_NUMBER];
    6353static rtems_irq_global_settings        initial_config;
     54
    6455static rtems_irq_connect_data           defaultIrq = {
    65   /* vectorIdex,         hdl            , handle        , on            , off           , isOn */
    66   0,                     nop_func       , NULL          , nop_func      , nop_func      , not_connected
    67 };
    68 static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER]={
    69   /*
    70    * actual priorities for interrupt :
    71    *    0   means that only current interrupt is masked
    72    *    255 means all other interrupts are masked
    73    */
    74   /*
    75    * ISA interrupts.
    76    * The second entry has a priority of 255 because
    77    * it is the slave pic entry and should always remain
    78    * unmasked.
    79    */
    80   0,0,
    81   255,
    82   0, 0, 0, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
    83   /*
    84    * PCI Interrupts
    85    */
    86   8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, /* for raven prio 0 means unactive... */
    87   /*
    88    * Processor exceptions handled as interrupts
    89    */
    90   0
     56/*name,  hdl                            handle  on                              off                             isOn */
     57  0,     IRQ_Default_rtems_irq_hdl,     NULL,   IRQ_Default_rtems_irq_enable,   IRQ_Default_rtems_irq_disable,  IRQ_Default_rtems_irq_is_enabled
    9158};
    9259
    93 #if defined(mvme2100)
    94 static unsigned char mvme2100_openpic_initpolarities[16] = {
    95     0,  /* Not used - should be disabled */
    96     0,  /* DEC21143 Controller */
    97     0,  /* PMC/PC-MIP Type I Slot 0 */
    98     0,  /* PC-MIP Type I Slot 1 */
    99     0,  /* PC-MIP Type II Slot 0 */
    100     0,  /* PC-MIP Type II Slot 1 */
    101     0,  /* Not used - should be disabled */
    102     0,  /* PCI Expansion Interrupt A/Universe II (LINT0) */
    103     0,  /* PCI Expansion Interrupt B/Universe II (LINT1) */
    104     0,  /* PCI Expansion Interrupt C/Universe II (LINT2) */
    105     0,  /* PCI Expansion Interrupt D/Universe II (LINT3) */
    106     0,  /* Not used - should be disabled */
    107     0,  /* Not used - should be disabled */
    108     1,  /* 16550 UART */
    109     0,  /* Front panel Abort Switch */
    110     0,  /* RTC IRQ */
    111 };
    112 
    113 static unsigned char mvme2100_openpic_initsenses[] = {
    114     0,  /* Not used - should be disabled */
    115     1,  /* DEC21143 Controller */
    116     1,  /* PMC/PC-MIP Type I Slot 0 */
    117     1,  /* PC-MIP Type I Slot 1 */
    118     1,  /* PC-MIP Type II Slot 0 */
    119     1,  /* PC-MIP Type II Slot 1 */
    120     0,  /* Not used - should be disabled */
    121     1,  /* PCI Expansion Interrupt A/Universe II (LINT0) */
    122     1,  /* PCI Expansion Interrupt B/Universe II (LINT1) */
    123     1,  /* PCI Expansion Interrupt C/Universe II (LINT2) */
    124     1,  /* PCI Expansion Interrupt D/Universe II (LINT3) */
    125     0,  /* Not used - should be disabled */
    126     0,  /* Not used - should be disabled */
    127     1,  /* 16550 UART */
    128     0,  /* Front panel Abort Switch */
    129     1,  /* RTC IRQ */
    130 };
    131 #else
    132 static unsigned char mcp750_openpic_initpolarities[16] = {
    133     1,  /* 8259 cascade */
    134     0,  /* all the rest of them */
    135 };
    136 
    137 static unsigned char mcp750_openpic_initsenses[] = {
    138     1,  /* MCP750_INT_PCB(8259) */
    139     0,  /* MCP750_INT_FALCON_ECC_ERR */
    140     1,  /* MCP750_INT_PCI_ETHERNET */
    141     1,  /* MCP750_INT_PCI_PMC */
    142     1,  /* MCP750_INT_PCI_WATCHDOG_TIMER1 */
    143     1,  /* MCP750_INT_PCI_PRST_SIGNAL */
    144     1,  /* MCP750_INT_PCI_FALL_SIGNAL */
    145     1,  /* MCP750_INT_PCI_DEG_SIGNAL */
    146     1,  /* MCP750_INT_PCI_BUS1_INTA */
    147     1,  /* MCP750_INT_PCI_BUS1_INTB */
    148     1,  /* MCP750_INT_PCI_BUS1_INTC */
    149     1,  /* MCP750_INT_PCI_BUS1_INTD */
    150     1,  /* MCP750_INT_PCI_BUS2_INTA */
    151     1,  /* MCP750_INT_PCI_BUS2_INTB */
    152     1,  /* MCP750_INT_PCI_BUS2_INTC */
    153     1,  /* MCP750_INT_PCI_BUS2_INTD */
    154 };
    155 #endif
    156 
    157 void VIA_isa_bridge_interrupts_setup(void)
    158 {
    159   pci_isa_bridge_device pci_dev;
    160   unsigned int temp;
    161   unsigned char tmp;
    162   unsigned char maxBus;
    163   unsigned found = 0;
    164 
    165   maxBus = pci_bus_count();
    166   pci_dev.function      = 0; /* Assumes the bidge is the first function */
    167 
    168   for (pci_dev.bus = 0; pci_dev.bus < maxBus; pci_dev.bus++) {
    169 #ifdef SCAN_PCI_PRINT
    170     printk("isa_bridge_interrupts_setup: Scanning bus %d\n", pci_dev.bus);
    171 #endif
    172     for (pci_dev.device = 0; pci_dev.device < PCI_MAX_DEVICES; pci_dev.device++) {
    173 #ifdef SCAN_PCI_PRINT
    174       printk("isa_bridge_interrupts_setup: Scanning device %d\n", pci_dev.device);
    175 #endif
    176       pci_read_config_dword(pci_dev.bus, pci_dev.device,  pci_dev.function,
    177                                PCI_VENDOR_ID, &temp);
    178 #ifdef SCAN_PCI_PRINT
    179       printk("Vendor/device = %x\n", temp);
    180 #endif
    181       if ((temp == (((unsigned short) PCI_VENDOR_ID_VIA) | (PCI_DEVICE_ID_VIA_82C586_0 << 16)))
    182          ) {
    183         bridge = pci_dev;
    184         via_82c586 = &bridge;
    185 #ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS
    186         /*
    187          * Should print : bus = 0, device = 11, function = 0 on a MCP750.
    188          */
    189         printk("Via PCI/ISA bridge found at bus = %d, device = %d, function = %d\n",
    190                via_82c586->bus,
    191                via_82c586->device,
    192                via_82c586->function);
    193 #endif
    194         found = 1;
    195         goto loop_exit;
    196 
    197       }
    198     }
    199   }
    200 loop_exit:
    201   if (!found) BSP_panic("VIA_82C586 PCI/ISA bridge not found!n");
    202 
    203   tmp = inb(0x810);
    204   if  ( !(tmp & 0x2)) {
    205 #ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS
    206     printk("This is a second generation MCP750 board\n");
    207     printk("We must reprogram the PCI/ISA bridge...\n");
    208 #endif
    209     pci_read_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function,
    210                          0x47,  &tmp);
    211 #ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS
    212     printk(" PCI ISA bridge control2 = %x\n", (unsigned) tmp);
    213 #endif
    214     /*
    215      * Enable 4D0/4D1 ISA interrupt level/edge config registers
    216      */
    217     tmp |= 0x20;
    218     pci_write_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function,
    219                           0x47, tmp);
    220     /*
    221      * Now program the ISA interrupt edge/level
    222      */
    223     tmp = ELCRS_INT9_LVL | ELCRS_INT10_LVL | ELCRS_INT11_LVL;
    224     outb(tmp, ISA8259_S_ELCR);
    225     tmp = ELCRM_INT5_LVL;
    226     outb(tmp, ISA8259_M_ELCR);;
    227     /*
    228      * Set the Interrupt inputs to non-inverting level interrupt
    229      */
    230     pci_read_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function,
    231                             0x54, &tmp);
    232 #ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS
    233     printk(" PCI ISA bridge PCI/IRQ Edge/Level Select = %x\n", (unsigned) tmp);
    234 #endif
    235     tmp = 0;
    236     pci_write_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function,
    237                           0x54, tmp);
    238   }
    239   else {
    240 #ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS
    241     printk("This is a first generation MCP750 board\n");
    242     printk("We just show the actual value used by PCI/ISA bridge\n");
    243 #endif
    244     pci_read_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function,
    245                          0x47,  &tmp);
    246 #ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS
    247     printk(" PCI ISA bridge control2 = %x\n", (unsigned) tmp);
    248 #endif
    249     /*
    250      * Show the Interrupt inputs inverting/non-inverting level status
    251      */
    252     pci_read_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function,
    253                          0x54, &tmp);
    254 #ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS
    255     printk(" PCI ISA bridge PCI/IRQ Edge/Level Select = %x\n", (unsigned) tmp);
    256 #endif
    257   }
    258 }
     60static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER];
    25961
    26062  /*
     
    26668void BSP_rtems_irq_mng_init(unsigned cpuId)
    26769{
    268 #if !defined(mvme2100)
    269   int known_cpi_isa_bridge = 0;
    270 #endif
    271   rtems_raw_except_connect_data vectorDesc;
    27270  int i;
    27371
     
    27573   * First initialize the Interrupt management hardware
    27674   */
    277 #if defined(mvme2100)
    278 #ifdef TRACE_IRQ_INIT
    279   printk("Going to initialize EPIC interrupt controller (openpic compliant)\n");
    280 #endif
    281   openpic_init(1, mvme2100_openpic_initpolarities, mvme2100_openpic_initsenses);
    282 #else
    283 #ifdef TRACE_IRQ_INIT
    284   printk("Going to initialize raven interrupt controller (openpic compliant)\n");
    285 #endif
    286   openpic_init(1, mcp750_openpic_initpolarities, mcp750_openpic_initsenses);
    287 #endif       
    288 
    289 #if !defined(mvme2100)
    290 #ifdef TRACE_IRQ_INIT 
    291   printk("Going to initialize the PCI/ISA bridge IRQ related setting (VIA 82C586)\n");
    292 #endif
    293   if ( currentBoard == MESQUITE ) {
    294     VIA_isa_bridge_interrupts_setup();
    295     known_cpi_isa_bridge = 1;
    296   }
    297   if ( currentBoard == MVME_2300 ) {
    298     /* nothing to do for W83C553 bridge */
    299     known_cpi_isa_bridge = 1;
    300   }
    301   if ( currentBoard == MTX_WO_PP || currentBoard == MTX_W_PP ) {
    302      /* W83C554, don't to anything at the moment.  gregm 11/6/2002 */
    303      known_cpi_isa_bridge = 1;
    304   }
    305 
    306   if (!known_cpi_isa_bridge) {
    307     printk("Please add code for PCI/ISA bridge init to libbsp/powerpc/shared/irq/irq_init.c\n");
    308     printk("If your card works correctly please add a test and set known_cpi_isa_bridge to true\n");
    309     printk("currentBoard = %i\n", currentBoard);
    310   }
    311 #ifdef TRACE_IRQ_INIT
    312   printk("Going to initialize the ISA PC legacy IRQ management hardware\n");
    313 #endif
    314   BSP_i8259s_init();
    315 #endif
    31675
    31776  /*
     
    32281     */
    32382    for (i = 0; i < BSP_IRQ_NUMBER; i++) {
     83      irqPrioTable[i]  = 8;
    32484      rtemsIrq[i]      = defaultIrq;
    32585      rtemsIrq[i].name = i;
     86#ifdef BSP_SHARED_HANDLER_SUPPORT
     87      rtemsIrq[i].next_handler = NULL;
     88#endif
    32689    }
     90
    32791    /*
    32892     * Init initial Interrupt management config
     
    341105    }
    342106
    343   /*
    344    * We must connect the raw irq handler for the two
    345    * expected interrupt sources : decrementer and external interrupts.
    346    */
    347     vectorDesc.exceptIndex      =       ASM_DEC_VECTOR;
    348     vectorDesc.hdl.vector       =       ASM_DEC_VECTOR;
    349     vectorDesc.hdl.raw_hdl      =       decrementer_exception_vector_prolog_code;
    350     vectorDesc.hdl.raw_hdl_size =       (unsigned) decrementer_exception_vector_prolog_code_size;
    351     vectorDesc.on               =       nop_func;
    352     vectorDesc.off              =       nop_func;
    353     vectorDesc.isOn             =       connected;
    354     if (!ppc_set_exception (&vectorDesc)) {
    355       BSP_panic("Unable to initialize RTEMS decrementer raw exception\n");
    356     }
    357     vectorDesc.exceptIndex      =       ASM_EXT_VECTOR;
    358     vectorDesc.hdl.vector       =       ASM_EXT_VECTOR;
    359     vectorDesc.hdl.raw_hdl      =       external_exception_vector_prolog_code;
    360     vectorDesc.hdl.raw_hdl_size =       (unsigned) external_exception_vector_prolog_code_size;
    361     if (!ppc_set_exception (&vectorDesc)) {
    362       BSP_panic("Unable to initialize RTEMS external raw exception\n");
    363     }
    364107#ifdef TRACE_IRQ_INIT
    365108    printk("RTEMS IRQ management is now operational\n");
  • c/src/lib/libbsp/powerpc/score603e/preinstall.am

    r3c4d2451 r42b6dd2a  
    2929PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp)
    3030
    31 $(PROJECT_INCLUDE)/bsp/$(dirstamp):
    32         @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp
    33         @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    34 PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    35 
    3631$(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp)
    3732        $(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs
     
    5449PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bootcard.h
    5550
     51$(PROJECT_INCLUDE)/bsp/$(dirstamp):
     52        @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp
     53        @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     54PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     55
    5656$(PROJECT_INCLUDE)/tod.h: ../../shared/tod.h $(PROJECT_INCLUDE)/$(dirstamp)
    5757        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tod.h
     
    6969        $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds
    7070PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds
    71 
    72 $(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
    73         $(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT)
    74 TMPINSTALL_FILES += $(PROJECT_LIB)/start.$(OBJEXT)
    75 
    76 $(PROJECT_LIB)/rtems_crti.$(OBJEXT): rtems_crti.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
    77         $(INSTALL_DATA) $< $(PROJECT_LIB)/rtems_crti.$(OBJEXT)
    78 TMPINSTALL_FILES += $(PROJECT_LIB)/rtems_crti.$(OBJEXT)
    7971
    8072$(PROJECT_INCLUDE)/bsp/pci.h: ../../powerpc/shared/pci/pci.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     
    9890PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/consoleIo.h
    9991
    100 $(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    101         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h
    102 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h
    103 
    104 $(PROJECT_INCLUDE)/bsp/irq-config.h: include/irq-config.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    105         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-config.h
    106 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-config.h
    107 
    10892$(PROJECT_INCLUDE)/bsp/irq.h: irq/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    10993        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
     
    11498PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/ppc_exc_bspsupp.h
    11599
     100$(PROJECT_INCLUDE)/bsp/vectors.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     101        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vectors.h
     102PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vectors.h
     103
    116104$(PROJECT_INCLUDE)/bsp/irq_supp.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    117105        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq_supp.h
    118106PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq_supp.h
    119107
    120 $(PROJECT_INCLUDE)/bsp/vectors.h: ../../powerpc/shared/vectors/vectors.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    121         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vectors.h
    122 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vectors.h
     108$(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
     109        $(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT)
     110TMPINSTALL_FILES += $(PROJECT_LIB)/start.$(OBJEXT)
    123111
    124 $(PROJECT_INCLUDE)/bsp/vmeUniverse.h: ../../shared/vmeUniverse/vmeUniverse.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    125         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vmeUniverse.h
    126 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vmeUniverse.h
     112$(PROJECT_LIB)/rtems_crti.$(OBJEXT): rtems_crti.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
     113        $(INSTALL_DATA) $< $(PROJECT_LIB)/rtems_crti.$(OBJEXT)
     114TMPINSTALL_FILES += $(PROJECT_LIB)/rtems_crti.$(OBJEXT)
    127115
    128 $(PROJECT_INCLUDE)/bsp/vme_am_defs.h: ../../shared/vmeUniverse/vme_am_defs.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    129         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vme_am_defs.h
    130 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vme_am_defs.h
    131 
    132 $(PROJECT_INCLUDE)/bsp/VME.h: ../../shared/vmeUniverse/VME.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    133         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/VME.h
    134 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/VME.h
    135 
    136 $(PROJECT_INCLUDE)/bsp/VMEConfig.h: vme/VMEConfig.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    137         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/VMEConfig.h
    138 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/VMEConfig.h
    139 
    140 $(PROJECT_INCLUDE)/bsp/motorola.h: ../../powerpc/shared/motorola/motorola.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    141         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/motorola.h
    142 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/motorola.h
    143 
    144 $(PROJECT_INCLUDE)/bsp/vmeUniverseDMA.h: ../../shared/vmeUniverse/vmeUniverseDMA.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    145         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vmeUniverseDMA.h
    146 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vmeUniverseDMA.h
    147 
    148 $(PROJECT_INCLUDE)/bsp/bspVmeDmaList.h: ../../shared/vmeUniverse/bspVmeDmaList.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    149         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bspVmeDmaList.h
    150 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bspVmeDmaList.h
    151 
    152 $(PROJECT_INCLUDE)/bsp/VMEDMA.h: ../../shared/vmeUniverse/VMEDMA.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    153         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/VMEDMA.h
    154 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/VMEDMA.h
    155 
  • c/src/lib/libbsp/powerpc/score603e/start/start.S

    r3c4d2451 r42b6dd2a  
    1818 */
    1919
    20 #warning Call to boot_card has changed and needs checking.
    21 #warning The call is "void boot_card(const char* cmdline);"
    22 #warning You need to pass a NULL.
    23 #warning Please check and remove these warnings.
    24        
    2520#include "ppc-asm.h"
    2621
  • c/src/lib/libbsp/powerpc/score603e/startup/Hwr_init.c

    r3c4d2451 r42b6dd2a  
    1 /*
    2  *  COPYRIGHT (c) 1989-2008.
     1/*  Hwr_init.c
     2 *
     3 *  COPYRIGHT (c) 1989-2009.
    34 *  On-Line Applications Research Corporation (OAR).
    45 *
     
    8990  /* DINK Monitor setsup and uses all 4 BAT registers.  */
    9091  /* The fourth BAT register can be modified to access this area */
    91 
    92   printk("init_PCI:\n");
    9392}
    9493
     
    115114  } while (0)
    116115
    117 void instruction_cache_enable ()
     116void instruction_cache_enable (void)
    118117{
    119118  uint32_t         value;
     
    130129}
    131130
    132 void data_cache_enable ()
     131void data_cache_enable (void)
    133132{
    134133  uint32_t         value;
  • c/src/lib/libbsp/powerpc/score603e/startup/bspstart.c

    r3c4d2451 r42b6dd2a  
    1 /*
     1/*  bspstart.c
     2 *
    23 *  This set of routines starts the application.  It includes application,
    34 *  board, and monitor specific initialization and configuration.
     
    56 *  before any of these are invoked.
    67 *
    7  *  COPYRIGHT (c) 1989-2008.
     8 *  COPYRIGHT (c) 1989-2009.
    89 *  On-Line Applications Research Corporation (OAR).
    910 *
    10  *  The license and distribution terms for this file may in
    11  *  the file LICENSE in this distribution or at
     11 *  The license and distribution terms for this file may be
     12 *  found in the file LICENSE in this distribution or at
    1213 *  http://www.rtems.com/license/LICENSE.
    1314 *
     
    1819
    1920#include <bsp.h>
     21#include <rtems/libio.h>
     22#include <rtems/libcsupport.h>
    2023#include <rtems/bspIo.h>
    21 #include <rtems/libio.h>
    2224#include <libcpu/cpuIdent.h>
    23 #define DEBUG 1
     25
     26#define DEBUG 0
    2427
    2528/*
     
    2932
    3033/*
    31  * Total RAM available and associated linker symbol
    32  */
    33 unsigned int BSP_mem_size;
    34 extern char  RamSize[];
    35 
    36 /*
    3734 * PCI Bus Frequency
    3835 */
    39 unsigned int BSP_bus_frequency;  /* XXX - Set this based upon the Score board */
     36unsigned int BSP_bus_frequency; 
    4037
    4138/*
    4239 * processor clock frequency
    4340 */
    44 unsigned int BSP_processor_frequency; /* XXX - Set this based upon the Score board */
     41unsigned int BSP_processor_frequency;
    4542
    4643/*
     
    4946unsigned int BSP_time_base_divisor = 4000;
    5047
     48/*
     49 *  Driver configuration parameters
     50 */
     51uint32_t   bsp_clicks_per_usec;
     52
     53/*
     54 * Memory on this board.
     55 */
     56extern char RamSize[];
     57uint32_t BSP_mem_size;
     58
    5159extern unsigned long __rtems_end[];
    52 
    53 /*
    54  *  Driver configuration parameters
    55  */
    56 uint32_t   bsp_clicks_per_usec;
    5760
    5861void BSP_panic(char *s)
     
    6972
    7073/*
     74 *  Use the shared implementations of the following routines
     75 */
     76
     77void bsp_libc_init( void *, uint32_t, int );
     78
     79/*PAGE
     80 *
    7181 *  bsp_predriver_hook
    7282 *
     
    7484 */
    7585
    76 void init_RTC();
    77 void initialize_PMC();
     86void init_RTC(void);
     87void initialize_PMC(void);
    7888
    7989void bsp_predriver_hook(void)
    8090{
     91  init_PCI();
     92  initialize_universe();
     93
     94  #if DEBUG
     95    printk("bsp_predriver_hook: initialize_PCI_bridge\n");
     96  #endif
     97  initialize_PCI_bridge ();
    8198
    8299#if (HAS_PMC_PSC8)
     
    98115 */
    99116
    100 void initialize_PMC() {
     117void initialize_PMC(void) {
    101118  volatile uint32_t     *PMC_addr;
    102119  uint32_t               data;
     
    132149/*PAGE
    133150 *
    134  *  bsp_postdriver_hook
    135  *
    136  *  Standard post driver hook plus some BSP specific stuff.
    137  */
    138 
    139 void bsp_postdriver_hook(void)
    140 {
    141   extern void Init_EE_mask_init(void);
    142   extern void open_dev_console(void);
    143 
    144   #if DEBUG
    145     printk("bsp_postdriver_hook: initialize libio\n");
    146   #endif
    147   if (rtems_libio_supp_helper)
    148     (*rtems_libio_supp_helper)();
    149   ShowBATS();
    150 
    151   #if DEBUG
    152     printk("bsp_postdriver_hook: Init_EE_mask_init\n");
    153   #endif
    154   Init_EE_mask_init();
    155   ShowBATS();
    156   #if DEBUG
    157     printk("bsp_postdriver_hook: Finished procedure\n");
    158   #endif
    159 }
    160 
    161 void bsp_set_trap_vectors( void );
    162 
    163 /*PAGE
    164  *
    165151 *  bsp_start
    166152 *
     
    170156void bsp_start( void )
    171157{
     158  unsigned char        *work_space_start;
    172159  unsigned int         msr_value = 0x0000;
    173160  uint32_t             intrStackStart;
    174161  uint32_t             intrStackSize;
    175   volatile uint32_t   *ptr;
     162  volatile uint32_t    *ptr;
    176163  ppc_cpu_id_t         myCpu;
    177164  ppc_cpu_revision_t   myCpuRevision;
    178  
     165
    179166  rtems_bsp_delay( 1000 );
    180167
     
    185172    printk("bsp_start: Zero out lots of memory\n");
    186173  #endif
    187 
    188   memset(
    189     &end,
    190     0,
    191     (unsigned char *)&RAM_END - (unsigned char *) &end
    192   );
    193174
    194175  BSP_processor_frequency = 266000000;
     
    210191  intrStackStart = (uint32_t) __rtems_end;
    211192  intrStackSize = rtems_configuration_get_interrupt_stack_size();
    212 
    213   BSP_heap_start = intrStackStart + intrStackSize;
    214   BSP_mem_size = (uintptr_t) RamSize;
     193  printk("Interrupt Stack Start: 0x%x Size: 0x%x  Heap Start: 0x%x\n",
     194    intrStackStart, intrStackSize, BSP_heap_start
     195  );
     196
     197  BSP_mem_size = RamSize;
     198  printk("BSP_mem_size: 0x%x\n", BSP_mem_size );
     199 
    215200
    216201  /*
     
    222207    intrStackSize
    223208  );
    224   #if DEBUG
    225     printk("bsp_predriver_hook: init_RTC\n");
    226   #endif
    227 
    228 /*   init_RTC(); */
    229   init_PCI();
    230   initialize_universe();
    231 
    232   #if DEBUG
    233     printk("bsp_predriver_hook: initialize_PCI_bridge\n");
    234   #endif
    235   initialize_PCI_bridge ();
    236209
    237210  msr_value = 0x2030;
    238211  _CPU_MSR_SET( msr_value );
    239 
    240 
    241   _CPU_MSR_SET( msr_value );
     212  asm volatile("sync; isync");
    242213
    243214  /*
     
    247218    printk("bsp_start: set clicks poer usec\n");
    248219  #endif
    249   bsp_clicks_per_usec = 66 / 4;  /* XXX get from linkcmds */
    250 
    251 #if ( PPC_USE_DATA_CACHE )
    252   #if DEBUG
    253     printk("bsp_start: cache_enable\n");
    254   #endif
    255   instruction_cache_enable ();
    256   data_cache_enable ();
    257   #if DEBUG
    258     printk("bsp_start: END PPC_USE_DATA_CACHE\n");
    259   #endif
    260 #endif
    261 
    262   /* Initalize interrupt support */
    263   if (bsp_interrupt_initialize() != RTEMS_SUCCESSFUL) {
    264     BSP_panic( "Cannot intitialize interrupt support\n");
    265   }
    266 
     220  bsp_clicks_per_usec = 66 / 4;
     221
     222  #if ( PPC_USE_DATA_CACHE )
     223    #if DEBUG
     224      printk("bsp_start: cache_enable\n");
     225    #endif
     226    instruction_cache_enable ();
     227    data_cache_enable ();
     228    #if DEBUG
     229      printk("bsp_start: END PPC_USE_DATA_CACHE\n");
     230    #endif
     231  #endif
     232
     233  /*
     234   * Initalize RTEMS IRQ system
     235   */
     236  #if DEBUG 
     237    printk("bspstart: Call BSP_rtems_irq_mng_init\n");
     238  #endif
     239  BSP_rtems_irq_mng_init(0);
     240 
    267241  #if DEBUG
    268242    printk("bsp_start: end BSPSTART\n");
    269   ShowBATS();
    270   #endif
    271 }
     243    ShowBATS();
     244  #endif
     245}
  • c/src/lib/libbsp/powerpc/score603e/startup/linkcmds

    r3c4d2451 r42b6dd2a  
    178178  PROVIDE (RAM_END = ADDR(.text) + 10M);
    179179  . =  ALIGN(8) + 0x1000;
    180   PROVIDE (__SBSS_START__ = .);
    181180  .sbss      :
    182181  {
     
    187186    PROVIDE (__sbss_end = .);
    188187  } >RAM
    189   PROVIDE (__SBSS_END__ = .);
    190188  .bss       :
    191189  {
     
    194192    *(.bss .bss* .gnu.linkonce.b*)
    195193    *(COMMON)
    196     . =  ALIGN(8) + 0x8000;
    197     PROVIDE (__stack = .);
    198     _end = . ;
    199     __rtems_end = . ;
    200     PROVIDE (end = .);
    201   } >RAM
     194  }  >RAM
     195  . = ALIGN(16) + 0x8000;
     196  PROVIDE (__stack = .);
     197  __rtems_end = . ;
     198  . =  ALIGN(8) + 0x8000;
     199  PROVIDE(_end = .);
     200  PROVIDE(end = .);
    202201
    203202  /* These are needed for ELF backends which have not yet been
  • c/src/lib/libbsp/powerpc/score603e/timer/timer.c

    r3c4d2451 r42b6dd2a  
    1 /*
     1/*  timer.c
     2 *
    23 *  This file implements a benchmark timer using the General Purpose Timer.
    34 *
     
    78 *  provided in bsp.h
    89 *
    9  *  COPYRIGHT (c) 1989-2008.
     10 *  COPYRIGHT (c) 1989-2009.
    1011 *  On-Line Applications Research Corporation (OAR).
    1112 *
    12  *  The license and distribution terms for this file may in
    13  *  the file LICENSE in this distribution or at
     13 *  The license and distribution terms for this file may be
     14 *  found in the file LICENSE in this distribution or at
    1415 *  http://www.rtems.com/license/LICENSE.
    1516 *
  • c/src/lib/libbsp/powerpc/score603e/tod/tod.c

    r3c4d2451 r42b6dd2a  
    11/*
    2  *  Real Time Clock (Harris ICM7170) for RTEMS
     2 * Real Time Clock (Harris ICM7170) for RTEMS
    33 *
    44 *  This part is found on the second generation of this board.
    55 *
    6  *  COPYRIGHT (c) 1989-2008.
     6 *  COPYRIGHT (c) 1989-2009.
    77 *  On-Line Applications Research Corporation (OAR).
    88 *
  • c/src/lib/libbsp/powerpc/score603e/vme/VMEConfig.h

    r3c4d2451 r42b6dd2a  
    11#ifndef RTEMS_BSP_VME_CONFIG_H
    22#define RTEMS_BSP_VME_CONFIG_H
    3 
    43/* $Id$ */
    54
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