Changeset 42540ecd in rtems
- Timestamp:
- 03/30/04 11:46:13 (20 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- 9a26317
- Parents:
- 16ce0e70
- Location:
- cpukit/score/cpu/or32
- Files:
-
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
cpukit/score/cpu/or32/ChangeLog
r16ce0e70 r42540ecd 1 2004-03-30 Ralf Corsepius <ralf_corsepius@rtems.org> 2 3 * cpu.c, cpu_asm.c, rtems/score/cpu.h: Convert to using c99 fixed 4 size types. 5 1 6 2004-03-29 Ralf Corsepius <ralf_corsepius@rtems.org> 2 7 -
cpukit/score/cpu/or32/cpu.c
r16ce0e70 r42540ecd 73 73 */ 74 74 75 inline u nsigned32_CPU_ISR_Get_level( void )75 inline uint32_t _CPU_ISR_Get_level( void ) 76 76 { 77 register u nsigned32sr;77 register uint32_t sr; 78 78 asm("l.mfspr %0,r0,0x17" : "=r" (sr)); 79 79 return !((sr & SR_EXR) && (sr & SR_EIR)); … … 94 94 95 95 void _CPU_ISR_install_raw_handler( 96 u nsigned32vector,96 uint32_t vector, 97 97 proc_ptr new_handler, 98 98 proc_ptr *old_handler 99 99 ) 100 100 { 101 register u nsigned32sr;102 register u nsigned32tmp;103 extern u nsigned32Or1k_Interrupt_Vectors[];101 register uint32_t sr; 102 register uint32_t tmp; 103 extern uint32_t Or1k_Interrupt_Vectors[]; 104 104 105 105 asm volatile ("l.mfspr %0,r0,0x11\n\t" … … 132 132 133 133 void _CPU_ISR_install_vector( 134 u nsigned32vector,134 uint32_t vector, 135 135 proc_ptr new_handler, 136 136 proc_ptr *old_handler -
cpukit/score/cpu/or32/cpu_asm.c
r16ce0e70 r42540ecd 77 77 ) 78 78 { 79 register u nsigned32temp;80 register u nsigned32 address = (unsigned32)(*fp_context_ptr);81 register u nsigned32xfer;82 register u nsigned32loop;79 register uint32_t temp; 80 register uint32_t address = (uint32_t )(*fp_context_ptr); 81 register uint32_t xfer; 82 register uint32_t loop; 83 83 84 84 /* %0 is a temporary register which is used for several … … 135 135 ) 136 136 { 137 register u nsigned32temp;138 register u nsigned32 address = (unsigned32)(*fp_context_ptr);139 register u nsigned32xfer;140 register u nsigned32loop;137 register uint32_t temp; 138 register uint32_t address = (uint32_t )(*fp_context_ptr); 139 register uint32_t xfer; 140 register uint32_t loop; 141 141 142 142 /* The reverse of Context_save_fp */ … … 194 194 ) 195 195 { 196 register u nsigned32temp1 = 0;197 register u nsigned32temp2 = 0;196 register uint32_t temp1 = 0; 197 register uint32_t temp2 = 0; 198 198 199 199 /* This function is really tricky. When this function is called, … … 499 499 */ 500 500 501 void _ISR_Handler(u nsigned32 vector,unsigned32ProgramCounter,502 u nsigned32 EffectiveAddress,unsigned32StatusRegister)501 void _ISR_Handler(uint32_t vector,uint32_t ProgramCounter, 502 uint32_t EffectiveAddress,uint32_t StatusRegister) 503 503 { 504 504 /* -
cpukit/score/cpu/or32/rtems/score/cpu.h
r16ce0e70 r42540ecd 377 377 378 378 #ifdef OR1K_64BIT_ARCH 379 #define or1kreg u nsigned64379 #define or1kreg uint64_t 380 380 #else 381 #define or1kreg u nsigned32381 #define or1kreg uint32_t 382 382 #endif 383 383 … … 434 434 435 435 typedef struct { 436 u nsigned32sr; /* Current status register non persistent values */437 u nsigned32esr; /* Saved exception status register */438 u nsigned32ear; /* Saved exception effective address register */439 u nsigned32epc; /* Saved exception PC register */436 uint32_t sr; /* Current status register non persistent values */ 437 uint32_t esr; /* Saved exception status register */ 438 uint32_t ear; /* Saved exception effective address register */ 439 uint32_t epc; /* Saved exception PC register */ 440 440 or1kreg r[31]; /* Registers */ 441 441 or1kreg pc; /* Context PC 4 or 8 bytes for 64 bit alignment */ … … 460 460 void (*idle_task)( void ); 461 461 boolean do_zero_of_workspace; 462 u nsigned32idle_task_stack_size;463 u nsigned32interrupt_stack_size;464 u nsigned32extra_mpci_receive_server_stack;465 void * (*stack_allocate_hook)( u nsigned32);462 uint32_t idle_task_stack_size; 463 uint32_t interrupt_stack_size; 464 uint32_t extra_mpci_receive_server_stack; 465 void * (*stack_allocate_hook)( uint32_t ); 466 466 void (*stack_free_hook)( void* ); 467 467 /* end of fields required on all CPUs */ … … 692 692 } 693 693 694 u nsigned32_CPU_ISR_Get_level( void );694 uint32_t _CPU_ISR_Get_level( void ); 695 695 696 696 /* end of ISR handler macros */ … … 724 724 { \ 725 725 memset(_the_context,'\0',sizeof(Context_Control)); \ 726 (_the_context)->r[1] = (u nsigned32*) ((unsigned32) (_stack_base) + (_size) ); \727 (_the_context)->r[2] = (u nsigned32*) ((unsigned32) (_stack_base)); \726 (_the_context)->r[1] = (uint32_t *) ((uint32_t ) (_stack_base) + (_size) ); \ 727 (_the_context)->r[2] = (uint32_t *) ((uint32_t ) (_stack_base)); \ 728 728 (_the_context)->sr = (_isr) ? 0x0000001B : 0x0000001F; \ 729 (_the_context)->pc = (u nsigned32*) _entry_point ; \729 (_the_context)->pc = (uint32_t *) _entry_point ; \ 730 730 } 731 731 … … 929 929 930 930 void _CPU_ISR_install_raw_handler( 931 u nsigned32vector,931 uint32_t vector, 932 932 proc_ptr new_handler, 933 933 proc_ptr *old_handler … … 945 945 946 946 void _CPU_ISR_install_vector( 947 u nsigned32vector,947 uint32_t vector, 948 948 proc_ptr new_handler, 949 949 proc_ptr *old_handler … … 1051 1051 ) 1052 1052 { 1053 u nsigned32byte1, byte2, byte3, byte4, swapped;1053 uint32_t byte1, byte2, byte3, byte4, swapped; 1054 1054 1055 1055 byte4 = (value >> 24) & 0xff;
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