Changeset 418899d in rtems for c/src/lib/libbsp/mips/csb350


Ignore:
Timestamp:
May 10, 2005, 6:27:31 AM (15 years ago)
Author:
Ralf Corsepius <ralf.corsepius@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
9f8023a2
Parents:
1e38faf
Message:

Eliminate unsigned{8|16|32}.

Location:
c/src/lib/libbsp/mips/csb350
Files:
5 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/mips/csb350/clock/clockdrv.c

    r1e38faf r418899d  
    1919#include <rtems/bspIo.h>
    2020
    21 unsigned32 tick_interval;
    22 unsigned32 last_match;
     21uint32_t tick_interval;
     22uint32_t last_match;
    2323
    2424#define CLOCK_VECTOR AU1X00_IRQ_TOY_MATCH2
     
    4646void au1x00_clock_init(void)
    4747{
    48     unsigned32 wakemask;
     48    uint32_t wakemask;
    4949    /* Clear the trim register */
    5050    AU1X00_SYS_TOYTRIM(AU1X00_SYS_ADDR) = 0;
  • c/src/lib/libbsp/mips/csb350/include/bsp.h

    r1e38faf r418899d  
    4343 *  Define the interrupt mechanism for Time Test 27
    4444 */
    45 int assert_sw_irw(unsigned32 irqnum);
    46 int negate_sw_irw(unsigned32 irqnum);
     45int assert_sw_irw(uint32_t irqnum);
     46int negate_sw_irw(uint32_t irqnum);
    4747
    4848#define MUST_WAIT_FOR_INTERRUPT 0
  • c/src/lib/libbsp/mips/csb350/network/network.c

    r1e38faf r418899d  
    9595     * register addresses
    9696     */
    97     unsigned32                      ctrl_regs;
    98     unsigned32                     *en_reg;
    99     unsigned32                      int_mask;
    100     unsigned32                      int_ctrlr;
     97    uint32_t                      ctrl_regs;
     98    uint32_t                     *en_reg;
     99    uint32_t                      int_mask;
     100    uint32_t                      int_ctrlr;
    101101
    102102    /*
     
    148148void au1x00_emac_stats (au1x00_emac_softc_t *sc);
    149149static int au1x00_emac_ioctl (struct ifnet *ifp, int command, caddr_t data);
    150 static void mii_write(au1x00_emac_softc_t *sc, unsigned8 reg, unsigned16 val);
    151 static void mii_read(au1x00_emac_softc_t *sc, unsigned8 reg, unsigned16 *val);
     150static void mii_write(au1x00_emac_softc_t *sc, uint8_t reg, uint16_t val);
     151static void mii_read(au1x00_emac_softc_t *sc, uint8_t reg, uint16_t *val);
    152152static void mii_init(au1x00_emac_softc_t *sc);
    153153
    154 static void mii_write(au1x00_emac_softc_t *sc, unsigned8 reg, unsigned16 val)
     154static void mii_write(au1x00_emac_softc_t *sc, uint8_t reg, uint16_t val)
    155155{
    156156    /* wait for the interface to get unbusy */
     
    171171}
    172172
    173 static void mii_read(au1x00_emac_softc_t *sc, unsigned8 reg, unsigned16 *val)
     173static void mii_read(au1x00_emac_softc_t *sc, uint8_t reg, uint16_t *val)
    174174{
    175175    /* wait for the interface to get unbusy */
     
    191191static void mii_init(au1x00_emac_softc_t *sc)
    192192{
    193     unsigned16 data;
     193    uint16_t data;
    194194
    195195    mii_write(sc, 0, 0x8000);     /* reset */
     
    459459         * boundary.
    460460         */
    461         if (mtod(m, unsigned32) & 0x1f) {
    462           unsigned32 *p = mtod(m, unsigned32 *);
    463           *p = (mtod(m, unsigned32) + 0x1f) & 0x1f;
     461        if (mtod(m, uint32_t) & 0x1f) {
     462          uint32_t *p = mtod(m, uint32_t *);
     463          *p = (mtod(m, uint32_t) + 0x1f) & 0x1f;
    464464        }
    465         sc->rx_dma[i].addr = (mtod(m, unsigned32) & ~0xe0000000);
     465        sc->rx_dma[i].addr = (mtod(m, uint32_t) & ~0xe0000000);
    466466        sc->rx_mbuf[i] = m;
    467467    }
     
    522522    struct mbuf *m;
    523523    rtems_event_set events;
    524     unsigned32 ic_base;     /* interrupt controller */
     524    uint32_t ic_base;     /* interrupt controller */
    525525
    526526    ic_base = AU1X00_IC0_ADDR;
     
    567567    struct ether_header *eh;
    568568    rtems_event_set events;
    569     unsigned32 status;
     569    uint32_t status;
    570570
    571571    while (1) {
     
    656656                 */
    657657                {
    658                   unsigned32 *p = mtod(m, unsigned32 *);
    659                   *p = (mtod(m, unsigned32) + 0x1f) & ~0x1f;
     658                  uint32_t *p = mtod(m, uint32_t *);
     659                  *p = (mtod(m, uint32_t) + 0x1f) & ~0x1f;
    660660                }
    661661           
     
    668668           
    669669            /* set up the receive dma to use the mbuf's cluster */
    670             sc->rx_dma[sc->rx_head].addr = (mtod(m, unsigned32) & ~0xe0000000);
     670            sc->rx_dma[sc->rx_head].addr = (mtod(m, uint32_t) & ~0xe0000000);
    671671            au_sync();
    672672            sc->rx_mbuf[sc->rx_head] = m;
     
    691691    unsigned int pkt_offset = 0;
    692692    au1x00_emac_softc_t *sc = (au1x00_emac_softc_t *)ifp->if_softc;
    693     unsigned32 txbuf;
     693    uint32_t txbuf;
    694694
    695695    /* Wait for EMAC Transmit Queue to become available. */
     
    702702    l = m;
    703703
    704     txbuf = (unsigned32)sc->tx_buf[sc->tx_head];
     704    txbuf = (uint32_t)sc->tx_buf[sc->tx_head];
    705705    while (l != NULL)
    706706    {
     
    863863    /* transmit interrupt */
    864864    while (sc->tx_dma[sc->tx_tail].addr & AU1X00_MAC_DMA_TXADDR_DN) {
    865         unsigned32 status;
     865        uint32_t status;
    866866        tx_flag = 1;
    867867        sc->tx_interrupts++;
  • c/src/lib/libbsp/mips/csb350/startup/bspstart.c

    r1e38faf r418899d  
    5050 
    5151void bsp_postdriver_hook(void);
    52 void bsp_libc_init( void *, unsigned32, int );
     52void bsp_libc_init( void *, uint32_t, int );
    5353
    5454/*
     
    6868void bsp_pretasking_hook(void)
    6969{
    70     unsigned32 heap_start;
    71     unsigned32 heap_size;
     70    uint32_t heap_start;
     71    uint32_t heap_size;
    7272
    7373    /*
     
    105105  BSP_Configuration.work_space_start = (void *)&_bss_free_start;
    106106 
    107   free_mem_start = ((unsigned32)&_bss_free_start +
     107  free_mem_start = ((uint32_t)&_bss_free_start +
    108108                    BSP_Configuration.work_space_size);
    109109 
    110   free_mem_end = ((unsigned32)&_sdram_base + (unsigned32)&_sdram_size);
     110  free_mem_end = ((uint32_t)&_sdram_base + (uint32_t)&_sdram_size);
    111111 
    112112  mips_set_sr( 0x7f00 );  /* all interrupts unmasked but globally off */
  • c/src/lib/libbsp/mips/csb350/timer/timer.c

    r1e38faf r418899d  
    1818
    1919rtems_boolean Timer_driver_Find_average_overhead;
    20 unsigned32 tstart;
     20uint32_t tstart;
    2121
    2222void Timer_initialize()
     
    3333int Read_timer()
    3434{
    35   unsigned32  total;
    36   unsigned32  cnt;
     35  uint32_t  total;
     36  uint32_t  cnt;
    3737
    3838  asm volatile ("mfc0 %0, $9\n" : "=r" (cnt));
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