Changeset 4159370 in rtems


Ignore:
Timestamp:
Jul 11, 2000, 9:16:53 PM (20 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
0daf588
Parents:
f38d829
Message:

Reworked score/cpu/sparc so it can be safely compiled multilib. All
routines and structures that require CPU model specific information
are now in libcpu. This primarily required moving erc32 specific
information from score/cpu files to libcpu/sparc and the erc32 BSP.

Files:
1 deleted
28 edited

Legend:

Unmodified
Added
Removed
  • c/src/exec/score/cpu/i960/rtems/score/i960.h

    rf38d829 r4159370  
    7373
    7474#if I960_HAS_FPU
    75 #define CPU_MODEL_NAME "i960 w/FPU"
     75#define CPU_MODEL_NAME "w/FPU"
    7676#else
    77 #define CPU_MODEL_NAME "i960 w/soft-float"
     77#define CPU_MODEL_NAME "w/soft-float"
    7878#endif
    7979#ifndef ASM
  • c/src/exec/score/cpu/sparc/Makefile.am

    rf38d829 r4159370  
    1111C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
    1212
    13 H_FILES = asm.h erc32.h
     13H_FILES = asm.h
    1414
    1515S_FILES = cpu_asm.S
     
    4444.PRECIOUS: $(REL)
    4545
    46 EXTRA_DIST = asm.h cpu.c cpu_asm.S erc32.h rtems.S
     46EXTRA_DIST = asm.h cpu.c cpu_asm.S rtems.S
    4747
    4848include $(top_srcdir)/../../../../../../automake/subdirs.am
  • c/src/exec/score/cpu/sparc/asm.h

    rf38d829 r4159370  
    109109
    110110/*
    111  *  Used for the reset trap for ERC32 to avoid a supervisor instruction
     111 *  Used for the reset trap to avoid a supervisor instruction
    112112 */
    113113 
  • c/src/exec/score/cpu/sparc/cpu.c

    rf38d829 r4159370  
    99 *  http://www.OARcorp.com/rtems/license.html.
    1010 *
    11  *  Ported to ERC32 implementation of the SPARC by On-Line Applications
    12  *  Research Corporation (OAR) under contract to the European Space
    13  *  Agency (ESA).
    14  *
    15  *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
    16  *  European Space Agency.
    17  *
    1811 *  $Id$
    1912 */
     
    2114#include <rtems/system.h>
    2215#include <rtems/score/isr.h>
    23 
    24 #if defined(erc32)
    25 #include <erc32.h>
    26 #endif
    2716
    2817/*
     
    112101
    113102  _CPU_Table = *cpu_table;
    114 
    115 #if defined(erc32)
    116 
    117   /*
    118    *  ERC32 specific initialization
    119    */
    120 
    121   _ERC32_MEC_Timer_Control_Mirror = 0;
    122   ERC32_MEC.Timer_Control = 0;
    123 
    124   ERC32_MEC.Control |= ERC32_CONFIGURATION_POWER_DOWN_ALLOWED;
    125 
    126 #endif
    127 
    128103}
    129104
     
    378353    the_context->psr = tmp_psr;
    379354}
    380 
    381 /*PAGE
    382  *
    383  *  _CPU_Thread_Idle_body
    384  *
    385  *  Some SPARC implementations have low power, sleep, or idle modes.  This
    386  *  tries to take advantage of those models. 
    387  */
    388  
    389 #if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
    390 
    391 /*
    392  *  This is the implementation for the erc32.
    393  *
    394  *  NOTE: Low power mode was enabled at initialization time.
    395  */
    396 
    397 #if defined(erc32)
    398 
    399 void _CPU_Thread_Idle_body( void )
    400 {
    401   while (1) {
    402     ERC32_MEC.Power_Down = 0;   /* value is irrelevant */
    403   }
    404 }
    405 
    406 #endif
    407 
    408 #endif /* CPU_PROVIDES_IDLE_THREAD_BODY */
  • c/src/exec/score/cpu/sparc/cpu_asm.S

    rf38d829 r4159370  
    1111 *  found in the file LICENSE in this distribution or at
    1212 *  http://www.OARcorp.com/rtems/license.html.
    13  *
    14  *  Ported to ERC32 implementation of the SPARC by On-Line Applications
    15  *  Research Corporation (OAR) under contract to the European Space
    16  *  Agency (ESA).
    17  *
    18  *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
    19  *  European Space Agency.
    2013 *
    2114 *  $Id$
  • c/src/exec/score/cpu/sparc/rtems.S

    rf38d829 r4159370  
    1010 *  found in the file LICENSE in this distribution or at
    1111 *  http://www.OARcorp.com/rtems/license.html.
    12  *
    13  *  Ported to ERC32 implementation of the SPARC by On-Line Applications
    14  *  Research Corporation (OAR) under contract to the European Space
    15  *  Agency (ESA).
    16  *
    17  *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
    18  *  European Space Agency.
    1912 *
    2013 *  $Id$
  • c/src/exec/score/cpu/sparc/rtems/score/cpu.h

    rf38d829 r4159370  
    1010 *  found in the file LICENSE in this distribution or at
    1111 *  http://www.OARcorp.com/rtems/license.html.
    12  *
    13  *  Ported to ERC32 implementation of the SPARC by On-Line Applications
    14  *  Research Corporation (OAR) under contract to the European Space
    15  *  Agency (ESA).
    16  *
    17  *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
    18  *  European Space Agency.
    1912 *
    2013 *  $Id$
     
    161154 */
    162155
    163 #if (SPARC_HAS_LOW_POWER_MODE == 1)
    164 #define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
    165 #else
    166156#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
    167 #endif
    168157
    169158/*
     
    561550SCORE_EXTERN void *_CPU_Interrupt_stack_high;
    562551
    563 #if defined(erc32)
    564 
    565 /*
    566  *  ERC32 Specific Variables
    567  */
    568 
    569 SCORE_EXTERN unsigned32 _ERC32_MEC_Timer_Control_Mirror;
    570 
    571 #endif
    572 
    573552/*
    574553 *  The following type defines an entry in the SPARC's trap table.
  • c/src/exec/score/cpu/sparc/rtems/score/sparc.h

    rf38d829 r4159370  
    1010 *  found in the file LICENSE in this distribution or at
    1111 *  http://www.OARcorp.com/rtems/license.html.
    12  *
    13  *  Ported to ERC32 implementation of the SPARC by On-Line Applications
    14  *  Research Corporation (OAR) under contract to the European Space
    15  *  Agency (ESA).
    16  *
    17  *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
    18  *  European Space Agency.
    1912 *
    2013 *  $Id$
     
    4841 *        8 is the most common number supported by SPARC implementations.
    4942 *        SPARC_PSR_CWP_MASK is derived from this value.
    50  *
    51  *    + SPARC_HAS_LOW_POWER_MODE
    52  *        0 - does not have low power mode support (or not supported)
    53  *        1 - has low power mode and thus a CPU model dependent idle task.
    54  *
    55  */
    56  
    57 #if defined(rtems_multilib)
    58 /*
    59  *  Figure out all CPU Model Feature Flags based upon compiler
    60  *  predefines.
    61  */
    62 
    63 #define CPU_MODEL_NAME                   "rtems_multilib"
     43 */
     44 
     45/*
     46 *  Some higher end SPARCs have a bitscan instructions. It would
     47 *  be nice to take advantage of them.  Right now, there is no
     48 *  port to a CPU model with this feature and no (untested) code
     49 *  that is based on this feature flag.
     50 */
     51
     52#define SPARC_HAS_BITSCAN                0
     53
     54/*
     55 *  This should be OK until a port to a higher end SPARC processor
     56 *  is made that has more than 8 register windows.  If this cannot
     57 *  be determined based on multilib settings (v7/v8/v9), then the
     58 *  cpu_asm.S code that depends on this will have to move to libcpu.
     59 */
     60
     61#define SPARC_NUMBER_OF_REGISTER_WINDOWS 8
     62 
     63/*
     64 *  This should be determined based on some soft float derived
     65 *  cpp predefine but gcc does not currently give us that information.
     66 */
     67
    6468#define SPARC_HAS_FPU                    1
    65 #define SPARC_HAS_BITSCAN                0
    66 #define SPARC_NUMBER_OF_REGISTER_WINDOWS 8
    67 #define SPARC_HAS_LOW_POWER_MODE         1
    68 
    69 #elif defined(erc32)
    70  
    71 #define CPU_MODEL_NAME                   "erc32"
    72 #define SPARC_HAS_FPU                    1
    73 #define SPARC_HAS_BITSCAN                0
    74 #define SPARC_NUMBER_OF_REGISTER_WINDOWS 8
    75 #define SPARC_HAS_LOW_POWER_MODE         1
    76  
     69
     70#if SPARC_HAS_FPU
     71#define CPU_MODEL_NAME "w/FPU"
    7772#else
    78  
    79 #error "Unsupported CPU Model"
    80  
     73#define CPU_MODEL_NAME "w/soft-float"
    8174#endif
    8275
  • c/src/exec/score/cpu/sparc/rtems/score/sparctypes.h

    rf38d829 r4159370  
    1010 *  found in the file LICENSE in this distribution or at
    1111 *  http://www.OARcorp.com/rtems/license.html.
    12  *
    13  *  Ported to ERC32 implementation of the SPARC by On-Line Applications
    14  *  Research Corporation (OAR) under contract to the European Space
    15  *  Agency (ESA).
    16  *
    17  *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
    18  *  European Space Agency.
    1912 *
    2013 *  $Id$
  • c/src/exec/score/cpu/sparc/rtems/score/types.h

    rf38d829 r4159370  
    1010 *  found in the file LICENSE in this distribution or at
    1111 *  http://www.OARcorp.com/rtems/license.html.
    12  *
    13  *  Ported to ERC32 implementation of the SPARC by On-Line Applications
    14  *  Research Corporation (OAR) under contract to the European Space
    15  *  Agency (ESA).
    16  *
    17  *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
    18  *  European Space Agency.
    1912 *
    2013 *  $Id$
  • c/src/exec/score/include/rtems/system.h

    rf38d829 r4159370  
    3131 * FIXME: cpuopts.h should be included here.
    3232 */
    33 #if defined(__sh__) \
     33#if defined(__h8300__) \
     34  || defined(__i960__) \
    3435  || defined(__mc68000__) \
    35   || defined(__h8300__) \
    36   || defined(__i960__)
     36  || defined(__sh__) \
     37  || defined(__sparc__)
    3738  /* these cpus are ready to apply cpuopts.h */
    3839#include <rtems/score/cpuopts.h>
    3940#else
    40   /* fallback to targopts.h */
     41  /* fallback to targopts.h for hppa1.1, i386, mips, and powerpc */
    4142#include <rtems/score/targopts.h>
    4243#endif
  • c/src/lib/libbsp/sparc/erc32/include/bsp.h

    rf38d829 r4159370  
    2020 */
    2121
    22 #ifndef __SIS_h
    23 #define __SIS_h
     22#ifndef __ERC32_BSP_h
     23#define __ERC32_BSP_h
    2424
    2525#ifdef __cplusplus
     
    2929#include <rtems.h>
    3030#include <iosupp.h>
    31 #include <erc32.h>
     31#include <libcpu/erc32.h>
    3232#include <clockdrv.h>
    3333
  • c/src/lib/libbsp/sparc/erc32/start/start.S

    rf38d829 r4159370  
    1212
    1313#include <asm.h>
    14 #include <erc32.h>
     14#include <libcpu/erc32.h>
    1515
    1616/*
  • c/src/lib/libbsp/sparc/erc32/startup/bspstart.c

    rf38d829 r4159370  
    4444
    4545extern rtems_unsigned32  rdb_start;
     46
     47/*
     48 *  Mirror of the Timer Control Register
     49 */
     50
     51unsigned32 _ERC32_MEC_Timer_Control_Mirror;
    4652
    4753/*
     
    166172
    167173/*
     174 *  ERC32_Idle_thread_body
     175 *
     176 *  ERC32 specific idle task that enters low power mode.
     177 */
     178
     179void ERC32_Idle_thread_body( void )
     180{
     181  while (1) {
     182    ERC32_MEC.Power_Down = 0;   /* value is irrelevant */
     183  }
     184}
     185
     186
     187
     188/*
    168189 *  bsp_start
    169190 *
     
    192213
    193214  }
     215
     216  /*
     217   *  Initialize the mirror of the Timer Control register.
     218   */
     219
     220  _ERC32_MEC_Timer_Control_Mirror = 0;
     221  ERC32_MEC.Timer_Control = 0;
     222
     223  ERC32_MEC.Control |= ERC32_CONFIGURATION_POWER_DOWN_ALLOWED;
    194224 
    195225  /*
     
    210240
    211241  /*
     242   *  ERC32 specific idle task.
     243   */
     244
     245  Cpu_table.idle_task = ERC32_Idle_thread_body;
     246
     247  /*
    212248   *  This should be enough interrupt stack.
    213249   */
  • c/src/lib/libcpu/i960/include/Makefile.am

    rf38d829 r4159370  
    66
    77H_FILES = i960CA.h i960HA.h i960KA.h i960RP.h i960JX_RP_common.h
    8 
    9 # NOTE: Unlike other CPUS, we install into a subdirectory to avoid
    10 #       file name conflicts
    118
    129$(PROJECT_INCLUDE)/libcpu:
  • c/src/lib/libcpu/sparc/Makefile.am

    rf38d829 r4159370  
    66ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal
    77
    8 SUBDIRS = reg_win syscall
     8SUBDIRS = include reg_win syscall
    99
    1010include $(top_srcdir)/../../../../../automake/subdirs.am
  • c/src/lib/libcpu/sparc/configure.in

    rf38d829 r4159370  
    3030AC_OUTPUT(
    3131Makefile
     32include/Makefile
    3233reg_win/Makefile
    3334syscall/Makefile)
  • cpukit/score/cpu/i960/rtems/score/i960.h

    rf38d829 r4159370  
    7373
    7474#if I960_HAS_FPU
    75 #define CPU_MODEL_NAME "i960 w/FPU"
     75#define CPU_MODEL_NAME "w/FPU"
    7676#else
    77 #define CPU_MODEL_NAME "i960 w/soft-float"
     77#define CPU_MODEL_NAME "w/soft-float"
    7878#endif
    7979#ifndef ASM
  • cpukit/score/cpu/sparc/Makefile.am

    rf38d829 r4159370  
    1111C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
    1212
    13 H_FILES = asm.h erc32.h
     13H_FILES = asm.h
    1414
    1515S_FILES = cpu_asm.S
     
    4444.PRECIOUS: $(REL)
    4545
    46 EXTRA_DIST = asm.h cpu.c cpu_asm.S erc32.h rtems.S
     46EXTRA_DIST = asm.h cpu.c cpu_asm.S rtems.S
    4747
    4848include $(top_srcdir)/../../../../../../automake/subdirs.am
  • cpukit/score/cpu/sparc/asm.h

    rf38d829 r4159370  
    109109
    110110/*
    111  *  Used for the reset trap for ERC32 to avoid a supervisor instruction
     111 *  Used for the reset trap to avoid a supervisor instruction
    112112 */
    113113 
  • cpukit/score/cpu/sparc/cpu.c

    rf38d829 r4159370  
    99 *  http://www.OARcorp.com/rtems/license.html.
    1010 *
    11  *  Ported to ERC32 implementation of the SPARC by On-Line Applications
    12  *  Research Corporation (OAR) under contract to the European Space
    13  *  Agency (ESA).
    14  *
    15  *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
    16  *  European Space Agency.
    17  *
    1811 *  $Id$
    1912 */
     
    2114#include <rtems/system.h>
    2215#include <rtems/score/isr.h>
    23 
    24 #if defined(erc32)
    25 #include <erc32.h>
    26 #endif
    2716
    2817/*
     
    112101
    113102  _CPU_Table = *cpu_table;
    114 
    115 #if defined(erc32)
    116 
    117   /*
    118    *  ERC32 specific initialization
    119    */
    120 
    121   _ERC32_MEC_Timer_Control_Mirror = 0;
    122   ERC32_MEC.Timer_Control = 0;
    123 
    124   ERC32_MEC.Control |= ERC32_CONFIGURATION_POWER_DOWN_ALLOWED;
    125 
    126 #endif
    127 
    128103}
    129104
     
    378353    the_context->psr = tmp_psr;
    379354}
    380 
    381 /*PAGE
    382  *
    383  *  _CPU_Thread_Idle_body
    384  *
    385  *  Some SPARC implementations have low power, sleep, or idle modes.  This
    386  *  tries to take advantage of those models. 
    387  */
    388  
    389 #if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
    390 
    391 /*
    392  *  This is the implementation for the erc32.
    393  *
    394  *  NOTE: Low power mode was enabled at initialization time.
    395  */
    396 
    397 #if defined(erc32)
    398 
    399 void _CPU_Thread_Idle_body( void )
    400 {
    401   while (1) {
    402     ERC32_MEC.Power_Down = 0;   /* value is irrelevant */
    403   }
    404 }
    405 
    406 #endif
    407 
    408 #endif /* CPU_PROVIDES_IDLE_THREAD_BODY */
  • cpukit/score/cpu/sparc/cpu_asm.S

    rf38d829 r4159370  
    1111 *  found in the file LICENSE in this distribution or at
    1212 *  http://www.OARcorp.com/rtems/license.html.
    13  *
    14  *  Ported to ERC32 implementation of the SPARC by On-Line Applications
    15  *  Research Corporation (OAR) under contract to the European Space
    16  *  Agency (ESA).
    17  *
    18  *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
    19  *  European Space Agency.
    2013 *
    2114 *  $Id$
  • cpukit/score/cpu/sparc/rtems/asm.h

    rf38d829 r4159370  
    109109
    110110/*
    111  *  Used for the reset trap for ERC32 to avoid a supervisor instruction
     111 *  Used for the reset trap to avoid a supervisor instruction
    112112 */
    113113 
  • cpukit/score/cpu/sparc/rtems/score/cpu.h

    rf38d829 r4159370  
    1010 *  found in the file LICENSE in this distribution or at
    1111 *  http://www.OARcorp.com/rtems/license.html.
    12  *
    13  *  Ported to ERC32 implementation of the SPARC by On-Line Applications
    14  *  Research Corporation (OAR) under contract to the European Space
    15  *  Agency (ESA).
    16  *
    17  *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
    18  *  European Space Agency.
    1912 *
    2013 *  $Id$
     
    161154 */
    162155
    163 #if (SPARC_HAS_LOW_POWER_MODE == 1)
    164 #define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
    165 #else
    166156#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
    167 #endif
    168157
    169158/*
     
    561550SCORE_EXTERN void *_CPU_Interrupt_stack_high;
    562551
    563 #if defined(erc32)
    564 
    565 /*
    566  *  ERC32 Specific Variables
    567  */
    568 
    569 SCORE_EXTERN unsigned32 _ERC32_MEC_Timer_Control_Mirror;
    570 
    571 #endif
    572 
    573552/*
    574553 *  The following type defines an entry in the SPARC's trap table.
  • cpukit/score/cpu/sparc/rtems/score/sparc.h

    rf38d829 r4159370  
    1010 *  found in the file LICENSE in this distribution or at
    1111 *  http://www.OARcorp.com/rtems/license.html.
    12  *
    13  *  Ported to ERC32 implementation of the SPARC by On-Line Applications
    14  *  Research Corporation (OAR) under contract to the European Space
    15  *  Agency (ESA).
    16  *
    17  *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
    18  *  European Space Agency.
    1912 *
    2013 *  $Id$
     
    4841 *        8 is the most common number supported by SPARC implementations.
    4942 *        SPARC_PSR_CWP_MASK is derived from this value.
    50  *
    51  *    + SPARC_HAS_LOW_POWER_MODE
    52  *        0 - does not have low power mode support (or not supported)
    53  *        1 - has low power mode and thus a CPU model dependent idle task.
    54  *
    55  */
    56  
    57 #if defined(rtems_multilib)
    58 /*
    59  *  Figure out all CPU Model Feature Flags based upon compiler
    60  *  predefines.
    61  */
    62 
    63 #define CPU_MODEL_NAME                   "rtems_multilib"
     43 */
     44 
     45/*
     46 *  Some higher end SPARCs have a bitscan instructions. It would
     47 *  be nice to take advantage of them.  Right now, there is no
     48 *  port to a CPU model with this feature and no (untested) code
     49 *  that is based on this feature flag.
     50 */
     51
     52#define SPARC_HAS_BITSCAN                0
     53
     54/*
     55 *  This should be OK until a port to a higher end SPARC processor
     56 *  is made that has more than 8 register windows.  If this cannot
     57 *  be determined based on multilib settings (v7/v8/v9), then the
     58 *  cpu_asm.S code that depends on this will have to move to libcpu.
     59 */
     60
     61#define SPARC_NUMBER_OF_REGISTER_WINDOWS 8
     62 
     63/*
     64 *  This should be determined based on some soft float derived
     65 *  cpp predefine but gcc does not currently give us that information.
     66 */
     67
    6468#define SPARC_HAS_FPU                    1
    65 #define SPARC_HAS_BITSCAN                0
    66 #define SPARC_NUMBER_OF_REGISTER_WINDOWS 8
    67 #define SPARC_HAS_LOW_POWER_MODE         1
    68 
    69 #elif defined(erc32)
    70  
    71 #define CPU_MODEL_NAME                   "erc32"
    72 #define SPARC_HAS_FPU                    1
    73 #define SPARC_HAS_BITSCAN                0
    74 #define SPARC_NUMBER_OF_REGISTER_WINDOWS 8
    75 #define SPARC_HAS_LOW_POWER_MODE         1
    76  
     69
     70#if SPARC_HAS_FPU
     71#define CPU_MODEL_NAME "w/FPU"
    7772#else
    78  
    79 #error "Unsupported CPU Model"
    80  
     73#define CPU_MODEL_NAME "w/soft-float"
    8174#endif
    8275
  • cpukit/score/cpu/sparc/rtems/score/types.h

    rf38d829 r4159370  
    1010 *  found in the file LICENSE in this distribution or at
    1111 *  http://www.OARcorp.com/rtems/license.html.
    12  *
    13  *  Ported to ERC32 implementation of the SPARC by On-Line Applications
    14  *  Research Corporation (OAR) under contract to the European Space
    15  *  Agency (ESA).
    16  *
    17  *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
    18  *  European Space Agency.
    1912 *
    2013 *  $Id$
  • cpukit/score/include/rtems/system.h

    rf38d829 r4159370  
    3131 * FIXME: cpuopts.h should be included here.
    3232 */
    33 #if defined(__sh__) \
     33#if defined(__h8300__) \
     34  || defined(__i960__) \
    3435  || defined(__mc68000__) \
    35   || defined(__h8300__) \
    36   || defined(__i960__)
     36  || defined(__sh__) \
     37  || defined(__sparc__)
    3738  /* these cpus are ready to apply cpuopts.h */
    3839#include <rtems/score/cpuopts.h>
    3940#else
    40   /* fallback to targopts.h */
     41  /* fallback to targopts.h for hppa1.1, i386, mips, and powerpc */
    4142#include <rtems/score/targopts.h>
    4243#endif
  • make/custom/p4600.cfg

    rf38d829 r4159370  
    44#  $Id$
    55#
    6 
    76
    87include $(RTEMS_ROOT)/make/custom/default.cfg
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