Changeset 40e7ae2 in rtems


Ignore:
Timestamp:
Sep 3, 2008, 8:36:21 PM (11 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.9, master
Children:
c8b03dbd
Parents:
e36390a6
Message:

2008-09-03 Joel Sherrill <joel.sherrill@…>

  • Makefile.am, README, configure.ac, console/85c30.c, console/console.c, console/consolebsp.h, include/bsp.h, include/gen2.h, irq/FPGA.c, irq/irq.c, irq/irq.h, irq/irq_init.c, start/start.S, startup/bspstart.c, startup/genpvec.c, startup/linkcmds, timer/timer.c, tod/tod.c: Initiate update and testing. Runs hello but does not run ticker yet.
Location:
c/src/lib/libbsp/powerpc/score603e
Files:
19 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/score603e/ChangeLog

    re36390a6 r40e7ae2  
     12008-09-03      Joel Sherrill <joel.sherrill@OARcorp.com>
     2
     3        * Makefile.am, README, configure.ac, console/85c30.c,
     4        console/console.c, console/consolebsp.h, include/bsp.h,
     5        include/gen2.h, irq/FPGA.c, irq/irq.c, irq/irq.h, irq/irq_init.c,
     6        start/start.S, startup/bspstart.c, startup/genpvec.c,
     7        startup/linkcmds, timer/timer.c, tod/tod.c: Initiate update and
     8        testing. Runs hello but does not run ticker yet.
     9
    1102008-08-31      Joel Sherrill <joel.sherrill@oarcorp.com>
    211
  • c/src/lib/libbsp/powerpc/score603e/Makefile.am

    re36390a6 r40e7ae2  
    2929    startup/bspstart.c ../../shared/bootcard.c \
    3030    ../../shared/sbrk.c startup/Hwr_init.c \
    31     startup/genpvec.c ../../shared/gnatinstallhandler.c
     31    startup/genpvec.c ../../shared/gnatinstallhandler.c \
     32    ../../powerpc/shared/showbats.c
     33
    3234pclock_SOURCES = ../../powerpc/shared/clock/p_clock.c
    3335console_SOURCES = console/85c30.c console/85c30.h console/console.c \
     
    3537
    3638include_bsp_HEADERS = ../../powerpc/shared/pci/pci.h \
     39    PCI_bus/PCI.h \
    3740    ../../powerpc/shared/residual/residual.h \
    3841    ../../powerpc/shared/residual/pnp.h \
     
    4043    ../../powerpc/shared/console/consoleIo.h
    4144pci_SOURCES = pci/no_host_bridge.c ../../powerpc/shared/pci/pci.c \
    42     ../../powerpc/shared/pci/pcifinddevice.c
     45    ../../powerpc/shared/pci/pcifinddevice.c  PCI_bus/PCI.c  PCI_bus/universe.c
    4346
    44 include_bsp_HEADERS += irq/irq.h
     47include_bsp_HEADERS += irq/irq.h \
     48    ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/ppc_exc_bspsupp.h \
     49    ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h \
     50    ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h
    4551irq_SOURCES = irq/FPGA.c irq/irq.c ../../powerpc/shared/irq/irq_asm.S
    4652
     
    5763    ../../shared/vmeUniverse/bspVmeDmaList.h\
    5864    ../../shared/vmeUniverse/VMEDMA.h
    59 vme_SOURCES = ../../shared/vmeUniverse/vmeUniverse.c \
     65vme_SOURCES = \
    6066    ../../shared/vmeUniverse/bspVmeDmaList.c \
    6167    ../../shared/vmeUniverse/vme_am_defs.h \
    62         ../shared/vme/vmeconfig.c \
    63         ../shared/vme/vme_universe.c
     68        ../shared/vme/vmeconfig.c
    6469
    6570EXTRA_DIST = start/start.S
     
    8287    ../../../libcpu/@RTEMS_CPU@/@exceptions@/rtems-cpu.rel \
    8388    ../../../libcpu/@RTEMS_CPU@/mpc6xx/clock.rel \
     89    ../../../libcpu/@RTEMS_CPU@/@exceptions@/exc_bspsupport.rel \
    8490    ../../../libcpu/@RTEMS_CPU@/@exceptions@/raw_exception.rel \
    85     ../../../libcpu/@RTEMS_CPU@/mpc6xx/mmu.rel \
     91     ../../../libcpu/@RTEMS_CPU@/mpc6xx/mmu.rel \
    8692    ../../../libcpu/@RTEMS_CPU@/mpc6xx/timer.rel
    8793
  • c/src/lib/libbsp/powerpc/score603e/README

    re36390a6 r40e7ae2  
    4343Notes
    4444=====
     45This BSP has been modified to use the latest exception model.
     46However, the modifications were never verified.  This version
     47has been partially verified in that Hello.ralf will load and
     48run on the board.
    4549
    46 This BSP has been tested using any Rom monitor.  There have
     50This BSP has been tested using DINK Rom monitor.  There have
    4751been three rom chips loaded on the boards.  One with the SDS
    4852debug monitor, one with the firmworks monitor, and one with
    49 the OAR Boot chip.  The OAR Boot chip contains the basic
    50 initialization from the SDS debugger and a jump to flash
    51 location 0x04001200.
     53the DINK monitor.
    5254
    5355The SCORE603e first generation board is no longer available,
  • c/src/lib/libbsp/powerpc/score603e/configure.ac

    re36390a6 r40e7ae2  
    3838[whether using console interrupts])
    3939
     40RTEMS_BSPOPTS_SET([HAS_PMC_PSC8],[*],[1])
     41RTEMS_BSPOPTS_HELP([HAS_PMC_PSC8],
     42[whether has a PSC8 PMC board attached to PMC slot])
     43
     44RTEMS_BSPOPTS_SET([INITIALIZE_COM_PORTS],[*],[0])
     45RTEMS_BSPOPTS_HELP([INITIALIZE_COM_PORTS],
     46[FIXME: Missing explanation])
     47
     48RTEMS_BSPOPTS_SET([PPC_USE_SPRG],[*],[0])
     49RTEMS_BSPOPTS_HELP([PPC_USE_SPRG],
     50[If defined, then the PowerPC specific code in RTEMS will use some
     51of the special purpose registers to slightly optimize interrupt
     52response time.  The use of these registers can conflict with
     53other tools like debuggers.])
     54
     55RTEMS_BSPOPTS_SET([PPC_USE_DATA_CACHE],[*],[0])
     56RTEMS_BSPOPTS_HELP([PPC_USE_DATA_CACHE],
     57[If defined, then the PowerPC specific code in RTEMS will use
     58 data cache instructions to optimize the context switch code.
     59 This code can conflict with debuggers or emulators.  It is known
     60 to break the Corelis PowerPC emulator with at least some combinations
     61 of PowerPC 603e revisions and emulator versions.
     62 The BSP actually contains the call that enables this.])
     63
     64RTEMS_BSPOPTS_SET([PPC_VECTOR_FILE_BASE],[*],[0x0100])
     65RTEMS_BSPOPTS_HELP([PPC_VECTOR_FILE_BASE],
     66[This defines the base address of the exception table.
     67 NOTE: Vectors are actually at 0xFFF00000 but file starts at offset.])
     68
    4069RTEMS_CHECK_NETWORKING
    4170AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
  • c/src/lib/libbsp/powerpc/score603e/console/85c30.c

    re36390a6 r40e7ae2  
    55 *  Currently only polled mode is supported.
    66 *
    7  *  COPYRIGHT (c) 1989-1997.
     7 *  COPYRIGHT (c) 1989-2008.
    88 *  On-Line Applications Research Corporation (OAR).
    99 *
     
    9595
    9696  rtems_bsp_delay_in_bus_cycles( 40 );
    97 
    9897  *csr = data;
    99 
    10098  rtems_bsp_delay_in_bus_cycles( 40 );
    10199}
     
    132130  uint16_t                baud_constant;
    133131
     132printk("initialize_85c30_port start\n");
     133
    134134  Setup = Port->Protocol;
    135135  ctrl  = Port->ctrl;
     
    156156   *  Set Write Register 2 to contain the interrupt vector
    157157   */
     158printk("initialize_85c30_port 2, %d\n", Port->Chip->vector );
    158159  Write_85c30_register( ctrl, 2, Port->Chip->vector );
    159160#endif
     
    162163   *  Set Write Register 3 to disable the Receiver
    163164   */
     165printk("initialize_85c30_port 0x03, 0x00\n");
    164166  Write_85c30_register( ctrl, 0x03, 0x00 );
    165167
     
    167169   *  Set Write Register 5 to disable the Transmitter
    168170   */
     171printk("initialize_85c30_port 5, 0x00\n");
    169172  Write_85c30_register( ctrl, 5, 0x00 );
    170173
     
    176179   *  Set Write Register 9 to disable all interrupt sources
    177180   */
     181printk("initialize_85c30_port 9, 0x00\n");
    178182  Write_85c30_register( ctrl, 9, 0x00 );
    179183
     
    181185   *  Set Write Register 10 for simple Asynchronous operation
    182186   */
     187printk("initialize_85c30_port 0x0a, 0x00\n");
    183188  Write_85c30_register( ctrl, 0x0a, 0x00 );
    184189
     
    188193   * as the output source for TRxC pin via register 11
    189194   */
     195printk("initialize_85c30_port 0x0b, 0x56\n");
    190196  Write_85c30_register( ctrl, 0x0b, 0x56 );
    191197
     
    197203   * baud rate will be equilvalent to 9600, via register 12.
    198204   */
     205printk("initialize_85c30_port 0x0c, 0x%x\n", value & 0xff);
    199206  Write_85c30_register( ctrl, 0x0c, value & 0xff );
    200207
     
    203210   * Setup the upper 8 bits time constants = 0
    204211   */
     212printk("initialize_85c30_port 0x0d, 0x%x\n", value>>8);
    205213  Write_85c30_register( ctrl, 0x0d, value>>8 );
    206214
     
    211219   * SCC's PCLK input via register 14.
    212220   */
     221printk("initialize_85c30_port 0x0e, 0x07\n");
    213222  Write_85c30_register( ctrl, 0x0e, 0x07 );
    214223
     
    226235  value = value | Char_size_85c30[ Setup->read_char_bits ].read_setup;
    227236
     237printk("initialize_85c30_port 0x03, 0x%x\n", value);
    228238  Write_85c30_register( ctrl, 0x03, value );
    229239
     
    240250  value = 0x8a;
    241251  value = value |  Char_size_85c30[ Setup->write_char_bits ].write_setup;
     252printk("initialize_85c30_port 0x05, 0x%x\n", value);
    242253  Write_85c30_register( ctrl, 0x05, value );
    243254
     
    246257   * via register 0
    247258   */
     259printk("initialize_85c30_port 0x00, 0xf0\n");
    248260   Write_85c30_register( ctrl, 0x00, 0xf0 );
    249261
     
    252264   *  Set Write Register 1 to interrupt on Rx characters or special condition.
    253265   */
     266printk("initialize_85c30_port 1, 0x10\n");
    254267  Write_85c30_register( ctrl, 1, 0x10 );
    255268#endif
     
    259272   */
    260273
     274printk("initialize_85c30_port 15, 0x00\n");
    261275  Write_85c30_register( ctrl, 15, 0x00 );
    262276
     
    264278   *  Set the Command Register to Reset Ext/STATUS.
    265279   */
     280printk("initialize_85c30_port 0x00, 0x10\n");
    266281  Write_85c30_register( ctrl, 0x00, 0x10 );
    267282
     
    274289   *    Enables Tx interrupt.
    275290   */
     291printk("initialize_85c30_port 1, 0x16\n");
    276292  Write_85c30_register( ctrl, 1, 0x16 );
    277293
     
    280296   *  Changed from 0 to a
    281297   */
     298printk("initialize_85c30_port 9, 0x0A\n");
    282299  Write_85c30_register( ctrl, 9, 0x0A );
    283300
     
    287304   *  Issue reset highest Interrupt Under Service (IUS) command.
    288305   */
     306printk("initialize_85c30_port STATUS_REGISTER, 0X38\n");
    289307  Write_85c30_register( Port->ctrl, STATUS_REGISTER, 0x38 );
    290308
    291309#endif
    292310
     311printk("initialize_85c30_port end of method\n");
    293312}
    294313
     
    378397  volatile Console_Protocol *Protocol;
    379398  unsigned char              data;
    380   rtems_boolean              did_something = FALSE;
     399  bool                       did_something = FALSE;
    381400
    382401  Protocol = Port->Protocol;
  • c/src/lib/libbsp/powerpc/score603e/console/console.c

    re36390a6 r40e7ae2  
    211211  int                        port, chip, p0,p1;
    212212
     213printk("console_initialize start\n");
     214
    213215  /*
    214216   * initialize the termio interface.
     
    265267   */
    266268
    267   for (port=0; port<NUM_Z85C30_PORTS; port++) {
    268     chip = port >> 1;
     269  for (port=1; port<NUM_Z85C30_PORTS; port++) {
     270   chip = port >> 1;
     271printk("console_initialize initialize_85c30_port %d\n", port);
    269272    initialize_85c30_port( &Ports_85C30[port] );
    270273  }
    271274
    272275#if CONSOLE_USE_INTERRUPTS
     276printk("console_initialize console_initialize_interrupts\n");
    273277  console_initialize_interrupts();
    274278#endif
    275279
     280printk("console_initialize end\n");
    276281  return RTEMS_SUCCESSFUL;
    277282}
     
    442447  csr = Ports_85C30[ console ].ctrl;
    443448
     449  if ('\n'==c){
     450    rtems_interrupt_disable( isrlevel );
     451    outbyte_polled_85c30( csr, '\r' );
     452    rtems_interrupt_enable( isrlevel );
     453    asm volatile("isync");
     454  }
     455
    444456  rtems_interrupt_disable( isrlevel );
    445457  outbyte_polled_85c30( csr, c );
  • c/src/lib/libbsp/powerpc/score603e/console/consolebsp.h

    re36390a6 r40e7ae2  
    1818#include <rtems.h>
    1919#include <rtems/ringbuf.h>
     20#include <bsp.h>
    2021
    2122#ifdef __cplusplus
     
    3536
    3637#if (HAS_PMC_PSC8)
     38#warning "HAS_PMC_PSC8 is Defined"
    3739#define NUM_Z85C30_CHIPS_ON_MEZZANINE  4
    3840#else
     
    7880#if CONSOLE_USE_INTERRUPTS
    7981  volatile Ring_buffer_t  TX_Buffer;         /* Transmit Buffer    */
    80   volatile rtems_boolean  Is_TX_active;      /* Transmitting       */
     82  volatile bool           Is_TX_active;      /* Transmitting       */
    8183  void          *console_termios_data;
    8284#endif
  • c/src/lib/libbsp/powerpc/score603e/include/bsp.h

    re36390a6 r40e7ae2  
    189189);
    190190
    191 rtems_boolean Is_PMC_IRQ(
     191bool Is_PMC_IRQ(
    192192  uint32_t           pmc_irq,
    193193  uint16_t           status_word
  • c/src/lib/libbsp/powerpc/score603e/include/gen2.h

    re36390a6 r40e7ae2  
    6161
    6262#define BSP_PMC_SERIAL_ADDRESS( _offset )    \
    63         ((volatile uint8_t *)(BSP_PCI_REGISTER_BASE + _offset))
     63        ((volatile uint8_t*)(BSP_PCI_REGISTER_BASE + _offset))
    6464
    6565/*
    6666 * PMC serial channels - (4-7: 232 and 8-11: 422)
    6767 */
    68 #define SCORE603E_85C30_CTRL_4        BSP_PMC_SERIAL_ADDRESS(0x200020)
    69 #define SCORE603E_85C30_DATA_4        BSP_PMC_SERIAL_ADDRESS(0x200024)
    70 #define SCORE603E_85C30_CTRL_5        BSP_PMC_SERIAL_ADDRESS(0x200028)
    71 #define SCORE603E_85C30_DATA_5        BSP_PMC_SERIAL_ADDRESS(0x20002c)
    72 #define SCORE603E_85C30_CTRL_6        BSP_PMC_SERIAL_ADDRESS(0x200030)
    73 #define SCORE603E_85C30_DATA_6        BSP_PMC_SERIAL_ADDRESS(0x200034)
    74 #define SCORE603E_85C30_CTRL_7        BSP_PMC_SERIAL_ADDRESS(0x200038)
    75 #define SCORE603E_85C30_DATA_7        BSP_PMC_SERIAL_ADDRESS(0x20003c)
    76 #define SCORE603E_85C30_CTRL_8        BSP_PMC_SERIAL_ADDRESS(0x200000)
    77 #define SCORE603E_85C30_DATA_8        BSP_PMC_SERIAL_ADDRESS(0x200004)
    78 #define SCORE603E_85C30_CTRL_9        BSP_PMC_SERIAL_ADDRESS(0x200008)
    79 #define SCORE603E_85C30_DATA_9        BSP_PMC_SERIAL_ADDRESS(0x20000c)
    80 #define SCORE603E_85C30_CTRL_10       BSP_PMC_SERIAL_ADDRESS(0x200010)
    81 #define SCORE603E_85C30_DATA_10       BSP_PMC_SERIAL_ADDRESS(0x200014)
    82 #define SCORE603E_85C30_CTRL_11       BSP_PMC_SERIAL_ADDRESS(0x200018)
    83 #define SCORE603E_85C30_DATA_11       BSP_PMC_SERIAL_ADDRESS(0x20001c)
     68#define SCORE603E_85C30_CTRL_4        BSP_PMC_SERIAL_ADDRESS(0x00200020)
     69#define SCORE603E_85C30_DATA_4        BSP_PMC_SERIAL_ADDRESS(0x00200024)
     70#define SCORE603E_85C30_CTRL_5        BSP_PMC_SERIAL_ADDRESS(0x00200028)
     71#define SCORE603E_85C30_DATA_5        BSP_PMC_SERIAL_ADDRESS(0x0020002c)
     72#define SCORE603E_85C30_CTRL_6        BSP_PMC_SERIAL_ADDRESS(0x00200030)
     73#define SCORE603E_85C30_DATA_6        BSP_PMC_SERIAL_ADDRESS(0x00200034)
     74#define SCORE603E_85C30_CTRL_7        BSP_PMC_SERIAL_ADDRESS(0x00200038)
     75#define SCORE603E_85C30_DATA_7        BSP_PMC_SERIAL_ADDRESS(0x0020003c)
     76#define SCORE603E_85C30_CTRL_8        BSP_PMC_SERIAL_ADDRESS(0x00200000)
     77#define SCORE603E_85C30_DATA_8        BSP_PMC_SERIAL_ADDRESS(0x00200004)
     78#define SCORE603E_85C30_CTRL_9        BSP_PMC_SERIAL_ADDRESS(0x00200008)
     79#define SCORE603E_85C30_DATA_9        BSP_PMC_SERIAL_ADDRESS(0x0020000c)
     80#define SCORE603E_85C30_CTRL_10       BSP_PMC_SERIAL_ADDRESS(0x00200010)
     81#define SCORE603E_85C30_DATA_10       BSP_PMC_SERIAL_ADDRESS(0x00200014)
     82#define SCORE603E_85C30_CTRL_11       BSP_PMC_SERIAL_ADDRESS(0x00200018)
     83#define SCORE603E_85C30_DATA_11       BSP_PMC_SERIAL_ADDRESS(0x0020001c)
    8484
    8585#define _IO_BASE                       PREP_ISA_IO_BASE
  • c/src/lib/libbsp/powerpc/score603e/irq/FPGA.c

    re36390a6 r40e7ae2  
    121121}
    122122
    123 rtems_boolean Is_PMC_IRQ(
     123bool Is_PMC_IRQ(
    124124  uint32_t           pmc_irq,
    125125  uint16_t           status_word
    126126)
    127127{
    128   rtems_boolean   result= FALSE;
     128  bool   result = FALSE;
    129129
    130130  switch(pmc_irq) {
  • c/src/lib/libbsp/powerpc/score603e/irq/irq.c

    re36390a6 r40e7ae2  
    9090    rtems_irq_connect_data* vchain;
    9191
     92printk(" BSP_install_rtems_shared_irq_handler %d\n", irq->name );
     93
    9294    if (!isValidInterrupt(irq->name)) {
    9395      printk("Invalid interrupt vector %d\n",irq->name);
     
    145147{
    146148    rtems_interrupt_level       level;
     149
     150printk(" BSP_install_rtems_irq_handler %d\n", irq->name );
    147151
    148152    if (!isValidInterrupt(irq->name)) {
     
    197201    rtems_interrupt_level       level;
    198202
     203printk(" BSP_get_current_rtems_irq_handler %d\n", irq->name );
    199204    if (!isValidInterrupt(irq->name)) {
    200205      return 0;
     
    211216    rtems_interrupt_level       level;
    212217
     218printk(" BSP_remove_rtems_irq_handler %d\n", irq->name );
    213219    if (!isValidInterrupt(irq->name)) {
    214220      return 0;
     
    320326    rtems_hdl_tbl               = config->irqHdlTbl;
    321327
     328printk(" BSP_rtems_irq_mngt_set\n");
     329
    322330    rtems_interrupt_disable(level);
    323331    /*
     
    398406
    399407unsigned BSP_spuriousIntr = 0;
     408
    400409/*
    401410 * High level IRQ handler called from shared_raw_irq_code_entry
     
    407416  register unsigned new_msr;
    408417
     418printk(" C_dispatch_irq_handler %d\n", excNum);
    409419  if (excNum == ASM_DEC_VECTOR) {
    410420    _CPU_MSR_GET(msr);
     
    418428
    419429  }
     430
    420431  irq = read_and_clear_irq();
    421432  _CPU_MSR_GET(msr);
     
    441452void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx)
    442453{
     454printk(" _ThreadProcessSignalsFromIrq \n");
    443455  /*
    444456   * Process pending signals that have not already been
  • c/src/lib/libbsp/powerpc/score603e/irq/irq.h

    re36390a6 r40e7ae2  
    1919 */
    2020
    21 #ifndef LIBBSP_POWERPC_IRQ_H
    22 #define LIBBSP_POWERPC_IRQ_H
     21#ifndef BSP_POWERPC_IRQ_H
     22#define BSP_POWERPC_IRQ_H
    2323
    2424#define BSP_SHARED_HANDLER_SUPPORT      1
     
    6666
    6767/*
    68  * Symbolic IRQ names and related definitions
     68 * rtems_irq_number Definitions
    6969 */
    7070
    71   /*
    72    * ISA IRQ handler related definitions
    73    */
     71/*
     72 * ISA IRQ handler related definitions
     73 */
    7474#define BSP_ISA_IRQ_NUMBER              (16)
    7575#define BSP_ISA_IRQ_LOWEST_OFFSET       (0)
    76 #define BSP_ISA_IRQ_MAX_OFFSET          (BSP_ISA_IRQ_LOWEST_OFFSET+BSP_ISA_IRQ_NUMBER-1)
    77   /*
    78    * PCI IRQ handlers related definitions
    79    * CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE
    80    */
     76#define BSP_ISA_IRQ_MAX_OFFSET          (BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1)
     77/*
     78 * PCI IRQ handlers related definitions
     79 * CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE
     80 */
    8181#define BSP_PCI_IRQ_NUMBER              (16)
    8282#define BSP_PCI_IRQ_LOWEST_OFFSET       (BSP_ISA_IRQ_NUMBER)
    83 #define BSP_PCI_IRQ_MAX_OFFSET          (BSP_PCI_IRQ_LOWEST_OFFSET+BSP_PCI_IRQ_NUMBER-1)
    84   /*
    85    * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt
    86    * handler might be connected
    87    */
     83#define BSP_PCI_IRQ_MAX_OFFSET          (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1)
     84/*
     85 * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt
     86 * handler might be connected
     87 */
    8888#define BSP_PROCESSOR_IRQ_NUMBER        (1)
    8989#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET + 1)
    90 #define BSP_PROCESSOR_IRQ_MAX_OFFSET    (BSP_PROCESSOR_IRQ_LOWEST_OFFSET+BSP_PROCESSOR_IRQ_NUMBER-1)
    91   /* Misc vectors for OPENPIC irqs (IPI, timers)
    92    */
     90#define BSP_PROCESSOR_IRQ_MAX_OFFSET    (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1)
     91/* Misc vectors for OPENPIC irqs (IPI, timers)
     92 */
    9393#define BSP_MISC_IRQ_NUMBER             (8)
    9494#define BSP_MISC_IRQ_LOWEST_OFFSET      (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1)
    95 #define BSP_MISC_IRQ_MAX_OFFSET         (BSP_MISC_IRQ_LOWEST_OFFSET+BSP_MISC_IRQ_NUMBER-1)
    96   /*
    97    * Summary
    98    */
     95#define BSP_MISC_IRQ_MAX_OFFSET         (BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1)
     96/*
     97 * Summary
     98 */
    9999#define BSP_IRQ_NUMBER                  (BSP_MISC_IRQ_MAX_OFFSET + 1)
    100100#define BSP_LOWEST_OFFSET               (BSP_ISA_IRQ_LOWEST_OFFSET)
    101 #define BSP_MAX_OFFSET                  (BSP_MISC_IRQ_MAX_OFFSET)
    102     /*
    103      * Some PCI IRQ symbolic name definition
    104      */
     101#define BSP_MAX_OFFSET                  (BSP_MISC_IRQ_MAX_OFFSET)
     102/*
     103 * Some ISA IRQ symbolic name definition
     104 */
     105#define BSP_ISA_PERIODIC_TIMER          (0)
     106#define BSP_ISA_KEYBOARD                (1)
     107#define BSP_ISA_UART_COM2_IRQ           (3)
     108#define BSP_ISA_UART_COM1_IRQ           (4)
     109#define BSP_ISA_RT_TIMER1               (8)
     110#define BSP_ISA_RT_TIMER3               (10)
     111/*
     112 * Some PCI IRQ symbolic name definition
     113 */
    105114#define BSP_PCI_IRQ0                    (BSP_PCI_IRQ_LOWEST_OFFSET)
     115#define BSP_PCI_ISA_BRIDGE_IRQ          (BSP_PCI_IRQ0)
    106116
    107     /*
    108      * Some Processor execption handled as RTEMS IRQ symbolic name definition
    109      */
     117#if defined(mvme2100)
     118#define BSP_DEC21143_IRQ                (BSP_PCI_IRQ_LOWEST_OFFSET + 1)
     119#define BSP_PMC_PCMIP_TYPE1_SLOT0_IRQ   (BSP_PCI_IRQ_LOWEST_OFFSET + 2)
     120#define BSP_PCMIP_TYPE1_SLOT1_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 3)
     121#define BSP_PCMIP_TYPE2_SLOT0_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 4)
     122#define BSP_PCMIP_TYPE2_SLOT1_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 5)
     123#define BSP_PCI_INTA_UNIVERSE_LINT0_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 7)
     124#define BSP_PCI_INTB_UNIVERSE_LINT1_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 8)
     125#define BSP_PCI_INTC_UNIVERSE_LINT2_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 9)
     126#define BSP_PCI_INTD_UNIVERSE_LINT3_IRQ (BSP_PCI_IRQ_LOWEST_OFFSET + 10)
     127#define BSP_UART_COM1_IRQ               (BSP_PCI_IRQ_LOWEST_OFFSET + 13)
     128#define BSP_FRONT_PANEL_ABORT_IRQ       (BSP_PCI_IRQ_LOWEST_OFFSET + 14)
     129#define BSP_RTC_IRQ                     (BSP_PCI_IRQ_LOWEST_OFFSET + 15)
     130#else
     131#define BSP_UART_COM1_IRQ               BSP_ISA_UART_COM1_IRQ
     132#define BSP_UART_COM2_IRQ               BSP_ISA_UART_COM2_IRQ
     133#endif
     134
     135/*
     136 * Some Processor execption handled as RTEMS IRQ symbolic name definition
     137 */
    110138#define BSP_DECREMENTER                 (BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
    111139
     140
     141/*
     142 * Type definition for RTEMS managed interrupts
     143 */
     144typedef unsigned short rtems_i8259_masks;
     145
     146extern  volatile rtems_i8259_masks i8259s_cache;
     147
     148/*-------------------------------------------------------------------------+
     149| Function Prototypes.
     150+--------------------------------------------------------------------------*/
     151/*
     152 * ------------------------ Intel 8259 (or emulation) Mngt Routines -------
     153 */
     154void BSP_i8259s_init(void);
     155
     156/*
     157 * function to disable a particular irq at 8259 level. After calling
     158 * this function, even if the device asserts the interrupt line it will
     159 * not be propagated further to the processor
     160 *
     161 * RETURNS: 1/0 if the interrupt was enabled/disabled originally or
     162 *          a value < 0 on error.
     163 */
     164int BSP_irq_disable_at_i8259s        (const rtems_irq_number irqLine);
     165/*
     166 * function to enable a particular irq at 8259 level. After calling
     167 * this function, if the device asserts the interrupt line it will
     168 * be propagated further to the processor
     169 */
     170int BSP_irq_enable_at_i8259s            (const rtems_irq_number irqLine);
     171/*
     172 * function to acknowledge a particular irq at 8259 level. After calling
     173 * this function, if a device asserts an enabled interrupt line it will
     174 * be propagated further to the processor. Mainly usefull for people
     175 * writing raw handlers as this is automagically done for RTEMS managed
     176 * handlers.
     177 */
     178int BSP_irq_ack_at_i8259s               (const rtems_irq_number irqLine);
     179/*
     180 * function to check if a particular irq is enabled at 8259 level. After calling
     181 */
     182int BSP_irq_enabled_at_i8259s           (const rtems_irq_number irqLine);
     183
     184extern void BSP_rtems_irq_mng_init(unsigned cpuId);
     185extern void BSP_i8259s_init(void);
     186
     187/* Stuff in irq_supp.h should eventually go into <rtems/irq.h> */
     188/* #include <bsp/irq_supp.h> */
     189
    112190#ifdef __cplusplus
    113 }
     191};
    114192#endif
    115193
    116194#endif
    117 
    118195#endif
  • c/src/lib/libbsp/powerpc/score603e/irq/irq_init.c

    re36390a6 r40e7ae2  
    2929#include <bsp/motorola.h>
    3030#include <rtems/bspIo.h>
     31
     32#define SHOW_ISA_PCI_BRIDGE_SETTINGS 1
     33#define SCAN_PCI_PRINT               1
     34#define TRACE_IRQ_INIT               1
    3135
    3236typedef struct {
  • c/src/lib/libbsp/powerpc/score603e/start/start.S

    re36390a6 r40e7ae2  
    105105
    106106.Lnostack:
     107
     108        lis     r13,_SDA_BASE_@ha
     109        la      r13,_SDA_BASE_@l(r13)           /* Read-write small data */
     110
    107111        /* set up initial stack frame */
    108112        addi    sp,sp,-4                /* make sure we don't overwrite debug mem */
  • c/src/lib/libbsp/powerpc/score603e/startup/bspstart.c

    re36390a6 r40e7ae2  
    2222#include <rtems/libcsupport.h>
    2323#include <rtems/bspIo.h>
     24#include <libcpu/cpuIdent.h>
     25#define DEBUG 1
     26
     27/*
     28 * Where the heap starts; is used by bsp_pretasking_hook;
     29 */
     30unsigned int BSP_heap_start;
    2431
    2532/*
     
    3744 */
    3845unsigned int BSP_time_base_divisor = 1000;  /* XXX - Just a guess */
     46
     47/*
     48 * system init stack
     49 */
     50#define INIT_STACK_SIZE 0x1000
     51
     52extern unsigned long __rtems_end[];
     53
    3954
    4055/*
     
    7691  uint32_t         heap_size;
    7792
     93  #if DEBUG
     94    printk("bsp_pretasking_hook: Set Heap\n");
     95  #endif
    7896  heap_start = (uint32_t) &end;
    7997  if (heap_start & (CPU_ALIGNMENT-1))
     
    83101  heap_size &= 0xfffffff0;  /* keep it as a multiple of 16 bytes */
    84102
     103  #if DEBUG
     104    printk("bsp_pretasking_hook: bsp_libc_init\n");
     105  #endif
    85106  bsp_libc_init((void *) heap_start, heap_size, 0);
     107  #if DEBUG
     108    printk("bsp_pretasking_hook: End of routine\n");
     109  #endif
    86110}
    87111
     
    98122void bsp_predriver_hook(void)
    99123{
     124  #if DEBUG
     125    printk("bsp_predriver_hook: init_RTC\n");
     126  #endif
    100127  init_RTC();
    101 /*   XXX - What Does this now ????
    102128  init_PCI();
    103129  initialize_universe();
    104 */
    105 
     130
     131  #if DEBUG
     132    printk("bsp_predriver_hook: initialize_PCI_bridge\n");
     133  #endif
    106134  initialize_PCI_bridge ();
    107135
    108136#if (HAS_PMC_PSC8)
     137  #if DEBUG
     138    printk("bsp_predriver_hook: initialize_PMC\n");
     139  #endif
    109140  initialize_PMC();
    110141#endif
    111142
     143#if 0
    112144 /*
    113145  * Initialize Bsp General purpose vector table.
    114146  */
     147  #if DEBUG
     148    printk("bsp_predriver_hook: initialize_external_exception_vector\n");
     149  #endif
    115150 initialize_external_exception_vector();
     151#endif
    116152
    117153#if (0)
     
    120156   *       to each interrupt location.  This is better for debug.
    121157   */
     158  #if DEBUG
     159    printk("bsp_predriver_hook: bsp_spurious_initialize\n");
     160  #endif
    122161 bsp_spurious_initialize();
    123162#endif
     163
     164  ShowBATS();
     165
     166  #if DEBUG
     167    printk("bsp_predriver_hook: End of routine\n");
     168  #endif
    124169
    125170}
     
    163208   * Clear status, enable SERR and memory space only.
    164209   */
     210  #if DEBUG
     211    printk("initialize_PMC: set Device Address 0x4 \n");
     212  ShowBATS();
     213  #endif
    165214  PMC_addr = BSP_PCI_DEVICE_ADDRESS( 0x4 );
    166215  *PMC_addr = 0x020080cc;
     
    169218   * set PMC base address.
    170219   */
     220  #if DEBUG
     221    printk("initialize_PMC: set Device Address 0x14 \n");
     222  ShowBATS();
     223  #endif
    171224  PMC_addr  = BSP_PCI_DEVICE_ADDRESS( 0x14 );
    172225  *PMC_addr = (BSP_PCI_REGISTER_BASE >> 24) & 0x3f;
    173226
    174   PMC_addr = (volatile uint32_t*)
     227  #if DEBUG
     228    printk("initialize_PMC: set PMC Serial Address 0x100000\n");
     229  #endif
     230   PMC_addr = (volatile uint32_t*)
    175231      BSP_PMC_SERIAL_ADDRESS( 0x100000 );
    176232  data = *PMC_addr;
     
    192248  extern void open_dev_console(void);
    193249
     250  #if DEBUG
     251    printk("bsp_postdriver_hook: open_dev_console\n");
     252  #endif
    194253  open_dev_console();
    195 
     254  ShowBATS();
     255
     256  #if DEBUG
     257    printk("bsp_postdriver_hook: Init_EE_mask_init\n");
     258  #endif
    196259  Init_EE_mask_init();
     260  ShowBATS();
     261  #if DEBUG
     262    printk("bsp_postdriver_hook: Finished procedure\n");
     263  #endif
    197264}
    198265
     
    210277  unsigned char *work_space_start;
    211278  unsigned int  msr_value = 0x0000;
     279  uint32_t      intrStackStart;
     280  uint32_t      intrStackSize;
    212281  volatile uint32_t         *ptr;
    213 
     282  ppc_cpu_id_t myCpu;
     283  ppc_cpu_revision_t myCpuRevision;
     284 
    214285  rtems_bsp_delay( 1000 );
    215286
     
    217288   *  Zero out lots of memory
    218289   */
     290  #if DEBUG
     291    printk("bsp_start: Zero out lots of memory\n");
     292    ShowBATS();
     293  #endif
    219294
    220295  memset(
     
    228303
    229304  /*
     305   * Get CPU identification dynamically. Note that the get_ppc_cpu_type()
     306   * function store the result in global variables so that it can be used
     307   * later...
     308   */
     309  myCpu         = get_ppc_cpu_type();
     310  myCpuRevision = get_ppc_cpu_revision();
     311
     312  /*
     313   * Initialize the interrupt related settings.
     314   */
     315  intrStackStart = (uint32_t) __rtems_end + INIT_STACK_SIZE;
     316  intrStackSize = rtems_configuration_get_interrupt_stack_size();
     317  BSP_heap_start = intrStackStart + intrStackSize;
     318
     319  /*
     320   * Initialize default raw exception handlers.
     321   */
     322printk("ppc_exc_initialize\n");
     323  ppc_exc_initialize(
     324    PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
     325    intrStackStart,
     326    intrStackSize
     327  );
     328
     329  /*
    230330   *  There are multiple ROM monitors available for this board.
    231331   */
    232332#if (SCORE603E_USE_SDS)
     333  #if DEBUG
     334    printk("bsp_start: USE SDS\n");
     335  #endif
     336
    233337
    234338  /*
     
    252356
    253357#elif (SCORE603E_USE_OPEN_FIRMWARE)
     358  #if DEBUG
     359    printk("bsp_start: USE OPEN FIRMWARE\n");
     360  #endif
    254361  msr_value = 0x2030;
    255362
    256363#elif (SCORE603E_USE_NONE)
     364  #if DEBUG
     365    printk("bsp_start: USE NONE\n");
     366  #endif
    257367  msr_value = 0x2030;
    258368  _CPU_MSR_SET( msr_value );
     
    260370
    261371#elif (SCORE603E_USE_DINK)
     372  #if DEBUG
     373    printk("bsp_start: USE DINK\n");
     374  #endif
    262375  msr_value = 0x2030;
    263376  _CPU_MSR_SET( msr_value );
     
    271384
    272385#else
     386  #if DEBUG
     387    printk("bsp_start: ERROR unknow ROM Monitor\n");
     388  #endif
    273389#error "SCORE603E BSPSTART.C -- what ROM monitor are you using"
    274390#endif
     
    282398   */
    283399
     400  #if DEBUG
     401    printk("bsp_start: Calculate Wrokspace\n");
     402  #endif
    284403  work_space_start =
    285404    (unsigned char *)&RAM_END - rtems_configuration_get_work_space_size();
     
    295414   *  initialize the device driver parameters
    296415   */
     416  #if DEBUG
     417    printk("bsp_start: set clicks poer usec\n");
     418  #endif
    297419  bsp_clicks_per_usec = 66 / 4;  /* XXX get from linkcmds */
    298420
    299421#if ( PPC_USE_DATA_CACHE )
     422  #if DEBUG
     423    printk("bsp_start: cache_enable\n");
     424  #endif
    300425  instruction_cache_enable ();
    301426  data_cache_enable ();
    302 #endif
    303 }
     427  #if DEBUG
     428    printk("bsp_start: END PPC_USE_DATA_CACHE\n");
     429  #endif
     430#endif
     431  #if DEBUG
     432    printk("bsp_start: end BSPSTART\n");
     433  ShowBATS();
     434  #endif
     435}
  • c/src/lib/libbsp/powerpc/score603e/startup/genpvec.c

    re36390a6 r40e7ae2  
    5353void init_irq_data_register(void);
    5454
     55#if 0
    5556void initialize_external_exception_vector (void)
    5657{
     
    7778           PPC_IRQ_EXTERNAL, (rtems_isr_entry *) &previous_isr );
    7879}
     80#endif
    7981
    8082void Init_EE_mask_init() {
     
    165167
    166168        if ( rtems_chain_is_tail( &ISR_Array[ index ], (void *)node ) ) {
    167           printk"ERROR:: check %d interrupt %02d has no isr\n", check_irq, index);
     169          printk ("ERROR:: check %d interrupt %02d has no isr\n", check_irq, index);
    168170          value = get_irq_mask();
    169171          printk("        Mask = %02x\n", value);
  • c/src/lib/libbsp/powerpc/score603e/startup/linkcmds

    re36390a6 r40e7ae2  
    194194    PROVIDE (__stack = .);
    195195    _end = . ;
     196    __rtems_end = . ;
    196197    PROVIDE (end = .);
    197198  } >RAM
  • c/src/lib/libbsp/powerpc/score603e/timer/timer.c

    re36390a6 r40e7ae2  
    2424uint64_t         Timer_driver_Start_time;
    2525
    26 rtems_boolean benchmark_timer_find_average_overhead;
     26bool benchmark_timer_find_average_overhead;
    2727
    2828/*
     
    7272
    7373void benchmark_timer_disable_subtracting_average_overhead(
    74   rtems_boolean find_flag
     74  bool find_flag
    7575)
    7676{
  • c/src/lib/libbsp/powerpc/score603e/tod/tod.c

    re36390a6 r40e7ae2  
    108108  int year;
    109109  int usec;
    110   static rtems_boolean init = TRUE;
     110  static bool init = TRUE;
    111111
    112112  /* Initialize the clock at once prior to reading */
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