Changeset 3fdea2d in rtems-docs


Ignore:
Timestamp:
Aug 25, 2017, 8:35:14 AM (2 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
5fc9f8b
Parents:
873ba80
Message:

cpu-supplement: Use literal instead of emphasis

Update #3082.

File:
1 edited

Legend:

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  • cpu-supplement/powerpc.rst

    r873ba80 r3fdea2d  
    126126==============
    127127
    128 * The thread pointer is `r13` in contrast to `r2` used in the 32-bit ABI.
     128* The thread pointer is ``r13`` in contrast to ``r2`` used in the 32-bit ABI.
    129129
    130 * The TOC pointer is `r2`.  It must be initialized as part of the C run-time
     130* The TOC pointer is ``r2``.  It must be initialized as part of the C run-time
    131131  setup.  A valid stack pointer is not enough to call C functions.  They may
    132132  use the TOC to get addresses and constants.
    133133
    134134* The TOC must be within the first 2GiB of the address space.  This simplifies
    135   the interrupt prologue, since the `r2` can be set to `.TOC.` via the usual
    136   `lis` followed by `ori` combination.  The `lis` is subject to sign-extension.
     135  the interrupt prologue, since the ``r2`` can be set to ``.TOC.`` via the
     136  usual ``lis`` followed by ``ori`` combination.  The ``lis`` is subject to
     137  sign-extension.
    137138
    138 * The `PPC_REG_LOAD`, `PPC_REG_STORE`, `PPC_REG_STORE_UPDATE`, and
    139   `PPC_REG_CMP` macros are available for assembly code to provide register size
    140   operations selected by the GCC `m32` and `m64` options.
     139* The ``PPC_REG_LOAD``, ``PPC_REG_STORE``, ``PPC_REG_STORE_UPDATE``, and
     140  ``PPC_REG_CMP`` macros are available for assembly code to provide register
     141  size operations selected by the GCC ``-m32`` and ``-m64`` options.
    141142
    142 * The `MSR[CM]` bit must be set all the time, otherwise the MMU translation my
    143   yield unexpected results.  The `EPCR[ICM]` or `EPCR[GICM]` bits may be used
    144   to enable the 64-bit compute mode for exceptions.
     143* The ``MSR[CM]`` bit must be set all the time, otherwise the MMU translation
     144  my yield unexpected results.  The ``EPCR[ICM]`` or ``EPCR[GICM]`` bits may be
     145  used to enable the 64-bit compute mode for exceptions.
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