Changeset 3f6b1ba in rtems
- Timestamp:
- 08/20/98 22:37:47 (24 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- fd808ba
- Parents:
- 1e291bb
- Location:
- doc/supplements/powerpc
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
doc/supplements/powerpc/timeDMV177.t
r1e291bb r3f6b1ba 61 61 62 62 All times reported in this chapter were measured using a RTEMS_BSP board. 63 All data and code caching was disabled. This results in very deterministic 64 times which represent the worst possible performance. Many embedded 65 applications disable caching to insure that execution times are 66 repeatable. Moreover, the JTAG port on certain revisions of the PowerPC 67 603e does not operate properly if caching is enabled. Thus during 68 development and debug, caching must be off. 63 69 64 70 The PowerPC decrementer register was was used to gather … … 66 72 this register typically counts 67 73 something like CPU cycles or is a function of the clock 68 speed. On the PPC603e decrements based on bus cycles. 69 This is a very accurate number and given the high clock 70 speed of the PowerPC family, Thus all measurements in this 74 speed. On the PPC603e decrements once for every four (4) bus cycles. 75 On the RTEMS_BSP, the bus operates at a clock speed of 76 33 Mhz. This result in a very accurate number since it is a function of the 77 microprocessor itself. Thus all measurements in this 71 78 chapter are reported as the actual number of decrementer 72 clicks reported. All sources of hardware interrupts were disabled, 79 clicks reported. 80 81 To convert the numbers reported to microseconds, one should 82 divide the number reported by 8.650752. This number was derived as 83 shown below: 84 85 @example 86 ((33 * 1048576) / 1000000) / 4 = 8.650752 87 @end example 88 89 All sources of hardware interrupts were disabled, 73 90 although traps were enabled and the interrupt level of the 74 91 PowerPC allows all interrupts. -
doc/supplements/powerpc/timedatadmv177.t
r1e291bb r3f6b1ba 61 61 62 62 All times reported in this chapter were measured using a RTEMS_BSP board. 63 All data and code caching was disabled. This results in very deterministic 64 times which represent the worst possible performance. Many embedded 65 applications disable caching to insure that execution times are 66 repeatable. Moreover, the JTAG port on certain revisions of the PowerPC 67 603e does not operate properly if caching is enabled. Thus during 68 development and debug, caching must be off. 63 69 64 70 The PowerPC decrementer register was was used to gather … … 66 72 this register typically counts 67 73 something like CPU cycles or is a function of the clock 68 speed. On the PPC603e decrements based on bus cycles. 69 This is a very accurate number and given the high clock 70 speed of the PowerPC family, Thus all measurements in this 74 speed. On the PPC603e decrements once for every four (4) bus cycles. 75 On the RTEMS_BSP, the bus operates at a clock speed of 76 33 Mhz. This result in a very accurate number since it is a function of the 77 microprocessor itself. Thus all measurements in this 71 78 chapter are reported as the actual number of decrementer 72 clicks reported. All sources of hardware interrupts were disabled, 79 clicks reported. 80 81 To convert the numbers reported to microseconds, one should 82 divide the number reported by 8.650752. This number was derived as 83 shown below: 84 85 @example 86 ((33 * 1048576) / 1000000) / 4 = 8.650752 87 @end example 88 89 All sources of hardware interrupts were disabled, 73 90 although traps were enabled and the interrupt level of the 74 91 PowerPC allows all interrupts.
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