Changeset 3f3c646 in rtems

Timestamp:

06/02/23 20:06:09 (6 months ago)

Author:

Kinsey Moore <kinsey.moore@…>

Branches:

master

Children:

ee63681a

Parents:

853429c3

git-author:

Kinsey Moore <kinsey.moore@…> (06/02/23 20:06:09)

git-committer:

Joel Sherrill <joel@…> (09/23/23 14:42:30)

Message:

bsps/xqspipsu: Add SFDP config space read ability

This adds a function to allow reading of the SFDP configuration space
that describes attributes of NOR flash chips.

Location:

bsps

Files:

• include/dev/spi/xqspipsu-flash-helper.h (modified) (1 diff)
• include/dev/spi/xqspipsu_flash_config.h (modified) (1 diff)
• shared/dev/spi/xqspipsu-flash-helper.c (modified) (1 diff)

bsps/include/dev/spi/xqspipsu-flash-helper.h

@@ -171 +171 @@
  ******************************************************************************/
 int QspiPsu_NOR_RDID(XQspiPsu *QspiPsuPtr, u8 *ReadBfrPtr, u32 ReadLen);
+
+/*****************************************************************************/
+/**
+ *
+ * This function performs a read of the SFDP configuration space.
+ *
+ * @param       QspiPsuPtr is a pointer to the QSPIPSU driver component to use.
+ * @param       ReadBfrPtr is a pointer to a buffer to be filled with
+ *              configuration data.
+ * @param       ReadLen is the total length of the configuration space to read.
+ *
+ * @return      XST_SUCCESS if successful, else XST_FAILURE.
+ *
+ ******************************************************************************/
+int QspiPsu_NOR_RDSFDP(
+  XQspiPsu *QspiPsuPtr,
+  u32 Address,
+  u32 ByteCount,
+  u8 **ReadBfrPtr
+);

bsps/include/dev/spi/xqspipsu_flash_config.h

@@ -65 +65 @@
 #define SEC_ERASE_CMD           0xD8
 #define READ_ID                 0x9F
+#define READ_SFDP               0x5A
 #define READ_CONFIG_CMD         0x35
 #define WRITE_CONFIG_CMD        0x01

bsps/shared/dev/spi/xqspipsu-flash-helper.c

@@ -273 +273 @@
     Error++;
   }
+}
+
+int QspiPsu_NOR_RDSFDP(
+  XQspiPsu *QspiPsuPtr,
+  u32 Address,
+  u32 ByteCount,
+  u8 **ReadBfrPtr
+)
+{
+  int Status;
+
+  *ReadBfrPtr = ReadBuffer;
+
+  CmdBfr[COMMAND_OFFSET]   = READ_SFDP;
+  CmdBfr[ADDRESS_1_OFFSET] =
+      (u8)((Address & 0xFF0000) >> 16);
+  CmdBfr[ADDRESS_2_OFFSET] =
+      (u8)((Address & 0xFF00) >> 8);
+  CmdBfr[ADDRESS_3_OFFSET] =
+      (u8)(Address & 0xFF);
+
+  FlashMsg[0].BusWidth = XQSPIPSU_SELECT_MODE_SPI;
+  FlashMsg[0].TxBfrPtr = CmdBfr;
+  FlashMsg[0].RxBfrPtr = NULL;
+  FlashMsg[0].ByteCount = 4;
+  FlashMsg[0].Flags = XQSPIPSU_MSG_FLAG_TX;
+
+  FlashMsg[1].BusWidth = XQSPIPSU_SELECT_MODE_SPI;
+  FlashMsg[1].TxBfrPtr = NULL;
+  FlashMsg[1].RxBfrPtr = NULL;
+  FlashMsg[1].ByteCount = DUMMY_CLOCKS;
+  FlashMsg[1].Flags = 0;
+
+  FlashMsg[2].BusWidth = XQSPIPSU_SELECT_MODE_SPI;
+  FlashMsg[2].TxBfrPtr = NULL;
+  FlashMsg[2].RxBfrPtr = *ReadBfrPtr;
+  FlashMsg[2].ByteCount = ByteCount;
+  FlashMsg[2].Flags = XQSPIPSU_MSG_FLAG_RX;
+
+  TransferInProgress = TRUE;
+  Status = XQspiPsu_InterruptTransfer(QspiPsuPtr, FlashMsg, 3);
+  if (Status != XST_SUCCESS)
+    return XST_FAILURE;
+
+  while (TransferInProgress);
+
+  rtems_cache_invalidate_multiple_data_lines(ReadBuffer, ByteCount);
+  return 0;
 }