Changeset 3ee5a2e in rtems


Ignore:
Timestamp:
Aug 9, 2011, 11:11:30 AM (10 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, 5, master
Children:
45dabfd
Parents:
40ae1fd
Message:

2011-08-09 Sebastian Huber <sebastian.huber@…>

  • nios2-iic-low-level.S: New file.
  • cpu_asm.S: Moved low-level interrupt handling into new file.
  • Makefile.am: Reflect change from above.
Location:
cpukit/score/cpu/nios2
Files:
1 added
3 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/nios2/ChangeLog

    r40ae1fd r3ee5a2e  
     12011-08-09      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * nios2-iic-low-level.S: New file.
     4        * cpu_asm.S: Moved low-level interrupt handling into new file.
     5        * Makefile.am: Reflect change from above.
     6
    172011-08-09      Sebastian Huber <sebastian.huber@embedded-brains.de>
    28
  • cpukit/score/cpu/nios2/Makefile.am

    r40ae1fd r3ee5a2e  
    1818
    1919noinst_LIBRARIES = libscorecpu.a
    20 libscorecpu_a_SOURCES = cpu.c irq.c cpu_asm.S
     20libscorecpu_a_SOURCES = cpu.c \
     21        irq.c \
     22        nios2-iic-low-level.S \
     23        cpu_asm.S
    2124libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS)
    2225
  • cpukit/score/cpu/nios2/cpu_asm.S

    r40ae1fd r3ee5a2e  
    8484    mov r5, r4
    8585    br  _CPU_Context_switch_restore
    86 
    87 
    88 /* ===================================================================== */
    89 
    90     .globl _exception_vector
    91 
    92 _exception_vector:
    93 
    94     /*
    95      * First, re-wind so we're pointed to the instruction where the exception
    96      * occurred.
    97      */
    98 
    99     addi ea, ea, -4
    100 
    101     /*
    102      * Now test to determine the cause of the exception.
    103      */
    104 
    105     /* TODO: Look at [ea] if there was an unknown/trap instruction */
    106 
    107     /* If interrupts are globally disabled, it certainly was no interrupt */
    108     rdctl et, estatus
    109     andi et, et, 1
    110     beq et, zero, _Exception_Handler
    111 
    112     /* If no interrupts are pending, it was a software exception */
    113     rdctl et, ipending
    114     beq et, zero, _Exception_Handler
    115 
    116     /*
    117      * Falling through to here means that this was a hardware interrupt.
    118      */
    119 
    120     br _ISR_Handler
    121 
    122 /* =====================================================================
    123  * Exception handler:
    124  *   Responsible for unimplemented instructions and other software
    125  *   exceptions. Not responsible for hardware interrupts. Currently,
    126  *   software exceptions are regarded as error conditions, and the
    127  *   handling isn't perfect. */
    128 
    129 _Exception_Handler:
    130 
    131     /* stw et, 108(sp') => stw et, -20(sp) */
    132     stw et, -20(sp)
    133     mov et, sp
    134     addi sp, sp, -128
    135 
    136     stw r1,   0(sp)
    137     stw r2,   4(sp)
    138     stw r3,   8(sp)
    139 
    140     rdctl r1, estatus
    141     rdctl r2, ienable
    142     rdctl r3, ipending
    143 
    144     stw r4,   12(sp)
    145     stw r5,   16(sp)
    146     stw r6,   20(sp)
    147     stw r7,   24(sp)
    148     stw r8,   28(sp)
    149     stw r9,   32(sp)
    150     stw r10,  36(sp)
    151     stw r11,  40(sp)
    152     stw r12,  44(sp)
    153     stw r13,  48(sp)
    154     stw r14,  52(sp)
    155     stw r15,  56(sp)
    156     stw r16,  60(sp)
    157     stw r17,  64(sp)
    158     stw r18,  68(sp)
    159     stw r19,  72(sp)
    160     stw r20,  76(sp)
    161     stw r21,  80(sp)
    162     stw r22,  84(sp)
    163     stw r23,  88(sp)
    164     stw gp,   92(sp)
    165     stw fp,   96(sp)
    166     /* sp */
    167     stw et,  100(sp)
    168     stw ra,  104(sp)
    169     /* stw et,  108(sp) */
    170     stw ea,  112(sp)
    171 
    172     /* status */
    173     stw r1, 116(sp)
    174     /* ienable */
    175     stw r2, 120(sp)
    176     /* ipending */
    177     stw r3, 124(sp)
    178 
    179     /*
    180      * Restore the global pointer.
    181      */
    182 
    183     movhi gp, %hiadj(_gp)
    184     addi gp, gp, %lo(_gp)
    185 
    186     /*
    187      * Pass a pointer to the stack frame as the input argument of the
    188      * exception handler (CPU_Exception_frame *).
    189      */
    190 
    191     mov r4, sp
    192 
    193     /*
    194      * Call the exception handler.
    195      */
    196 
    197     .extern __Exception_Handler
    198     call __Exception_Handler
    199 
    200 stuck_in_exception:
    201     br stuck_in_exception
    202 
    203     /*
    204      * Restore the saved registers, so that all general purpose registers
    205      * have been restored to their state at the time the interrupt occured.
    206      */
    207 
    208     ldw r1,   0(sp)
    209     ldw r2,   4(sp)
    210     ldw r3,   8(sp)
    211     ldw r4,   12(sp)
    212     ldw r5,   16(sp)
    213     ldw r6,   20(sp)
    214     ldw r7,   24(sp)
    215     ldw r8,   28(sp)
    216     ldw r9,   32(sp)
    217     ldw r10,  36(sp)
    218     ldw r11,  40(sp)
    219     ldw r12,  44(sp)
    220     ldw r13,  48(sp)
    221     ldw r14,  52(sp)
    222     ldw r15,  56(sp)
    223     ldw r16,  60(sp)
    224     ldw r17,  64(sp)
    225     ldw r18,  68(sp)
    226     ldw r19,  72(sp)
    227     ldw r20,  76(sp)
    228     ldw r21,  80(sp)
    229     ldw r22,  84(sp)
    230     ldw r23,  88(sp)
    231     ldw gp,   92(sp)
    232     ldw fp,   96(sp)
    233     ldw ra,  104(sp)
    234 
    235     /* Disable interrupts */
    236     wrctl status, r0
    237 
    238     ldw ea,  112(sp)
    239     ldw et,  116(sp)
    240 
    241     /* FIXME: Enable interrupts after exception processing */
    242     ori et, et, 1
    243     wrctl estatus, et
    244     ldw et,  108(sp)
    245 
    246     /* Restore stack pointer */
    247     ldw sp,  100(sp)
    248 
    249     eret
    250 
    251 /* ===================================================================== */
    252 
    253     .section .text
    254 
    255 _ISR_Handler:
    256 
    257     /*
    258      * Process an external hardware interrupt.
    259      *
    260      * First, preserve all callee saved registers on
    261      * the stack. (See the Nios2 ABI documentation for details).
    262      *
    263      * Do we really need to save all?
    264      *
    265      * If this is interrupting a task (and not another interrupt),
    266      * everything is saved into the task's stack, thus putting us
    267      * in a situation similar to when the task calls a subroutine
    268      * (and only the CPU_Context_Control subset needs to be changed)
    269      */
    270 
    271     rdctl et, estatus
    272 
    273     /* Keep this in the same order as CPU_Interrupt_frame: */
    274 
    275     addi sp, sp, -76
    276     stw r1,  0(sp)
    277     stw r2,  4(sp)
    278     stw r3,  8(sp)
    279     stw r4,  12(sp)
    280     stw r5,  16(sp)
    281     stw r6,  20(sp)
    282     stw r7,  24(sp)
    283     stw r8,  28(sp)
    284     stw r9,  32(sp)
    285     stw r10, 36(sp)
    286     stw r11, 40(sp)
    287     stw r12, 44(sp)
    288     stw r13, 48(sp)
    289     stw r14, 52(sp)
    290     stw r15, 56(sp)
    291     stw ra,  60(sp)
    292     stw gp,  64(sp)
    293     /* et contains status */
    294     stw et,  68(sp)
    295     stw ea,  72(sp)
    296 
    297     /*
    298      * Obtain a bitlist of the pending interrupts.
    299      */
    300 
    301     rdctl et, ipending
    302 
    303     /*
    304      * Restore the global pointer to the expected value.
    305      */
    306 
    307     movhi gp, %hiadj(_gp)
    308     addi gp, gp, %lo(_gp)
    309 
    310     /*
    311      * Search through the bit list stored in r24(et) to find the first enabled
    312      * bit. The offset of this bit is the index of the interrupt that is
    313      * to be handled.
    314      */
    315 
    316     mov r4, zero
    317 6:
    318     andi r3, r24, 1
    319     bne r3, zero, 7f
    320     addi r4, r4, 1
    321     srli r24, r24, 1
    322     br 6b
    323 7:
    324 
    325     /*
    326      * Having located the interrupt source, r4 contains the index of the
    327      * interrupt to be handled. r5, the 2nd argument to the function,
    328      * will point to the CPU_Interrupt_frame.
    329      */
    330 
    331     mov     r5, sp
    332 
    333     .extern __ISR_Handler
    334     call    __ISR_Handler
    335 
    336     /*
    337      * Now that the interrupt processing is complete, prepare to return to
    338      * the interrupted code.
    339      */
    340 
    341     /*
    342      * Restore the saved registers, so that all general purpose registers
    343      * have been restored to their state at the time the interrupt occured.
    344      */
    345 
    346     ldw r1,   0(sp)
    347     ldw r2,   4(sp)
    348     ldw r3,   8(sp)
    349     ldw r4,  12(sp)
    350     ldw r5,  16(sp)
    351     ldw r6,  20(sp)
    352     ldw r7,  24(sp)
    353     ldw r8,  28(sp)
    354     ldw r9,  32(sp)
    355     ldw r10, 36(sp)
    356     ldw r11, 40(sp)
    357     ldw r12, 44(sp)
    358     ldw r13, 48(sp)
    359     ldw r14, 52(sp)
    360     ldw r15, 56(sp)
    361     ldw ra,  60(sp)
    362     ldw gp,  64(sp)
    363 
    364     /* Disable interrupts */
    365     wrctl status, r0
    366 
    367     /* Restore the exception registers */
    368 
    369     /* load saved ea into ea */
    370     ldw ea,  72(sp)
    371     /* load saved estatus into et */
    372     ldw et,  68(sp)
    373     /* Always have interrupts enabled when we return from interrupt */
    374     ori et, et, 1
    375     wrctl estatus, et
    376     /* Restore the stack pointer */
    377     addi sp, sp, 76
    378 
    379     /*
    380      * Return to the interrupted instruction.
    381      */
    382     eret
    383 
    384 
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