Changeset 3d7fa72 in rtems


Ignore:
Timestamp:
Sep 12, 2007, 3:23:49 PM (12 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
7459fbf
Parents:
f93630d
Message:

2007-09-12 Joel Sherrill <joel.sherrill@…>

PR 1257/bsps

  • sh7032/score/cpu_asm.c, sh7032/timer/timer.c, sh7045/score/cpu_asm.c, sh7045/timer/timer.c, sh7750/score/cpu_asm.c, sh7750/timer/timer.c: Code outside of cpukit should use the public API for rtems_interrupt_disable/rtems_interrupt_enable. By bypassing the public API and directly accessing _CPU_ISR_Disable and _CPU_ISR_Enable, they were bypassing the compiler memory barrier directive which could lead to problems. This patch also changes the type of the variable passed into these routines and addresses minor style issues.
Location:
c/src/lib/libcpu/sh
Files:
7 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/sh/ChangeLog

    rf93630d r3d7fa72  
     12007-09-12      Joel Sherrill <joel.sherrill@OARcorp.com>
     2
     3        PR 1257/bsps
     4        * sh7032/score/cpu_asm.c, sh7032/timer/timer.c, sh7045/score/cpu_asm.c,
     5        sh7045/timer/timer.c, sh7750/score/cpu_asm.c, sh7750/timer/timer.c:
     6        Code outside of cpukit should use the public API for
     7        rtems_interrupt_disable/rtems_interrupt_enable. By bypassing the
     8        public API and directly accessing _CPU_ISR_Disable and
     9        _CPU_ISR_Enable, they were bypassing the compiler memory barrier
     10        directive which could lead to problems. This patch also changes the
     11        type of the variable passed into these routines and addresses minor
     12        style issues.
     13
    1142007-04-17      Ralf Corsépius <ralf.corsepius@rtems.org>
    215
  • c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c

    rf93630d r3d7fa72  
    6969  unsigned int prio )
    7070{
    71   uint32_t   shiftcount;
    72   uint32_t   prioreg;
    73   uint16_t   temp16;
    74   uint32_t   level;
     71  uint32_t         shiftcount;
     72  uint32_t         prioreg;
     73  uint16_t         temp16;
     74  ISR_Level        level;
    7575
    7676  /*
     
    113113   * Set the interrupt priority register
    114114   */
    115   _CPU_ISR_Disable( level );
    116 
    117   temp16 = read16( prioreg);
    118   temp16 &= ~( 15 << shiftcount);
    119   temp16 |= prio << shiftcount;
    120   write16( temp16, prioreg);
    121 
    122   _CPU_ISR_Enable( level );
     115  _ISR_Disable( level );
     116
     117    temp16 = read16( prioreg);
     118    temp16 &= ~( 15 << shiftcount);
     119    temp16 |= prio << shiftcount;
     120    write16( temp16, prioreg);
     121
     122  _ISR_Enable( level );
    123123
    124124  return 0;
     
    258258void __ISR_Handler( uint32_t   vector)
    259259{
    260   register uint32_t  level;
    261 
    262   _CPU_ISR_Disable( level );
     260  ISR_Level level;
     261
     262  _ISR_Disable( level );
    263263
    264264  _Thread_Dispatch_disable_level++;
     
    276276  _ISR_Nest_level++;
    277277
    278   _CPU_ISR_Enable( level );
     278  _ISR_Enable( level );
    279279
    280280  /* call isp */
     
    282282    (*_ISR_Vector_table[ vector ])( vector );
    283283
    284   _CPU_ISR_Disable( level );
     284  _ISR_Disable( level );
    285285
    286286  _Thread_Dispatch_disable_level--;
     
    295295#endif
    296296
    297   _CPU_ISR_Enable( level );
     297  _ISR_Enable( level );
    298298
    299299  if ( _ISR_Nest_level )
  • c/src/lib/libcpu/sh/sh7032/timer/timer.c

    rf93630d r3d7fa72  
    7373void Timer_initialize( void )
    7474{
    75   uint8_t    temp8;
    76   uint16_t   temp16;
    77   uint32_t   level;
    78   rtems_isr        *ignored;
     75  uint8_t                temp8;
     76  uint16_t               temp16;
     77  rtems_interrupt_level  level;
     78  rtems_isr             *ignored;
    7979
    8080  Timer_HZ = rtems_cpu_configuration_get_clicks_per_second() / CLOCK_SCALE ;
     
    8686
    8787  Timer_interrupts /* .i */ = 0;
    88   _CPU_ISR_Disable( level);
     88  rtems_interrupt_disable( level );
    8989
    9090  /*
     
    9292   */
    9393  /* stop Timer 1  */
    94   temp8 = read8( ITU_TSTR) & ITU1_STARTMASK;
    95   write8( temp8, ITU_TSTR);
     94  temp8 = read8(ITU_TSTR) & ITU1_STARTMASK;
     95  write8( temp8, ITU_TSTR );
    9696
    9797  /* initialize counter 1 */
    98   write16( 0, ITU_TCNT1);
     98  write16( 0, ITU_TCNT1 );
    9999
    100100  /* Timer 1 is independent of other timers */
    101   temp8 = read8( ITU_TSNC) & ITU1_SYNCMASK;
    102   write8( temp8, ITU_TSNC);
     101  temp8 = read8(ITU_TSNC) & ITU1_SYNCMASK;
     102  write8( temp8, ITU_TSNC );
    103103
    104104  /* Timer 1, normal mode */
    105   temp8 = read8( ITU_TMDR) & ITU1_MODEMASK;
    106   write8( temp8, ITU_TMDR);
     105  temp8 = read8(ITU_TMDR) & ITU1_MODEMASK;
     106  write8( temp8, ITU_TMDR );
    107107
    108108  /* Use a Phi/X counter */
    109   write8( ITU1_TCRMASK, ITU_TCR1);
     109  write8( ITU1_TCRMASK, ITU_TCR1 );
    110110
    111111  /* gra and grb are not used */
    112   write8( ITU1_TIORMASK, ITU_TIOR1);
     112  write8( ITU1_TIORMASK, ITU_TIOR1 );
    113113
    114114  /* reset all status flags */
    115   temp8 = read8( ITU_TSR1) & ITU1_STAT_MASK;
    116   write8( temp8, ITU_TSR1);
     115  temp8 = read8(ITU_TSR1) & ITU1_STAT_MASK;
     116  write8( temp8, ITU_TSR1 );
    117117
    118118  /* enable overflow interrupt */
    119   write8( ITU1_TIERMASK, ITU_TIER1);
     119  write8( ITU1_TIERMASK, ITU_TIER1 );
    120120
    121121  /* set interrupt priority */
    122   temp16 = read16( INTC_IPRC) & IPRC_ITU1_MASK;
     122  temp16 = read16(INTC_IPRC) & IPRC_ITU1_MASK;
    123123  temp16 |= ITU1_PRIO;
    124   write16( temp16, INTC_IPRC);
     124  write16( temp16, INTC_IPRC );
    125125
    126126  /* initialize ISR */
    127127  _CPU_ISR_install_raw_handler( ITU1_VECTOR, timerisr, &ignored );
    128   _CPU_ISR_Enable( level);
     128  rtems_interrupt_enable( level );
    129129
    130130  /* start timer 1 */
    131   temp8 = read8( ITU_TSTR) | ~ITU1_STARTMASK;
    132   write8( temp8, ITU_TSTR);
     131  temp8 = read8(ITU_TSTR) | ~ITU1_STARTMASK;
     132  write8( temp8, ITU_TSTR );
    133133}
    134134
     
    157157
    158158
    159   cclicks = read16( ITU_TCNT1);   /* XXX: read some HW here */
     159  cclicks = read16( ITU_TCNT1 );    /* XXX: read some HW here */
    160160
    161161  /*
     
    165165   */
    166166
    167   total = cclicks + Timer_interrupts * 65536 ;
     167  total = cclicks + Timer_interrupts * 65536;
    168168
    169169  if ( Timer_driver_Find_average_overhead )
     
    176176   *  Somehow convert total into microseconds
    177177   */
    178     return (total / CLOCK_SCALE - AVG_OVERHEAD) ;
     178    return (total / CLOCK_SCALE - AVG_OVERHEAD);
    179179  }
    180180}
     
    205205
    206206  /* reset the flags of the status register */
    207   temp8 = read8( ITU_TSR1) & ITU1_STAT_MASK;
    208   write8( temp8, ITU_TSR1);
     207  temp8 = read8(ITU_TSR1) & ITU1_STAT_MASK;
     208  write8( temp8, ITU_TSR1 );
    209209
    210210  Timer_interrupts += 1;
  • c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c

    rf93630d r3d7fa72  
    7171  uint32_t   prioreg;
    7272  uint16_t   temp16;
    73   uint32_t   level;
     73  ISR_Level  level;
    7474
    7575  /*
     
    115115   * Set the interrupt priority register
    116116   */
    117   _CPU_ISR_Disable( level );
    118 
    119   temp16 = read16( prioreg);
    120   temp16 &= ~( 15 << shiftcount);
    121   temp16 |= prio << shiftcount;
    122   write16( temp16, prioreg);
    123 
    124   _CPU_ISR_Enable( level );
     117  _ISR_Disable( level );
     118
     119    temp16 = read16( prioreg);
     120    temp16 &= ~( 15 << shiftcount);
     121    temp16 |= prio << shiftcount;
     122    write16( temp16, prioreg);
     123
     124  _ISR_Enable( level );
    125125
    126126  return 0;
     
    260260void __ISR_Handler( uint32_t   vector)
    261261{
    262   register uint32_t  level;
    263 
    264   _CPU_ISR_Disable( level );
     262  ISR_Level level;
     263
     264  _ISR_Disable( level );
    265265
    266266  _Thread_Dispatch_disable_level++;
     
    278278  _ISR_Nest_level++;
    279279
    280   _CPU_ISR_Enable( level );
     280  _ISR_Enable( level );
    281281
    282282  /* call isp */
     
    284284    (*_ISR_Vector_table[ vector ])( vector );
    285285
    286   _CPU_ISR_Disable( level );
     286  _ISR_Disable( level );
    287287
    288288  _Thread_Dispatch_disable_level--;
     
    297297#endif
    298298
    299   _CPU_ISR_Enable( level );
     299  _ISR_Enable( level );
    300300
    301301  if ( _ISR_Nest_level )
  • c/src/lib/libcpu/sh/sh7045/timer/timer.c

    rf93630d r3d7fa72  
    6464void Timer_initialize( void )
    6565{
    66   uint8_t    temp8;
    67   uint16_t   temp16;
    68   uint32_t   level;
    69   rtems_isr        *ignored;
     66  uint8_t                temp8;
     67  uint16_t               temp16;
     68  rtems_interrupt_level  level;
     69  rtems_isr             *ignored;
    7070
    7171  Timer_MHZ = rtems_cpu_configuration_get_clicks_per_second() / 1000000 ;
     
    7777
    7878  Timer_interrupts /* .i */ = 0;
    79   _CPU_ISR_Disable( level);
     79  rtems_interrupt_disable( level );
    8080
    8181  /*
     
    8383   */
    8484  /* stop Timer 1  */
    85   temp8 = read8( MTU_TSTR) & MTU1_STARTMASK;
    86   write8( temp8, MTU_TSTR);
     85  temp8 = read8(MTU_TSTR) & MTU1_STARTMASK;
     86  write8( temp8, MTU_TSTR );
    8787
    8888  /* initialize counter 1 */
     
    9090
    9191  /* Timer 1 is independent of other timers */
    92   temp8 = read8( MTU_TSYR) & MTU1_SYNCMASK;
    93   write8( temp8, MTU_TSYR);
     92  temp8 = read8(MTU_TSYR) & MTU1_SYNCMASK;
     93  write8( temp8, MTU_TSYR );
    9494
    9595  /* Timer 1, normal mode */
    96   temp8 = read8( MTU_TMDR1) & MTU1_MODEMASK;
    97   write8( temp8, MTU_TMDR1);
     96  temp8 = read8(MTU_TMDR1) & MTU1_MODEMASK;
     97  write8( temp8, MTU_TMDR1 );
    9898
    9999  /* x0000000
     
    103103   * +---------- don`t care
    104104   */
    105   write8( MTU1_TCRMASK, MTU_TCR1);
     105  write8( MTU1_TCRMASK, MTU_TCR1 );
    106106
    107107  /* gra and grb are not used */
    108   write8( MTU1_TIORMASK, MTU_TIOR1);
     108  write8( MTU1_TIORMASK, MTU_TIOR1 );
    109109
    110110  /* reset all status flags */
    111   temp8 = read8( MTU_TSR1) & MTU1_STAT_MASK;
    112   write8( temp8, MTU_TSR1);
     111  temp8 = read8(MTU_TSR1) & MTU1_STAT_MASK;
     112  write8( temp8, MTU_TSR1 );
    113113
    114114  /* enable overflow interrupt */
    115   write8( MTU1_TIERMASK, MTU_TIER1);
     115  write8( MTU1_TIERMASK, MTU_TIER1 );
    116116
    117117  /* set interrupt priority */
    118   temp16 = read16( INTC_IPRC) & IPRC_MTU1_MASK;
     118  temp16 = read16(INTC_IPRC) & IPRC_MTU1_MASK;
    119119  temp16 |= MTU1_PRIO;
    120120  write16( temp16, INTC_IPRC);
     
    122122  /* initialize ISR */
    123123  _CPU_ISR_install_raw_handler( MTU1_VECTOR, timerisr, &ignored );
    124   _CPU_ISR_Enable( level);
     124  rtems_interrupt_enable( level );
    125125
    126126  /* start timer 1 */
    127   temp8 = read8( MTU_TSTR) | ~MTU1_STARTMASK;
    128   write8( temp8, MTU_TSTR);
     127  temp8 = read8(MTU_TSTR) | ~MTU1_STARTMASK;
     128  write8( temp8, MTU_TSTR );
    129129}
    130130
     
    153153
    154154
    155   clicks = read16( MTU_TCNT1);   /* XXX: read some HW here */
     155  clicks = read16( MTU_TCNT1 );   /* XXX: read some HW here */
    156156
    157157  /*
     
    161161   */
    162162
    163   total = clicks + Timer_interrupts * 65536 ;
     163  total = clicks + Timer_interrupts * 65536;
    164164
    165165  if ( Timer_driver_Find_average_overhead )
     
    201201
    202202  /* reset the flags of the status register */
    203   temp8 = read8( MTU_TSR1) & MTU1_STAT_MASK;
    204   write8( temp8, MTU_TSR1);
     203  temp8 = read8(MTU_TSR1) & MTU1_STAT_MASK;
     204  write8( temp8, MTU_TSR1 );
    205205
    206206  Timer_interrupts += 1;
  • c/src/lib/libcpu/sh/sh7750/score/cpu_asm.c

    rf93630d r3d7fa72  
    257257void __ISR_Handler( uint32_t   vector)
    258258{
    259   register uint32_t  level;
    260 
    261   _CPU_ISR_Disable( level );
     259  ISR_Level level;
     260
     261  _ISR_Disable( level );
    262262
    263263  _Thread_Dispatch_disable_level++;
     
    275275  _ISR_Nest_level++;
    276276
    277   _CPU_ISR_Enable( level );
     277  _ISR_Enable( level );
    278278
    279279  /* call isp */
     
    281281    (*_ISR_Vector_table[ vector ])( vector );
    282282
    283   _CPU_ISR_Disable( level );
     283  _ISR_Disable( level );
    284284
    285285  _Thread_Dispatch_disable_level--;
     
    294294#endif
    295295
    296   _CPU_ISR_Enable( level );
     296  _ISR_Enable( level );
    297297
    298298  if ( _ISR_Nest_level )
  • c/src/lib/libcpu/sh/sh7750/timer/timer.c

    rf93630d r3d7fa72  
    6666Timer_initialize(void)
    6767{
    68     uint8_t         temp8;
    69     uint16_t        temp16;
     68    uint8_t               temp8;
     69    uint16_t              temp16;
    7070    rtems_interrupt_level level;
    7171    rtems_isr            *ignored;
     
    7474
    7575    Timer_interrupts  = 0;
    76     _CPU_ISR_Disable(level);
     76    rtems_interrupt_disable(level);
    7777
    7878    /* Get CPU frequency divider from clock unit */
     
    168168
    169169
    170     _CPU_ISR_Enable(level);
     170    rtems_interrupt_enable(level);
    171171
    172172    /* Start the Timer 1 */
     
    204204Read_timer(void)
    205205{
    206     uint32_t   clicks;
    207     uint32_t   ints;
    208     uint32_t   total ;
     206    uint32_t              clicks;
     207    uint32_t              ints;
     208    uint32_t              total;
    209209    rtems_interrupt_level level;
    210     uint32_t   tcr;
    211 
    212 
    213     _CPU_ISR_Disable(level);
     210    uint32_t              tcr;
     211
     212
     213    rtems_interrupt_disable(level);
    214214
    215215    clicks = 0xFFFFFFFF - read32(SH7750_TCNT1);
     
    217217    ints = Timer_interrupts;
    218218
    219     _CPU_ISR_Enable(level);
     219    rtems_interrupt_enable(level);
    220220
    221221    /* Handle the case when timer overflowed but interrupt was not processed */
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