Changeset 3d6e174 in rtems


Ignore:
Timestamp:
Dec 21, 2013, 9:36:05 PM (5 years ago)
Author:
Daniel Ramirez <javamonn@…>
Branches:
4.11, master
Children:
49232d0
Parents:
2bafb960
git-author:
Daniel Ramirez <javamonn@…> (12/21/13 21:36:05)
git-committer:
Gedare Bloom <gedare@…> (12/22/13 16:10:01)
Message:

gumstix: added new doxygen

Location:
c/src/lib/libbsp/arm/gumstix
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/gumstix/include/bsp.h

    r2bafb960 r3d6e174  
     1/**
     2 * @file
     3 * @ingroup arm_gumstix
     4 * @brief Global BSP definitions.
     5 */
     6
    17/*
    28 *  By Yang Xi <hiyangxi@gmail.com>.
     
    2228#include <libchip/serial.h>
    2329
     30/**
     31 * @defgroup arm_gumstix Gumstix Support
     32 * @ingroup bsp_arm
     33 * @brief Gumstix support package
     34 * @{
     35 */
     36
    2437#define BSP_FEATURE_IRQ_EXTENSION
    2538
    2639#define BSP_HAS_FRAME_BUFFER 1
    2740
    28 /* What is the input clock freq in hertz */
     41/** @brief What is the input clock freq in hertz */
    2942#define BSP_MAIN_FREQ 3686400      /* 3.6864 MHz */
    3043#define BSP_SLCK_FREQ   32768      /* 32.768 KHz */
    3144
    32 /* What is the last interrupt */
     45/** @brief What is the last interrupt */
    3346#define BSP_MAX_INT AT91RM9200_MAX_INT
    3447
     
    3649static inline int32_t BSP_get_baud(void) {return 115200;}
    3750
    38 /* How big should the interrupt stack be? */
     51/** @brief How big should the interrupt stack be? */
    3952#define CONFIGURE_INTERRUPT_STACK_MEMORY  (16 * 1024)
    4053
     
    5972#endif
    6073
     74/** @} */
     75
    6176#ifdef __cplusplus
    6277}
  • c/src/lib/libbsp/arm/gumstix/include/tm27.h

    r2bafb960 r3d6e174  
     1/**
     2 * @file
     3 * @ingroup gumstix_tm27
     4 * @brief tm27 timing test support
     5 */
     6
    17/*
    28 *  tm27.h
     
    1420#define __tm27_h
    1521
    16 /*
    17  *  Define the interrupt mechanism for Time Test 27
     22/**
     23 * @defgroup gumstix_tm27 tm27 Support
     24 * @ingroup arm_gumstix
     25 * @brief tm27 Timing Test Support
     26 * @{
     27 */
     28
     29/**
     30 * @name Interrupt mechanisms for Time Test 27
     31 * @{
    1832 */
    1933
     
    2842#define Lower_tm27_intr() /* empty */
    2943
     44/** @} */
     45
     46/** @} */
     47
    3048#endif
  • c/src/lib/libbsp/arm/gumstix/rtl8019/wd80x3.h

    r2bafb960 r3d6e174  
     1/**
     2 * @file
     3 * @ingroup gumstix_dp8390
     4 * @brief DP8390 Ethernet Controller Support
     5 */
     6
    17/*
    28 *  Information about the DP8390 Ethernet controller.
     
    713
    814/* Register descriptions */
    9 /* Controller DP8390.    */
    10 
    11 #define DATAPORT        0x10    /* Port Window. */
    12 #define RESET           0x1f    /* Issue a read for reset */
    13 #define W83CREG         0x00    /* I/O port definition */
     15
     16/**
     17 * @defgroup gumstix_dp8390 DP8390 Support
     18 * @ingroup arm_gumstix
     19 * @brief DP8390 Ethernet Controller Support
     20 * @{
     21 */
     22
     23/**
     24 * @name Controller DP8390.
     25 * @{
     26 */
     27
     28/** @brief Port Window. */
     29#define DATAPORT        0x10
     30/** @brief Issue a read for reset */
     31#define RESET           0x1f
     32/** @brief I/O port definition */
     33#define W83CREG         0x00
    1434#define ADDROM          0x08
    1535
    16 /* page 0 read or read/write registers */
     36/** @} */
     37
     38/**
     39 * @name page 0 read or read/write registers
     40 * @{
     41 */
    1742
    1843#define CMDR            0x00+RO
    19 #define CLDA0           0x01+RO /* current local dma addr 0 for read */
    20 #define CLDA1           0x02+RO /* current local dma addr 1 for read */
    21 #define BNRY            0x03+RO /* boundary reg for rd and wr */
    22 #define TSR             0x04+RO /* tx status reg for rd */
    23 #define NCR             0x05+RO /* number of collision reg for rd */
    24 #define FIFO            0x06+RO /* FIFO for rd */
    25 #define ISR             0x07+RO /* interrupt status reg for rd and wr */
    26 #define CRDA0           0x08+RO /* current remote dma address 0 for rd */
    27 #define CRDA1           0x09+RO /* current remote dma address 1 for rd */
    28 #define RSR             0x0C+RO /* rx status reg for rd */
    29 #define CNTR0           0x0D+RO /* tally cnt 0 for frm alg err for rd */
    30 #define CNTR1           RO+0x0E /* tally cnt 1 for crc err for rd */
    31 #define CNTR2           0x0F+RO /* tally cnt 2 for missed pkt for rd */
    32 
    33 /* page 0 write registers */
    34 
    35 #define PSTART          0x01+RO /* page start register */
    36 #define PSTOP           0x02+RO /* page stop register */
    37 #define TPSR            0x04+RO /* tx start page start reg */
    38 #define TBCR0           0x05+RO /* tx byte count 0 reg */
    39 #define TBCR1           0x06+RO /* tx byte count 1 reg */
    40 #define RSAR0           0x08+RO /* remote start address reg 0  */
    41 #define RSAR1           0x09+RO /* remote start address reg 1 */
    42 #define RBCR0           0x0A+RO /* remote byte count reg 0 */
    43 #define RBCR1           0x0B+RO /* remote byte count reg 1 */
    44 #define RCR             0x0C+RO /* rx configuration reg */
    45 #define TCR             0x0D+RO /* tx configuration reg */
    46 #define DCR             RO+0x0E /* data configuration reg */
    47 #define IMR             0x0F+RO /* interrupt mask reg */
    48 
    49 /* page 1 registers */
    50 
    51 #define PAR             0x01+RO /* physical addr reg base for rd and wr */
    52 #define CURR            0x07+RO /* current page reg for rd and wr */
    53 #define MAR             0x08+RO /* multicast addr reg base fro rd and WR */
    54 #define MARsize 8               /* size of multicast addr space */
    55 
    56 /*-----W83CREG command bits-----*/
    57 #define MSK_RESET  0x80         /* W83CREG masks */
     44/** @brief current local dma addr 0 for read */
     45#define CLDA0           0x01+RO
     46/** @brief current local dma addr 1 for read */
     47#define CLDA1           0x02+RO
     48/** @brief boundary reg for rd and wr */
     49#define BNRY            0x03+RO
     50/** @brief tx status reg for rd */
     51#define TSR             0x04+RO
     52/** @brief number of collision reg for rd */
     53#define NCR             0x05+RO
     54/** @breif FIFO for rd */
     55#define FIFO            0x06+RO
     56/** @brief interrupt status reg for rd and wr */
     57#define ISR             0x07+RO
     58/** @brief current remote dma address 0 for rd */
     59#define CRDA0           0x08+RO
     60/** @brief current remote dma address 1 for rd */
     61#define CRDA1           0x09+RO
     62/** @brief rx status reg for rd */
     63#define RSR             0x0C+RO
     64/** @brief tally cnt 0 for frm alg err for rd */
     65#define CNTR0           0x0D+RO
     66/** @brief tally cnt 1 for crc err for rd */
     67#define CNTR1           RO+0x0E
     68/** @brief tally cnt 2 for missed pkt for rd */
     69#define CNTR2           0x0F+RO
     70
     71/** @} */
     72
     73/**
     74 * @name page 0 write registers
     75 * @{
     76 */
     77
     78/** @brief page start register */
     79#define PSTART          0x01+RO
     80/** @brief page stop register */
     81#define PSTOP           0x02+RO
     82/** @breif tx start page start reg */
     83#define TPSR            0x04+RO
     84/** @brief tx byte count 0 reg */
     85#define TBCR0           0x05+RO
     86/** @brief tx byte count 1 reg */
     87#define TBCR1           0x06+RO
     88/** @brief remote start address reg 0  */
     89#define RSAR0           0x08+RO
     90/** @brief remote start address reg 1 */
     91#define RSAR1           0x09+RO
     92/** @brief remote byte count reg 0 */
     93#define RBCR0           0x0A+RO
     94/** @brief remote byte count reg 1 */
     95#define RBCR1           0x0B+RO
     96/** @brief rx configuration reg */
     97#define RCR             0x0C+RO
     98/** @brief tx configuration reg */
     99#define TCR             0x0D+RO
     100/** @brief data configuration reg */
     101#define DCR             RO+0x0E
     102/** @brief interrupt mask reg */
     103#define IMR             0x0F+RO
     104
     105/** @} */
     106
     107/**
     108 * @name page 1 registers
     109 * @{
     110 */
     111
     112/** @brief physical addr reg base for rd and wr */
     113#define PAR             0x01+RO
     114/** @brief current page reg for rd and wr */
     115#define CURR            0x07+RO
     116/** @brief multicast addr reg base fro rd and WR */
     117#define MAR             0x08+RO
     118/** @brief size of multicast addr space */
     119#define MARsize 8
     120
     121/** @} */
     122
     123/**
     124 * @name W83CREG command bits
     125 * @{
     126 */
     127
     128/** @brief W83CREG masks */
     129#define MSK_RESET  0x80
    58130#define MSK_ENASH  0x40
    59 #define MSK_DECOD  0x3F         /* memory decode bits, corresponding */
    60                                 /* to SA 18-13. SA 19 assumed to be 1 */
    61 
    62 /*-----CMDR command bits-----*/
    63 #define MSK_STP         0x01    /* stop the chip */
    64 #define MSK_STA         0x02    /* start the chip */
    65 #define MSK_TXP         0x04    /* initial txing of a frm */
    66 #define MSK_RRE         0x08    /* remote read */
    67 #define MSK_RWR         0x10    /* remote write */
    68 #define MSK_RD2         0x20    /* no DMA used */
    69 #define MSK_PG0         0x00    /* select register page 0 */
    70 #define MSK_PG1         0x40    /* select register page 1 */
    71 #define MSK_PG2         0x80    /* select register page 2 */
    72 
    73 /*-----ISR and TSR status bits-----*/
    74 #define MSK_PRX         0x01    /* rx with no error */
    75 #define MSK_PTX         0x02    /* tx with no error */
    76 #define MSK_RXE         0x04    /* rx with error */
    77 #define MSK_TXE         0x08    /* tx with error */
    78 #define MSK_OVW         0x10    /* overwrite warning */
    79 #define MSK_CNT         0x20    /* MSB of one of the tally counters is set */
    80 #define MSK_RDC         0x40    /* remote dma completed */
    81 #define MSK_RST         0x80    /* reset state indicator */
    82 
    83 /*-----DCR command bits-----*/
    84 #define MSK_WTS         0x01    /* word transfer mode selection */
    85 #define MSK_BOS         0x02    /* byte order selection */
    86 #define MSK_LAS         0x04    /* long addr selection */
    87 #define MSK_BMS         0x08    /* burst mode selection */
    88 #define MSK_ARM         0x10    /* autoinitialize remote */
    89 #define MSK_FT00        0x00    /* burst lrngth selection */
    90 #define MSK_FT01        0x20    /* burst lrngth selection */
    91 #define MSK_FT10        0x40    /* burst lrngth selection */
    92 #define MSK_FT11        0x60    /* burst lrngth selection */
    93 
    94 /*-----RCR command bits-----*/
    95 #define MSK_SEP         0x01    /* save error pkts */
    96 #define MSK_AR          0x02    /* accept runt pkt */
    97 #define MSK_AB          0x04    /* 8390 RCR */
    98 #define MSK_AM          0x08    /* accept multicast  */
    99 #define MSK_PRO         0x10    /* accept all pkt with physical adr */
    100 #define MSK_MON         0x20    /* monitor mode */
    101 
    102 /*-----TCR command bits-----*/
    103 #define MSK_CRC         0x01    /* inhibit CRC, do not append crc */
    104 #define MSK_LOOP        0x02    /* set loopback mode */
    105 #define MSK_BCST        0x04    /* Accept broadcasts */
    106 #define MSK_LB01        0x06    /* encoded loopback control */
    107 #define MSK_ATD         0x08    /* auto tx disable */
    108 #define MSK_OFST        0x10    /* collision offset enable  */
    109 
    110 /*-----receive status bits-----*/
    111 #define SMK_PRX   0x01          /* rx without error */
    112 #define SMK_CRC   0x02          /* CRC error */
    113 #define SMK_FAE   0x04          /* frame alignment error */
    114 #define SMK_FO    0x08          /* FIFO overrun */
    115 #define SMK_MPA   0x10          /* missed pkt */
    116 #define SMK_PHY   0x20          /* physical/multicase address */
    117 #define SMK_DIS   0x40          /* receiver disable. set in monitor mode */
    118 #define SMK_DEF   0x80          /* deferring */
    119 
    120 /*-----transmit status bits-----*/
    121 #define SMK_PTX   0x01          /* tx without error */
    122 #define SMK_DFR   0x02          /* non deferred tx */
    123 #define SMK_COL   0x04          /* tx collided */
    124 #define SMK_ABT   0x08          /* tx abort because of excessive collisions */
    125 #define SMK_CRS   0x10          /* carrier sense lost */
    126 #define SMK_FU    0x20          /* FIFO underrun */
    127 #define SMK_CDH   0x40          /* collision detect heartbeat */
    128 #define SMK_OWC   0x80          /* out of window collision */
     131/** @brief memory decode bits, corresponding */
     132#define MSK_DECOD  0x3F
     133
     134/** @} */
     135
     136/**
     137 * @name CMDR command bits
     138 * @{
     139 */
     140
     141/** @brief stop the chip */
     142#define MSK_STP         0x01
     143/** @brief start the chip */
     144#define MSK_STA         0x02
     145/** @brief initial txing of a frm */
     146#define MSK_TXP         0x04
     147/** @brief remote read */
     148#define MSK_RRE         0x08
     149/** @brief remote write */
     150#define MSK_RWR         0x10
     151/** @brief no DMA used */
     152#define MSK_RD2         0x20
     153/** @brief select register page 0 */
     154#define MSK_PG0         0x00
     155/** @brief select register page 1 */
     156#define MSK_PG1         0x40
     157/** @brief select register page 2 */
     158#define MSK_PG2         0x80
     159
     160/** @} */
     161
     162/**
     163 * @name ISR and TSR status bits
     164 * @{
     165 */
     166
     167/* @brief rx with no error */
     168#define MSK_PRX         0x01
     169/* @brief tx with no error */
     170#define MSK_PTX         0x02
     171/* @brief rx with error */
     172#define MSK_RXE         0x04
     173/* @brief tx with error */
     174#define MSK_TXE         0x08
     175/* @brief overwrite warning */
     176#define MSK_OVW         0x10
     177/* @brief MSB of one of the tally counters is set */
     178#define MSK_CNT         0x20
     179/* @brief remote dma completed */
     180#define MSK_RDC         0x40
     181/* @brief reset state indicator */
     182#define MSK_RST         0x80
     183
     184/** @} */
     185
     186/**
     187 * @name DCR command bits
     188 * @{
     189 */
     190
     191/** @brief word transfer mode selection */
     192#define MSK_WTS         0x01
     193/** @brief byte order selection */
     194#define MSK_BOS         0x02
     195/** @brief long addr selection */
     196#define MSK_LAS         0x04
     197/** @brief burst mode selection */
     198#define MSK_BMS         0x08
     199/** @brief autoinitialize remote */
     200#define MSK_ARM         0x10
     201/** @brief burst lrngth selection */
     202#define MSK_FT00        0x00
     203/** @brief burst lrngth selection */
     204#define MSK_FT01        0x20
     205/** @brief burst lrngth selection */
     206#define MSK_FT10        0x40
     207/** @brief burst lrngth selection */
     208#define MSK_FT11        0x60
     209
     210/** @} */
     211
     212/**
     213 * @name RCR command bits
     214 * @{
     215 */
     216
     217/** @brief save error pkts */
     218#define MSK_SEP         0x01
     219/** @brief accept runt pkt */
     220#define MSK_AR          0x02
     221/** @brief 8390 RCR */
     222#define MSK_AB          0x04
     223/** @brief accept multicast  */
     224#define MSK_AM          0x08
     225/** @brief accept all pkt with physical adr */
     226#define MSK_PRO         0x10
     227/** @brief monitor mode */
     228#define MSK_MON         0x20
     229
     230/** @} */
     231
     232/**
     233 * @name TCR command bits
     234 * @{
     235 */
     236
     237/** @brief inhibit CRC, do not append crc */
     238#define MSK_CRC         0x01
     239/** @brief set loopback mode */
     240#define MSK_LOOP        0x02
     241/** @brief Accept broadcasts */
     242#define MSK_BCST        0x04
     243/** @brief encoded loopback control */
     244#define MSK_LB01        0x06
     245/** @brief auto tx disable */
     246#define MSK_ATD         0x08
     247/** @brief collision offset enable  */
     248#define MSK_OFST        0x10
     249
     250/** @} */
     251
     252/**
     253 * @name receive status bits
     254 * @{
     255 */
     256
     257/** @brief rx without error */
     258#define SMK_PRX   0x01
     259/** @brief CRC error */
     260#define SMK_CRC   0x02
     261/** @brief frame alignment error */
     262#define SMK_FAE   0x04
     263/** @brief FIFO overrun */
     264#define SMK_FO    0x08
     265/** @brief missed pkt */
     266#define SMK_MPA   0x10
     267/** @brief physical/multicase address */
     268#define SMK_PHY   0x20
     269/** @brief receiver disable. set in monitor mode */
     270#define SMK_DIS   0x40
     271/** @brief deferring */
     272#define SMK_DEF   0x80
     273
     274/** @} */
     275
     276/**
     277 * @name transmit status bits
     278 * @{
     279 */
     280
     281/** @brief tx without error */
     282#define SMK_PTX   0x01
     283/** @brief non deferred tx */
     284#define SMK_DFR   0x02
     285/** @brief tx collided */
     286#define SMK_COL   0x04
     287/** @brief tx abort because of excessive collisions */
     288#define SMK_ABT   0x08
     289/** @brief carrier sense lost */
     290#define SMK_CRS   0x10
     291/** @brief FIFO underrun */
     292#define SMK_FU    0x20
     293/** @brief collision detect heartbeat */
     294#define SMK_CDH   0x40
     295/** @brief out of window collision */
     296#define SMK_OWC   0x80
     297
     298/** @} */
     299
     300/** @} */
    129301
    130302#endif
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