Changeset 3d4898f in rtems


Ignore:
Timestamp:
Oct 20, 2014, 2:21:06 AM (5 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.11, master
Children:
4f21badb
Parents:
8566e1fc
Message:

m68k/av5282: Fix warning

Location:
c/src/lib/libbsp/m68k/av5282
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/m68k/av5282/include/bsp.h

    r8566e1fc r3d4898f  
    1111 */
    1212
     13/**
     14 * @defgroup m68k_av5282 AV5282 Support
     15 *
     16 * @ingroup bsp_m68k
     17 *
     18 * @brief AV5282 support.
     19 */
     20
    1321#ifndef __SBav5282_BSP_H
    1422#define __SBav5282_BSP_H
     23
     24#ifndef ASM
    1525
    1626#ifdef __cplusplus
     
    7989#define UART2_IRQ_PRIORITY  5
    8090
     91/*
     92 * Prototypes for methods called from .S to alow dependency tracking
     93 */
     94void Init5282(void);
     95
    8196#ifdef __cplusplus
    8297}
    8398#endif
    8499
     100#endif /* !ASM */
    85101#endif
    86 
    87 /**
    88  * @defgroup m68k_av5282 AV5282 Support
    89  *
    90  * @ingroup bsp_m68k
    91  *
    92  * @brief AV5282 support.
    93  */
  • c/src/lib/libbsp/m68k/av5282/start/start.S

    r8566e1fc r3d4898f  
    66 *  It jumps to the BSP which is responsible for performing
    77 *  all initialization.
    8  *
    9  *  COPYRIGHT (c) 1989-1998.
     8 */
     9
     10/*
     11 *  COPYRIGHT (c) 1989-2014.
    1012 *  On-Line Applications Research Corporation (OAR).
    1113 *
     
    1517 */
    1618
     19#include <bsp.h>
    1720#include <rtems/asm.h>
    1821
  • c/src/lib/libbsp/m68k/av5282/startup/init5282.c

    r8566e1fc r3d4898f  
    88 */
    99
    10 #include <rtems.h>
    1110#include <bsp.h>
    12 #define m68k_set_cacr(_cacr) __asm__ volatile ("movec %0,%%cacr" : : "d" (_cacr))
    13 #define m68k_set_acr0(_acr0) __asm__ volatile ("movec %0,%%acr0" : : "d" (_acr0))
    14 #define m68k_set_acr1(_acr1) __asm__ volatile ("movec %0,%%acr1" : : "d" (_acr1))
    15 #define MM_SDRAM_BASE           (0x00000000)
     11
     12#define m68k_set_cacr(_cacr) \
     13    __asm__ volatile ("movec %0,%%cacr" : : "d" (_cacr))
     14#define m68k_set_acr0(_acr0) \
     15    __asm__ volatile ("movec %0,%%acr0" : : "d" (_acr0))
     16#define m68k_set_acr1(_acr1) \
     17    __asm__ volatile ("movec %0,%%acr1" : : "d" (_acr1))
     18#define MM_SDRAM_BASE    (0x00000000)
    1619
    1720/*
     
    4245    MCF5282_CS0_CSCR =(((0xf)&0x0F)<<10)|(1<<8)|(0x80);
    4346
    44         /*Setup the SDRAM  */
    45         for(x=0; x<20000; x++)
    46         {
    47                 temp +=1;
    48         }
    49         MCF5282_SDRAMC_DCR  = 0x00000239;
    50         MCF5282_SDRAMC_DACR0 = 0x00001320;
    51         MCF5282_SDRAMC_DMR0 = (0x00FC0000) | (0x00000001);
    52         for(x=0; x<20000; x++)
    53         {
    54                 temp +=1;
    55         }
    56         /* set ip ( bit 3 ) in dacr */
    57         MCF5282_SDRAMC_DACR0 |= (0x00000008) ;
    58         /* init precharge */
    59         *((short *)MM_SDRAM_BASE) = 0;
    60         /* set RE in dacr */
    61         MCF5282_SDRAMC_DACR0 |= (0x00008000);
    62         /* wait */
    63         for(x=0; x<20000; x++)
    64         {
    65                 temp +=1;
    66         }
    67         /* issue IMRS */
    68         MCF5282_SDRAMC_DACR0 |= (0x00000040);
    69         *((short *)MM_SDRAM_BASE) = 0x0000;
    70         for(x=0; x<60000; x++)
    71         {
    72                 temp +=1;
    73         }
    74         *((unsigned long*)MM_SDRAM_BASE)=0x12345678;
     47  /*Setup the SDRAM  */
     48  for(x=0; x<20000; x++) {
     49    temp +=1;
     50  }
     51  MCF5282_SDRAMC_DCR  = 0x00000239;
     52  MCF5282_SDRAMC_DACR0 = 0x00001320;
     53  MCF5282_SDRAMC_DMR0 = (0x00FC0000) | (0x00000001);
     54  for(x=0; x<20000; x++) {
     55    temp +=1;
     56  }
     57  /* set ip ( bit 3 ) in dacr */
     58  MCF5282_SDRAMC_DACR0 |= (0x00000008) ;
     59  /* init precharge */
     60  *((short *)MM_SDRAM_BASE) = 0;
     61  /* set RE in dacr */
     62  MCF5282_SDRAMC_DACR0 |= (0x00008000);
     63  /* wait */
     64  for(x=0; x<20000; x++) {
     65    temp +=1;
     66  }
     67  /* issue IMRS */
     68  MCF5282_SDRAMC_DACR0 |= (0x00000040);
     69  *((short *)MM_SDRAM_BASE) = 0x0000;
     70  for(x=0; x<60000; x++) {
     71    temp +=1;
     72  }
     73  *((unsigned long*)MM_SDRAM_BASE)=0x12345678;
    7574
    7675    /* Copy the interrupt vector table to address 0x0 in SDRAM */
     
    7978        uint32_t *intvec = (uint32_t *)0x0;
    8079        register int i;
    81         for (i = 0; i < 256; i++)
    82         {
     80        for (i = 0; i < 256; i++) {
    8381            *(intvec++) = *(inttab++);
    8482        }
    8583    }
    86         /*
     84    /*
    8785     * Copy data, clear BSS and call boot_card()
    8886     */
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