Changeset 3d34e70f in rtems
- Timestamp:
- 03/07/06 20:47:24 (18 years ago)
- Children:
- ec24e126
- Parents:
- dda09e3b
- Location:
- cpukit/score
- Files:
-
- 5 edited
Legend:
- Unmodified
- Added
- Removed
-
cpukit/score/ChangeLog
rdda09e3b r3d34e70f 1 2006-03-07 Joel Sherrill <joel@OARcorp.com> 2 3 PR 866/rtems 4 * include/rtems/system.h, include/rtems/score/isr.h, 5 inline/rtems/score/thread.inl, macros/rtems/score/thread.inl: Added 6 memory barriers to enter and exit of dispatching and interrupt 7 critical sections so GCC will not optimize and reorder code out of a 8 critical section. 9 1 10 2005-09-01 Joel Sherrill <joel@OARcorp.com> 2 11 -
cpukit/score/include/rtems/score/isr.h
rdda09e3b r3d34e70f 112 112 113 113 #define _ISR_Disable( _level ) \ 114 _CPU_ISR_Disable( _level ) 114 do { \ 115 _CPU_ISR_Disable( _level ); \ 116 RTEMS_COMPILER_MEMORY_BARRIER(); \ 117 } while (0) 115 118 116 119 /* … … 125 128 126 129 #define _ISR_Enable( _level ) \ 127 _CPU_ISR_Enable( _level ) 130 do { \ 131 RTEMS_COMPILER_MEMORY_BARRIER(); \ 132 _CPU_ISR_Enable( _level ); \ 133 } while (0) 128 134 129 135 /* … … 145 151 146 152 #define _ISR_Flash( _level ) \ 147 _CPU_ISR_Flash( _level ) 153 do { \ 154 RTEMS_COMPILER_MEMORY_BARRIER(); \ 155 _CPU_ISR_Flash( _level ); \ 156 RTEMS_COMPILER_MEMORY_BARRIER(); \ 157 } while (0) 148 158 149 159 /* -
cpukit/score/include/rtems/system.h
rdda09e3b r3d34e70f 103 103 104 104 /* 105 * The following macro is a compiler specific way to ensure that memory 106 * writes are not reordered around certian points. This specifically can 107 * impact interrupt disable and thread dispatching critical sections. 108 */ 109 #ifdef __GNUC__ 110 #define RTEMS_COMPILER_MEMORY_BARRIER() asm volatile("" ::: "memory") 111 #else 112 #define RTEMS_COMPILER_MEMORY_BARRIER() 113 #endif 114 115 /* 105 116 * The following are used by the POSIX implementation to catch bad paths. 106 117 */ -
cpukit/score/inline/rtems/score/thread.inl
rdda09e3b r3d34e70f 185 185 { 186 186 _Thread_Dispatch_disable_level += 1; 187 RTEMS_COMPILER_MEMORY_BARRIER(); 187 188 } 188 189 … … 202 203 RTEMS_INLINE_ROUTINE void _Thread_Enable_dispatch() 203 204 { 205 RTEMS_COMPILER_MEMORY_BARRIER(); 204 206 if ( (--_Thread_Dispatch_disable_level) == 0 ) 205 207 _Thread_Dispatch(); … … 224 226 RTEMS_INLINE_ROUTINE void _Thread_Unnest_dispatch( void ) 225 227 { 228 RTEMS_COMPILER_MEMORY_BARRIER(); 226 229 _Thread_Dispatch_disable_level -= 1; 227 230 } -
cpukit/score/macros/rtems/score/thread.inl
rdda09e3b r3d34e70f 127 127 128 128 #define _Thread_Disable_dispatch() \ 129 _Thread_Dispatch_disable_level += 1 129 do { \ 130 _Thread_Dispatch_disable_level += 1; \ 131 RTEMS_COMPILER_MEMORY_BARRIER(); \ 132 } while (0) 130 133 131 134 /*PAGE … … 137 140 #if ( CPU_INLINE_ENABLE_DISPATCH == TRUE ) 138 141 #define _Thread_Enable_dispatch() \ 139 { if ( (--_Thread_Dispatch_disable_level) == 0 ) \ 140 _Thread_Dispatch(); \ 141 } 142 do { \ 143 RTEMS_COMPILER_MEMORY_BARRIER(); \ 144 if ( (--_Thread_Dispatch_disable_level) == 0 ) \ 145 _Thread_Dispatch(); \ 146 } while (0) 142 147 #endif 143 148 … … 153 158 154 159 #define _Thread_Unnest_dispatch() \ 155 _Thread_Dispatch_disable_level -= 1 160 do { \ 161 RTEMS_COMPILER_MEMORY_BARRIER(); \ 162 _Thread_Dispatch_disable_level -= 1; \ 163 } while (0) 156 164 157 165 /*PAGE
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