Changeset 3d34e70f in rtems


Ignore:
Timestamp:
03/07/06 20:47:24 (18 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Children:
ec24e126
Parents:
dda09e3b
Message:

2006-03-07 Joel Sherrill <joel@…>

PR 866/rtems

  • include/rtems/system.h, include/rtems/score/isr.h, inline/rtems/score/thread.inl, macros/rtems/score/thread.inl: Added memory barriers to enter and exit of dispatching and interrupt critical sections so GCC will not optimize and reorder code out of a critical section.
Location:
cpukit/score
Files:
5 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/ChangeLog

    rdda09e3b r3d34e70f  
     12006-03-07      Joel Sherrill <joel@OARcorp.com>
     2
     3        PR 866/rtems
     4        * include/rtems/system.h, include/rtems/score/isr.h,
     5        inline/rtems/score/thread.inl, macros/rtems/score/thread.inl: Added
     6        memory barriers to enter and exit of dispatching and interrupt
     7        critical sections so GCC will not optimize and reorder code out of a
     8        critical section.
     9
    1102005-09-01      Joel Sherrill <joel@OARcorp.com>
    211
  • cpukit/score/include/rtems/score/isr.h

    rdda09e3b r3d34e70f  
    112112
    113113#define _ISR_Disable( _level ) \
    114         _CPU_ISR_Disable( _level )
     114  do { \
     115    _CPU_ISR_Disable( _level ); \
     116    RTEMS_COMPILER_MEMORY_BARRIER(); \
     117  } while (0)
    115118
    116119/*
     
    125128
    126129#define _ISR_Enable( _level ) \
    127         _CPU_ISR_Enable( _level )
     130  do { \
     131    RTEMS_COMPILER_MEMORY_BARRIER(); \
     132    _CPU_ISR_Enable( _level ); \
     133  } while (0)
    128134
    129135/*
     
    145151
    146152#define _ISR_Flash( _level ) \
    147         _CPU_ISR_Flash( _level )
     153  do { \
     154    RTEMS_COMPILER_MEMORY_BARRIER(); \
     155    _CPU_ISR_Flash( _level ); \
     156    RTEMS_COMPILER_MEMORY_BARRIER(); \
     157  } while (0)
    148158
    149159/*
  • cpukit/score/include/rtems/system.h

    rdda09e3b r3d34e70f  
    103103
    104104/*
     105 *  The following macro is a compiler specific way to ensure that memory
     106 *  writes are not reordered around certian points.  This specifically can
     107 *  impact interrupt disable and thread dispatching critical sections.
     108 */
     109#ifdef __GNUC__
     110  #define RTEMS_COMPILER_MEMORY_BARRIER() asm volatile("" ::: "memory")
     111#else
     112  #define RTEMS_COMPILER_MEMORY_BARRIER()
     113#endif
     114
     115/*
    105116 *  The following are used by the POSIX implementation to catch bad paths.
    106117 */
  • cpukit/score/inline/rtems/score/thread.inl

    rdda09e3b r3d34e70f  
    185185{
    186186  _Thread_Dispatch_disable_level += 1;
     187  RTEMS_COMPILER_MEMORY_BARRIER();
    187188}
    188189
     
    202203RTEMS_INLINE_ROUTINE void _Thread_Enable_dispatch()
    203204{
     205  RTEMS_COMPILER_MEMORY_BARRIER();
    204206  if ( (--_Thread_Dispatch_disable_level) == 0 )
    205207    _Thread_Dispatch();
     
    224226RTEMS_INLINE_ROUTINE void _Thread_Unnest_dispatch( void )
    225227{
     228  RTEMS_COMPILER_MEMORY_BARRIER();
    226229  _Thread_Dispatch_disable_level -= 1;
    227230}
  • cpukit/score/macros/rtems/score/thread.inl

    rdda09e3b r3d34e70f  
    127127
    128128#define _Thread_Disable_dispatch() \
    129   _Thread_Dispatch_disable_level += 1
     129  do { \
     130    _Thread_Dispatch_disable_level += 1; \
     131    RTEMS_COMPILER_MEMORY_BARRIER(); \
     132  } while (0)
    130133
    131134/*PAGE
     
    137140#if ( CPU_INLINE_ENABLE_DISPATCH == TRUE )
    138141#define _Thread_Enable_dispatch()  \
    139       { if ( (--_Thread_Dispatch_disable_level) == 0 ) \
    140              _Thread_Dispatch();  \
    141       }
     142  do { \
     143    RTEMS_COMPILER_MEMORY_BARRIER(); \
     144    if ( (--_Thread_Dispatch_disable_level) == 0 ) \
     145       _Thread_Dispatch(); \
     146  } while (0)
    142147#endif
    143148
     
    153158
    154159#define _Thread_Unnest_dispatch()  \
    155   _Thread_Dispatch_disable_level -= 1
     160  do { \
     161    RTEMS_COMPILER_MEMORY_BARRIER(); \
     162    _Thread_Dispatch_disable_level -= 1; \
     163  } while (0)
    156164
    157165/*PAGE
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