Changeset 3d11c1e in rtems


Ignore:
Timestamp:
Aug 1, 2018, 8:06:37 AM (12 months ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
28b8cf9b
Parents:
dee2ebb
git-author:
Sebastian Huber <sebastian.huber@…> (08/01/18 08:06:37)
git-committer:
Sebastian Huber <sebastian.huber@…> (08/02/18 07:28:23)
Message:

bsp/riscv: Fix a synchronization issue for PLIC

Update #3433.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • bsps/riscv/riscv/irq/irq.c

    rdee2ebb r3d11c1e  
    8585        RISCV_INTERRUPT_VECTOR_EXTERNAL(interrupt_index)
    8686      );
     87
    8788      plic_hart_regs->claim_complete = interrupt_index;
     89
     90      /*
     91       * FIXME: It is not clear which fence is necessary here or if a fence is
     92       * necessary at all.  The goal is that the complete signal is somehow
     93       * recognized by the PLIC before the next claim is issued.
     94       */
     95      __asm__ volatile ("fence o, i" : : : "memory");
    8896    }
    8997  } else if (mcause == (RISCV_INTERRUPT_SOFTWARE_MACHINE << 1)) {
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