Changeset 3b0f7cc in rtems


Ignore:
Timestamp:
Jun 1, 1998, 3:14:36 PM (22 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
64be9d4
Parents:
2785eab2
Message:

Added text from Erik Ivanenko <erik.ivanenko@…> describing
transition from real to protected mode and modified the spacing.

Location:
doc/supplements/i386
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • doc/supplements/i386/bsp.t

    r2785eab2 r3b0f7cc  
    2424@section Introduction
    2525
    26 An RTEMS Board Support Package (BSP) must be designed
    27 to support a particular processor and target board combination.
    28 This chapter presents a discussion of i386 specific BSP issues.
    29 For more information on developing a BSP, refer to the chapter
    30 titled Board Support Packages in the RTEMS
    31 Applications User's Guide.
     26An RTEMS Board Support Package (BSP) must be designed to support a
     27particular processor and target board combination.  This chapter presents a
     28discussion of i386 specific BSP issues.  For more information on developing
     29a BSP, refer to the chapter titled Board Support Packages in the RTEMS
     30Applications User's Guide.
    3231
    3332@ifinfo
     
    4039
    4140@itemize @bullet
    42 @item The EAX register is set to indicate the results of the
    43 processor's power-up self test.   If the self-test was not
    44 executed, the contents of this register are undefined.
    45 Otherwise, a non-zero value indicates the processor is faulty
    46 and a zero value indicates a successful self-test.
    4741
    48 @item The DX register holds a component identifier and
    49 revision level.  DH contains 3 to indicate an i386 component and
    50 DL contains a unique revision level indicator.
     42@item The EAX register is set to indicate the results of the processor's
     43power-up self test.  If the self-test was not executed, the contents of
     44this register are undefined.  Otherwise, a non-zero value indicates the
     45processor is faulty and a zero value indicates a successful self-test.
    5146
    52 @item Control register zero (CR0) is set such that the
    53 processor is in real mode with paging disabled.   Other portions
    54 of CR0 are used to indicate the presence of a numeric
    55 coprocessor.
     47@item The DX register holds a component identifier and revision level.  DH
     48contains 3 to indicate an i386 component and DL contains a unique revision
     49level indicator.
    5650
    57 @item All bits in the extended flags register (EFLAG) which
    58 are not permanently set are cleared.  This inhibits all maskable
    59 interrupts.
     51@item Control register zero (CR0) is set such that the processor is in real
     52mode with paging disabled.  Other portions of CR0 are used to indicate the
     53presence of a numeric coprocessor.
    6054
    61 @item The Interrupt Descriptor Register (IDTR) is set to point
    62 at address zero.
     55@item All bits in the extended flags register (EFLAG) which are not
     56permanently set are cleared.  This inhibits all maskable interrupts.
    6357
    64 @item All segment registers are set to zero.
     58@item The Interrupt Descriptor Register (IDTR) is set to point at address
     59zero.
    6560
    66 @item The instruction pointer is set to 0x0000FFF0.   The
    67 first instruction executed after a reset is actually at
    68 0xFFFFFFF0 because the i386 asserts the upper twelve address
    69 until the first intersegment (FAR) JMP or CALL instruction.
    70 When a JMP or CALL is executed, the upper twelve address lines
    71 are lowered and the processor begins executing in the first
    72 megabyte of memory.
    73 @end itemize
     61@item All segment registers are set to zero.
    7462
    75 Typically, an intersegment JMP to the application's
    76 initialization code is placed at address 0xFFFFFFF0.
     63@item The instruction pointer is set to 0x0000FFF0.  The first instruction
     64executed after a reset is actually at 0xFFFFFFF0 because the i386 asserts
     65the upper twelve address until the first intersegment (FAR) JMP or CALL
     66instruction.  When a JMP or CALL is executed, the upper twelve address
     67lines are lowered and the processor begins executing in the first megabyte
     68of memory.  @end itemize
     69
     70Typically, an intersegment JMP to the application's initialization code is
     71placed at address 0xFFFFFFF0.
    7772
    7873@ifinfo
    79 @node Board Support Packages Processor Initialization, Processor Dependent Information Table, Board Support Packages System Reset, Board Support Packages
    80 @end ifinfo
     74@node Board Support Packages Processor Initialization, Processor Dependent Information Table, Board Support Packages System Reset, Board Support Packages 
     75@end ifinfo 
    8176@section Processor Initialization
    8277
    83 This initialization code is responsible for
    84 initializing all data structures required by the i386 in
    85 protected mode and for actually entering protected mode.  The
    86 i386 must be placed in protected mode and the segment registers
    87 and associated selectors must be initialized before the
    88 initialize_executive directive is invoked.
     78This initialization code is responsible for initializing all data
     79structures required by the i386 in protected mode and for actually entering
     80protected mode.  The i386 must be placed in protected mode and the segment
     81registers and associated selectors must be initialized before the
     82initialize_executive directive is invoked.
    8983
    90 The initialization code is responsible for
    91 initializing the Global Descriptor Table such that the i386 is
    92 in the thirty-two bit flat memory model with paging disabled.
    93 In this mode, the i386 automatically converts every address from
    94 a logical to a physical address each time it is used.  For more
    95 information on the memory model used by RTEMS, please refer to
    96 the Memory Model chapter in this document.
     84The initialization code is responsible for initializing the Global
     85Descriptor Table such that the i386 is in the thirty-two bit flat memory
     86model with paging disabled.  In this mode, the i386 automatically converts
     87every address from a logical to a physical address each time it is used.
     88For more information on the memory model used by RTEMS, please refer to the
     89Memory Model chapter in this document.
    9790
    98 If the application requires that the IDTR be some
    99 value besides zero, then it should set it to the required value
    100 at this point.  All tasks share the same i386 IDTR value.
    101 Because interrupts are enabled automatically by RTEMS as part of
    102 the initialize_executive directive, the IDTR MUST be set
    103 properly before this directive is invoked to insure correct
    104 interrupt vectoring.  If processor caching is to be utilized,
    105 then it should be enabled during the reset application
    106 initialization code.  The reset code which is executed before
    107 the call to initialize_executive has the following requirements:
     91Since the processor is in real mode upon reset, the processor must be
     92switched to protected mode before RTEMS can execute.  Before switching to
     93protected mode, at least one descriptor table and two descriptors must be
     94created.  Descriptors are needed for a code segment and a data segment. (
     95This will give you the flat memory model.)  The stack can be placed in a
     96normal read/write data segment, so no descriptor for the stack is needed.
     97Before the GDT can be used, the base address and limit must be loaded into
     98the GDTR register using an LGDT instruction.
    10899
    109 For more information regarding the i386s data
    110 structures and their contents, refer to Intel's 386
    111 Programmer's Reference Manual.
     100If the hardware allows an NMI to be generated, you need to create the IDT
     101and a gate for the NMI interrupt handler.  Before the IDT can be used, the
     102base address and limit for the idt must be loaded into the IDTR register
     103using an LIDT instruction.
    112104
     105Protected mode is entered by setting thye PE bit in the CR0 register.
     106Either a LMSW or MOV CR0 instruction may be used to set this bit. Because
     107the processor overlaps the interpretation of several instructions, it is
     108necessary to discard the instructions from the read-ahead cache. A JMP
     109instruction immediately after the LMSW changes the flow and empties the
     110processor if intructions which have been pre-fetched and/or decoded.  At
     111this point, the processor is in protected mode and begins to perform
     112protected mode application initialization.
     113
     114If the application requires that the IDTR be some value besides zero, then
     115it should set it to the required value at this point.  All tasks share the
     116same i386 IDTR value.  Because interrupts are enabled automatically by
     117RTEMS as part of the initialize_executive directive, the IDTR MUST be set
     118properly before this directive is invoked to insure correct interrupt
     119vectoring.  If processor caching is to be utilized, then it should be
     120enabled during the reset application initialization code.  The reset code
     121which is executed before the call to initialize_executive has the following
     122requirements:
     123
     124For more information regarding the i386s data structures and their
     125contents, refer to Intel's 386 Programmer's Reference Manual.
     126
  • doc/supplements/i386/bsp.texi

    r2785eab2 r3b0f7cc  
    2424@section Introduction
    2525
    26 An RTEMS Board Support Package (BSP) must be designed
    27 to support a particular processor and target board combination.
    28 This chapter presents a discussion of i386 specific BSP issues.
    29 For more information on developing a BSP, refer to the chapter
    30 titled Board Support Packages in the RTEMS
    31 Applications User's Guide.
     26An RTEMS Board Support Package (BSP) must be designed to support a
     27particular processor and target board combination.  This chapter presents a
     28discussion of i386 specific BSP issues.  For more information on developing
     29a BSP, refer to the chapter titled Board Support Packages in the RTEMS
     30Applications User's Guide.
    3231
    3332@ifinfo
     
    4039
    4140@itemize @bullet
    42 @item The EAX register is set to indicate the results of the
    43 processor's power-up self test.   If the self-test was not
    44 executed, the contents of this register are undefined.
    45 Otherwise, a non-zero value indicates the processor is faulty
    46 and a zero value indicates a successful self-test.
    4741
    48 @item The DX register holds a component identifier and
    49 revision level.  DH contains 3 to indicate an i386 component and
    50 DL contains a unique revision level indicator.
     42@item The EAX register is set to indicate the results of the processor's
     43power-up self test.  If the self-test was not executed, the contents of
     44this register are undefined.  Otherwise, a non-zero value indicates the
     45processor is faulty and a zero value indicates a successful self-test.
    5146
    52 @item Control register zero (CR0) is set such that the
    53 processor is in real mode with paging disabled.   Other portions
    54 of CR0 are used to indicate the presence of a numeric
    55 coprocessor.
     47@item The DX register holds a component identifier and revision level.  DH
     48contains 3 to indicate an i386 component and DL contains a unique revision
     49level indicator.
    5650
    57 @item All bits in the extended flags register (EFLAG) which
    58 are not permanently set are cleared.  This inhibits all maskable
    59 interrupts.
     51@item Control register zero (CR0) is set such that the processor is in real
     52mode with paging disabled.  Other portions of CR0 are used to indicate the
     53presence of a numeric coprocessor.
    6054
    61 @item The Interrupt Descriptor Register (IDTR) is set to point
    62 at address zero.
     55@item All bits in the extended flags register (EFLAG) which are not
     56permanently set are cleared.  This inhibits all maskable interrupts.
    6357
    64 @item All segment registers are set to zero.
     58@item The Interrupt Descriptor Register (IDTR) is set to point at address
     59zero.
    6560
    66 @item The instruction pointer is set to 0x0000FFF0.   The
    67 first instruction executed after a reset is actually at
    68 0xFFFFFFF0 because the i386 asserts the upper twelve address
    69 until the first intersegment (FAR) JMP or CALL instruction.
    70 When a JMP or CALL is executed, the upper twelve address lines
    71 are lowered and the processor begins executing in the first
    72 megabyte of memory.
    73 @end itemize
     61@item All segment registers are set to zero.
    7462
    75 Typically, an intersegment JMP to the application's
    76 initialization code is placed at address 0xFFFFFFF0.
     63@item The instruction pointer is set to 0x0000FFF0.  The first instruction
     64executed after a reset is actually at 0xFFFFFFF0 because the i386 asserts
     65the upper twelve address until the first intersegment (FAR) JMP or CALL
     66instruction.  When a JMP or CALL is executed, the upper twelve address
     67lines are lowered and the processor begins executing in the first megabyte
     68of memory.  @end itemize
     69
     70Typically, an intersegment JMP to the application's initialization code is
     71placed at address 0xFFFFFFF0.
    7772
    7873@ifinfo
    79 @node Board Support Packages Processor Initialization, Processor Dependent Information Table, Board Support Packages System Reset, Board Support Packages
    80 @end ifinfo
     74@node Board Support Packages Processor Initialization, Processor Dependent Information Table, Board Support Packages System Reset, Board Support Packages 
     75@end ifinfo 
    8176@section Processor Initialization
    8277
    83 This initialization code is responsible for
    84 initializing all data structures required by the i386 in
    85 protected mode and for actually entering protected mode.  The
    86 i386 must be placed in protected mode and the segment registers
    87 and associated selectors must be initialized before the
    88 initialize_executive directive is invoked.
     78This initialization code is responsible for initializing all data
     79structures required by the i386 in protected mode and for actually entering
     80protected mode.  The i386 must be placed in protected mode and the segment
     81registers and associated selectors must be initialized before the
     82initialize_executive directive is invoked.
    8983
    90 The initialization code is responsible for
    91 initializing the Global Descriptor Table such that the i386 is
    92 in the thirty-two bit flat memory model with paging disabled.
    93 In this mode, the i386 automatically converts every address from
    94 a logical to a physical address each time it is used.  For more
    95 information on the memory model used by RTEMS, please refer to
    96 the Memory Model chapter in this document.
     84The initialization code is responsible for initializing the Global
     85Descriptor Table such that the i386 is in the thirty-two bit flat memory
     86model with paging disabled.  In this mode, the i386 automatically converts
     87every address from a logical to a physical address each time it is used.
     88For more information on the memory model used by RTEMS, please refer to the
     89Memory Model chapter in this document.
    9790
    98 If the application requires that the IDTR be some
    99 value besides zero, then it should set it to the required value
    100 at this point.  All tasks share the same i386 IDTR value.
    101 Because interrupts are enabled automatically by RTEMS as part of
    102 the initialize_executive directive, the IDTR MUST be set
    103 properly before this directive is invoked to insure correct
    104 interrupt vectoring.  If processor caching is to be utilized,
    105 then it should be enabled during the reset application
    106 initialization code.  The reset code which is executed before
    107 the call to initialize_executive has the following requirements:
     91Since the processor is in real mode upon reset, the processor must be
     92switched to protected mode before RTEMS can execute.  Before switching to
     93protected mode, at least one descriptor table and two descriptors must be
     94created.  Descriptors are needed for a code segment and a data segment. (
     95This will give you the flat memory model.)  The stack can be placed in a
     96normal read/write data segment, so no descriptor for the stack is needed.
     97Before the GDT can be used, the base address and limit must be loaded into
     98the GDTR register using an LGDT instruction.
    10899
    109 For more information regarding the i386s data
    110 structures and their contents, refer to Intel's 386
    111 Programmer's Reference Manual.
     100If the hardware allows an NMI to be generated, you need to create the IDT
     101and a gate for the NMI interrupt handler.  Before the IDT can be used, the
     102base address and limit for the idt must be loaded into the IDTR register
     103using an LIDT instruction.
    112104
     105Protected mode is entered by setting thye PE bit in the CR0 register.
     106Either a LMSW or MOV CR0 instruction may be used to set this bit. Because
     107the processor overlaps the interpretation of several instructions, it is
     108necessary to discard the instructions from the read-ahead cache. A JMP
     109instruction immediately after the LMSW changes the flow and empties the
     110processor if intructions which have been pre-fetched and/or decoded.  At
     111this point, the processor is in protected mode and begins to perform
     112protected mode application initialization.
     113
     114If the application requires that the IDTR be some value besides zero, then
     115it should set it to the required value at this point.  All tasks share the
     116same i386 IDTR value.  Because interrupts are enabled automatically by
     117RTEMS as part of the initialize_executive directive, the IDTR MUST be set
     118properly before this directive is invoked to insure correct interrupt
     119vectoring.  If processor caching is to be utilized, then it should be
     120enabled during the reset application initialization code.  The reset code
     121which is executed before the call to initialize_executive has the following
     122requirements:
     123
     124For more information regarding the i386s data structures and their
     125contents, refer to Intel's 386 Programmer's Reference Manual.
     126
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