Changeset 3a4ae6c in rtems for cpukit/score/cpu/unix
- Timestamp:
- Sep 11, 1995, 7:35:39 PM (26 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- ced11f99
- Parents:
- 5072b07
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
cpukit/score/cpu/unix/cpu.c
r5072b07 r3a4ae6c 18 18 19 19 #include <rtems/system.h> 20 #include <rtems/ isr.h>20 #include <rtems/core/isr.h> 21 21 22 22 #include <stdio.h> … … 187 187 } 188 188 189 /*PAGE 190 * 191 * _CPU_ISR_Get_level 192 */ 193 194 unsigned32 _CPU_ISR_Get_level( void ) 195 { 196 sigset_t sigset; 197 198 sigprocmask( 0, 0, &sigset ); 199 200 /* 201 * This is an educated guess based on ONLY ONE of the signals we 202 * disable/enable to mask ISRs. 203 */ 204 205 if ( sigismember( &sigset, SIGUSR1 ) ) 206 return 1; 207 else 208 return 0; 209 } 210 189 211 /* _CPU_Initialize 190 212 * … … 199 221 void _CPU_Initialize( 200 222 rtems_cpu_table *cpu_table, 201 void (*thread_dispatch) /* ignored on this CPU */ 202 ) 203 { 204 if ( cpu_table == NULL ) 205 _CPU_Fatal_halt( RTEMS_NOT_CONFIGURED ); 206 223 void (*thread_dispatch) /* ignored on this CPU */ 224 ) 225 { 207 226 /* 208 227 * The thread_dispatch argument is the address of the entry point
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