Changeset 39c8fdb in rtems for c/src/lib/libcpu/arm


Ignore:
Timestamp:
Jan 12, 2010, 3:03:22 PM (10 years ago)
Author:
Thomas Doerfler <Thomas.Doerfler@…>
Branches:
4.10, 4.11, master
Children:
61df726
Parents:
29a3d72
Message:

add support for lpc32xx

Location:
c/src/lib/libcpu/arm
Files:
3 added
4 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/arm/ChangeLog

    r29a3d72 r39c8fdb  
     12010-01-12      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * shared/include/arm-cp15.h, shared/include/cache.h,
     4        shared/include/cache_.h: New files.
     5        * Makefile.am, preinstall.am: Update for new files.
     6        * shared/arm920/mmu.c: Include and use <libcpu/arm-cp15.h>.
     7
    182009-11-30      Fernando Nicodemos <fgnicodemos@terra.com.br>
    29
  • c/src/lib/libcpu/arm/Makefile.am

    r29a3d72 r39c8fdb  
    1616
    1717include_libcpu_HEADERS = shared/include/mmu.h
     18include_libcpu_HEADERS += shared/include/arm-cp15.h
    1819
    1920## shared/arm920
  • c/src/lib/libcpu/arm/preinstall.am

    r29a3d72 r39c8fdb  
    2828        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/mmu.h
    2929PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/mmu.h
     30
     31$(PROJECT_INCLUDE)/libcpu/arm-cp15.h: shared/include/arm-cp15.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
     32        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/arm-cp15.h
     33PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/arm-cp15.h
    3034endif
    3135if pxa255
  • c/src/lib/libcpu/arm/shared/arm920/mmu.c

    r29a3d72 r39c8fdb  
    88 */
    99#include <libcpu/mmu.h>
     10#include <libcpu/arm-cp15.h>
    1011
    1112typedef uint32_t mmu_lvl1_t;
     
    1314extern uint32_t _ttbl_base;
    1415
    15 static inline uint32_t mmu_get_id(void);
    16 static inline uint32_t mmu_get_ctrl(void);
    17 static inline void mmu_set_ctrl(uint32_t val);
    18 static inline uint32_t mmu_get_trans_tbl(void);
    19 static inline void mmu_set_trans_tbl(uint32_t val);
    20 static inline uint32_t mmu_get_domain_ctrl(void);
    21 static inline void mmu_set_domain_ctrl(uint32_t val);
    22 static inline uint32_t mmu_get_fault_stat(void);
    23 static inline void mmu_set_fault_stat(uint32_t val);
    24 static inline uint32_t mmu_get_fault_addr(void);
    25 static inline void mmu_set_fault_addr(uint32_t val);
    26 static inline void mmu_set_cache_inval(void);
    27 static inline void mmu_set_tlb_inval(void);
    28 static inline uint32_t mmu_get_proc_id(void);
    29 static inline void mmu_set_proc_id(uint32_t val);
    3016static void mmu_set_map_inval(mmu_lvl1_t *base);
    3117
     
    5541#define MMU_SECT_AP_ALL (0x3 << 10)
    5642
    57 #define NOP ( { asm volatile ("nop\n" ); } )
    58 
    5943void mmu_init(mmu_sect_map_t *map)
    6044{
     
    6347
    6448    /* flush the cache and TLB */
    65     mmu_set_cache_inval();
    66     mmu_set_tlb_inval();
     49    arm_cp15_cache_invalidate();
     50    arm_cp15_tlb_invalidate();
    6751
    6852    /* set manage mode access for all domains */
    69     mmu_set_domain_ctrl(0xffffffff);
     53    arm_cp15_set_domain_access_control(0xffffffff);
    7054
    7155    lvl1_base = (mmu_lvl1_t *)&_ttbl_base;
     
    7357    /* set up the trans table */
    7458    mmu_set_map_inval(lvl1_base);
    75     mmu_set_trans_tbl((uint32_t) lvl1_base);
     59    arm_cp15_set_translation_table_base(lvl1_base);
    7660
    7761    /* create a 1:1 mapping of the entire address space */
     
    121105
    122106    /* flush the cache and TLB */
    123     mmu_set_cache_inval();
    124     mmu_set_tlb_inval();
    125 
    126     NOP;
    127     NOP;
     107    arm_cp15_cache_invalidate();
     108    arm_cp15_tlb_invalidate();
    128109
    129110    /*  I & D caches turned on */
    130     mmu_set_ctrl(MMU_CTRL_DEFAULT |
    131                  MMU_CTRL_D_CACHE_EN |
    132                  MMU_CTRL_I_CACHE_EN |
    133                  MMU_CTRL_ALIGN_FAULT_EN |
    134                  MMU_CTRL_LITTLE_ENDIAN |
    135                  MMU_CTRL_MMU_EN);
    136 
    137     NOP;
    138     NOP;
     111    arm_cp15_set_control(MMU_CTRL_DEFAULT |
     112                         MMU_CTRL_D_CACHE_EN |
     113                         MMU_CTRL_I_CACHE_EN |
     114                         MMU_CTRL_ALIGN_FAULT_EN |
     115                         MMU_CTRL_LITTLE_ENDIAN |
     116                         MMU_CTRL_MMU_EN);
    139117
    140118    return;
    141 }
    142 
    143 
    144 static inline uint32_t mmu_get_id(void)
    145 {
    146     uint32_t val;
    147     asm volatile ("msr 15, 0, %0, cr0, cr0\n" : "=r" (val));
    148     return val;
    149 }
    150 
    151 static inline uint32_t mmu_get_ctrl(void)
    152 {
    153     uint32_t val;
    154     asm volatile ("mrc 15, 0, %0, cr1, cr0\n" : "=r" (val));
    155     return val;
    156 }
    157 
    158 static inline void mmu_set_ctrl(uint32_t val)
    159 {
    160     asm volatile ("mcr 15, 0, %0, cr1, cr0, 0\n" : :"r" (val));
    161 }
    162 
    163 static inline uint32_t mmu_get_trans_tbl(void)
    164 {
    165     uint32_t val;
    166     asm volatile ("msr 15, 0, %0, cr2, cr0\n" : "=r" (val));
    167     return val;
    168 }
    169 
    170 static inline void mmu_set_trans_tbl(uint32_t val)
    171 {
    172     asm volatile ("mcr 15, 0, %0, cr2, cr0, 0\n" : :"r" (val));
    173 }
    174 
    175 static inline uint32_t mmu_get_domain_ctrl(void)
    176 {
    177     uint32_t val;
    178     asm volatile ("msr 15, 0, %0, cr3, cr0\n" : "=r" (val));
    179     return val;
    180 }
    181 
    182 static inline void mmu_set_domain_ctrl(uint32_t val)
    183 {
    184     asm volatile ("mcr 15, 0, %0, cr3, cr0, 0\n" : :"r" (val));
    185 }
    186 
    187 static inline uint32_t mmu_get_fault_stat(void)
    188 {
    189     uint32_t val;
    190     asm volatile ("msr 15, 0, %0, cr5, cr0\n" : "=r" (val));
    191     return val;
    192 }
    193 
    194 static inline void mmu_set_fault_stat(uint32_t val)
    195 {
    196     asm volatile ("mcr 15, 0, %0, cr5, cr0, 0\n" : :"r" (val));
    197 }
    198 
    199 static inline uint32_t mmu_get_fault_addr(void)
    200 {
    201     uint32_t val;
    202     asm volatile ("msr 15, 0, %0, cr6, cr0\n" : "=r" (val));
    203     return val;
    204 }
    205 
    206 static inline void mmu_set_fault_addr(uint32_t val)
    207 {
    208     asm volatile ("mcr 15, 0, %0, cr6, cr0, 0\n" : :"r" (val));
    209 }
    210 
    211 static inline void mmu_set_cache_inval(void)
    212 {
    213     uint32_t val = 0;
    214     asm volatile ("mcr 15, 0, %0, cr7, cr7, 0\n" : :"r" (val));
    215 }
    216 
    217 static inline void mmu_set_tlb_inval(void)
    218 {
    219     uint32_t val = 0;
    220     asm volatile ("mcr 15, 0, %0, cr8, cr7, 0\n" : :"r" (val));
    221 }
    222 
    223 static inline uint32_t mmu_get_proc_id(void)
    224 {
    225     uint32_t val;
    226     asm volatile ("msr 15, 0, %0, cr13, cr0\n" : "=r" (val));
    227     return val;
    228 }
    229 
    230 static inline void mmu_set_proc_id(uint32_t val)
    231 {
    232     asm volatile ("mcr 15, 0, %0, cr13, cr0, 0\n" : :"r" (val));
    233119}
    234120
     
    242128}
    243129
    244 
    245130void mmu_set_cpu_async_mode(void)
    246131{
    247132    uint32_t reg;
    248     reg = mmu_get_ctrl();
     133    reg = arm_cp15_get_control();
    249134    reg |= 0xc0000000;
    250     mmu_set_ctrl(reg);
     135    arm_cp15_set_control(reg);
    251136}
    252 
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