Changeset 39c8fdb in rtems


Ignore:
Timestamp:
Jan 12, 2010, 3:03:22 PM (10 years ago)
Author:
Thomas Doerfler <Thomas.Doerfler@…>
Branches:
4.10, 4.11, master
Children:
61df726
Parents:
29a3d72
Message:

add support for lpc32xx

Files:
7 added
33 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/lpc24xx/ChangeLog

    r29a3d72 r39c8fdb  
     12010-01-12      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * include/lpc-ethernet-config.h: New file.
     4        * network/network.c: Removed file.
     5        * Makefile.am, configure.ac, preinstall.am, include/bsp.h,
     6        include/lpc24xx.h: Changes throughout.
     7
    182009-12-15      Sebastian Huber <sebastian.huber@embedded-brains.de>
    29
  • c/src/lib/libbsp/arm/lpc24xx/Makefile.am

    r29a3d72 r39c8fdb  
    1313
    1414include_bspdir = $(includedir)/bsp
     15include_libcpudir = $(includedir)/libcpu
    1516
    1617dist_project_lib_DATA = bsp_specs
     
    4546include_bsp_HEADERS += include/io.h
    4647include_bsp_HEADERS += include/lpc-clock-config.h
     48include_bsp_HEADERS += include/lpc-ethernet-config.h
    4749
    4850include_HEADERS += ../../shared/include/tm27.h
     51
     52include_libcpu_HEADERS = ../../../libcpu/arm/shared/include/cache.h
    4953
    5054###############################################################################
     
    7377
    7478libbsp_a_SOURCES =
     79libbsp_a_CPPFLAGS =
     80libbsp_a_LIBADD =
    7581
    7682# Shared
     
    125131libbsp_a_SOURCES += i2c/i2c.c
    126132
     133# Cache
     134libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c \
     135        ../../../libcpu/arm/shared/cache/cache_.h
     136libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include
     137
    127138# Start hooks (FIXME: This is brittle.)
    128139libbsp_a_SOURCES += startup/bspstarthooks.c
    129 bspstarthooks.o: startup/bspstarthooks.c
    130         $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS:-mthumb=) \
    131         -MT bspstarthooks.o -MD -MP -MF $(DEPDIR)/bspstarthooks.Tpo -c -o bspstarthooks.o \
     140libbsp_a-bspstarthooks.o: startup/bspstarthooks.c
     141        $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libbsp_a_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS:-mthumb=) \
     142        -MT libbsp_a-bspstarthooks.o -MD -MP -MF $(DEPDIR)/libbsp_a-bspstarthooks.Tpo -c -o libbsp_a-bspstarthooks.o \
    132143        `test -f 'startup/bspstarthooks.c' || echo '$(srcdir)/'`startup/bspstarthooks.c
     144        $(am__mv) $(DEPDIR)/libbsp_a-bspstarthooks.Tpo $(DEPDIR)/libbsp_a-bspstarthooks.Po
    133145
    134146###############################################################################
     
    140152noinst_PROGRAMS = network.rel
    141153
    142 network_rel_SOURCES = network/network.c
     154network_rel_SOURCES = ../shared/lpc/network/lpc-ethernet.c
    143155network_rel_CPPFLAGS = $(AM_CPPFLAGS) -D__INSIDE_RTEMS_BSD_TCPIP_STACK__ -D__BSD_VISIBLE
    144156network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
    145157
    146 libbsp_a_LIBADD = network.rel
     158libbsp_a_LIBADD += network.rel
    147159
    148160endif
  • c/src/lib/libbsp/arm/lpc24xx/configure.ac

    r29a3d72 r39c8fdb  
    3434RTEMS_BSPOPTS_HELP([LPC24XX_UART_BAUD],[baud for UARTs])
    3535
    36 RTEMS_BSPOPTS_SET([LPC24XX_ETHERNET_RMII],[lpc24xx_ncs_*],[1])
     36RTEMS_BSPOPTS_SET([LPC24XX_ETHERNET_RMII],[*],[])
    3737RTEMS_BSPOPTS_HELP([LPC24XX_ETHERNET_RMII],[enable RMII for Ethernet])
    3838
  • c/src/lib/libbsp/arm/lpc24xx/include/bsp.h

    r29a3d72 r39c8fdb  
    5151 * @brief Network driver attach and detach function.
    5252 */
    53 int lpc24xx_eth_attach_detach(
     53int lpc_eth_attach_detach(
    5454  struct rtems_bsdnet_ifconfig *config,
    5555  int attaching
     
    5959 * @brief Standard network driver attach and detach function.
    6060 */
    61 #define RTEMS_BSP_NETWORK_DRIVER_ATTACH lpc24xx_eth_attach_detach
     61#define RTEMS_BSP_NETWORK_DRIVER_ATTACH lpc_eth_attach_detach
    6262
    6363/**
  • c/src/lib/libbsp/arm/lpc24xx/include/lpc24xx.h

    r29a3d72 r39c8fdb  
    208208
    209209/* FIOs can be accessed through WORD, HALF-WORD or BYTE. */
    210 #define FIO0DIR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x01))
    211 #define FIO1DIR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x21))
    212 #define FIO2DIR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x41))
    213 #define FIO3DIR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x61))
    214 #define FIO4DIR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x81))
    215 
    216 #define FIO0DIR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x02))
    217 #define FIO1DIR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x22))
    218 #define FIO2DIR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x42))
    219 #define FIO3DIR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x62))
    220 #define FIO4DIR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x82))
    221 
    222 #define FIO0DIR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x03))
    223 #define FIO1DIR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x23))
    224 #define FIO2DIR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x43))
    225 #define FIO3DIR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x63))
    226 #define FIO4DIR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x83))
    227 
    228 #define FIO0DIR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x04))
    229 #define FIO1DIR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x24))
    230 #define FIO2DIR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x44))
    231 #define FIO3DIR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x64))
    232 #define FIO4DIR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x84))
     210#define FIO0DIR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x00))
     211#define FIO1DIR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x20))
     212#define FIO2DIR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x40))
     213#define FIO3DIR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x60))
     214#define FIO4DIR0       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x80))
     215
     216#define FIO0DIR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x01))
     217#define FIO1DIR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x21))
     218#define FIO2DIR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x41))
     219#define FIO3DIR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x61))
     220#define FIO4DIR1       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x81))
     221
     222#define FIO0DIR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x02))
     223#define FIO1DIR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x22))
     224#define FIO2DIR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x42))
     225#define FIO3DIR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x62))
     226#define FIO4DIR2       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x82))
     227
     228#define FIO0DIR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x03))
     229#define FIO1DIR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x23))
     230#define FIO2DIR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x43))
     231#define FIO3DIR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x63))
     232#define FIO4DIR3       (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x83))
    233233
    234234#define FIO0DIRL       (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x00))
     
    18381838#define GPDMA_CH_CFG_HALT 0x00040000U
    18391839
    1840 /* Ethernet (MAC) */
    1841 
    1842 typedef struct {
    1843   uint32_t start;
    1844   uint32_t control;
    1845 } lpc24xx_eth_transfer_descriptor;
    1846 
    1847 typedef struct {
    1848   uint32_t status;
    1849   uint32_t hash_crc;
    1850 } lpc24xx_eth_receive_info;
    1851 
    1852 #define ETH_TRANSFER_DESCRIPTOR_SIZE 8
    1853 
    1854 #define ETH_RECEIVE_INFO_SIZE 8
    1855 
    1856 #define ETH_TRANSMIT_STATUS_SIZE 4
    1857 
    1858 /* ETH_RX_CTRL */
    1859 
    1860 #define ETH_RX_CTRL_SIZE_MASK 0x000007ffU
    1861 
    1862 #define GET_ETH_RX_CTRL_SIZE(reg) \
    1863   GET_FIELD(reg, ETH_RX_CTRL_SIZE_MASK, 0)
    1864 
    1865 #define SET_ETH_RX_CTRL_SIZE(reg, val) \
    1866   SET_FIELD(reg, val, ETH_RX_CTRL_SIZE_MASK, 0)
    1867 
    1868 #define ETH_RX_CTRL_INTERRUPT 0x80000000U
    1869 
    1870 /* ETH_RX_STAT */
    1871 
    1872 #define ETH_RX_STAT_RXSIZE_MASK 0x000007ffU
    1873 
    1874 #define GET_ETH_RX_STAT_RXSIZE(reg) \
    1875   GET_FIELD(reg, ETH_RX_STAT_RXSIZE_MASK, 0)
    1876 
    1877 #define SET_ETH_RX_STAT_RXSIZE(reg, val) \
    1878   SET_FIELD(reg, val, ETH_RX_STAT_RXSIZE_MASK, 0)
    1879 
    1880 #define ETH_RX_STAT_BYTES 0x00000100U
    1881 
    1882 #define ETH_RX_STAT_CONTROL_FRAME 0x00040000U
    1883 
    1884 #define ETH_RX_STAT_VLAN 0x00080000U
    1885 
    1886 #define ETH_RX_STAT_FAIL_FILTER 0x00100000U
    1887 
    1888 #define ETH_RX_STAT_MULTICAST 0x00200000U
    1889 
    1890 #define ETH_RX_STAT_BROADCAST 0x00400000U
    1891 
    1892 #define ETH_RX_STAT_CRC_ERROR 0x00800000U
    1893 
    1894 #define ETH_RX_STAT_SYMBOL_ERROR 0x01000000U
    1895 
    1896 #define ETH_RX_STAT_LENGTH_ERROR 0x02000000U
    1897 
    1898 #define ETH_RX_STAT_RANGE_ERROR 0x04000000U
    1899 
    1900 #define ETH_RX_STAT_ALIGNMENT_ERROR 0x08000000U
    1901 
    1902 #define ETH_RX_STAT_OVERRUN 0x10000000U
    1903 
    1904 #define ETH_RX_STAT_NO_DESCRIPTOR 0x20000000U
    1905 
    1906 #define ETH_RX_STAT_LAST_FLAG 0x40000000U
    1907 
    1908 #define ETH_RX_STAT_ERROR 0x80000000U
    1909 
    1910 /* ETH_TX_CTRL */
    1911 
    1912 #define ETH_TX_CTRL_SIZE_MASK 0x000007ffU
    1913 
    1914 #define GET_ETH_TX_CTRL_SIZE(reg) \
    1915   GET_FIELD(reg, ETH_TX_CTRL_SIZE_MASK, 0)
    1916 
    1917 #define SET_ETH_TX_CTRL_SIZE(reg, val) \
    1918   SET_FIELD(reg, val, ETH_TX_CTRL_SIZE_MASK, 0)
    1919 
    1920 #define ETH_TX_CTRL_OVERRIDE 0x04000000U
    1921 
    1922 #define ETH_TX_CTRL_HUGE 0x08000000U
    1923 
    1924 #define ETH_TX_CTRL_PAD 0x10000000U
    1925 
    1926 #define ETH_TX_CTRL_CRC 0x20000000U
    1927 
    1928 #define ETH_TX_CTRL_LAST 0x40000000U
    1929 
    1930 #define ETH_TX_CTRL_INTERRUPT 0x80000000U
    1931 
    1932 /* ETH_TX_STAT */
    1933 
    1934 #define ETH_TX_STAT_COLLISION_COUNT_MASK 0x01e00000U
    1935 
    1936 #define GET_ETH_TX_STAT_COLLISION_COUNT(reg) \
    1937   GET_FIELD(reg, ETH_TX_STAT_COLLISION_COUNT_MASK, 21)
    1938 
    1939 #define SET_ETH_TX_STAT_COLLISION_COUNT(reg, val) \
    1940   SET_FIELD(reg, val, ETH_TX_STAT_COLLISION_COUNT_MASK, 21)
    1941 
    1942 #define ETH_TX_STAT_DEFER 0x02000000U
    1943 
    1944 #define ETH_TX_STAT_EXCESSIVE_DEFER 0x04000000U
    1945 
    1946 #define ETH_TX_STAT_EXCESSIVE_COLLISION 0x08000000U
    1947 
    1948 #define ETH_TX_STAT_LATE_COLLISION 0x10000000U
    1949 
    1950 #define ETH_TX_STAT_UNDERRUN 0x20000000U
    1951 
    1952 #define ETH_TX_STAT_NO_DESCRIPTOR 0x40000000U
    1953 
    1954 #define ETH_TX_STAT_ERROR 0x80000000U
    1955 
    1956 /* ETH_INT */
    1957 
    1958 #define ETH_INT_RX_OVERRUN 0x00000001U
    1959 
    1960 #define ETH_INT_RX_ERROR 0x00000002U
    1961 
    1962 #define ETH_INT_RX_FINISHED 0x00000004U
    1963 
    1964 #define ETH_INT_RX_DONE 0x00000008U
    1965 
    1966 #define ETH_INT_TX_UNDERRUN 0x00000010U
    1967 
    1968 #define ETH_INT_TX_ERROR 0x00000020U
    1969 
    1970 #define ETH_INT_TX_FINISHED 0x00000040U
    1971 
    1972 #define ETH_INT_TX_DONE 0x00000080U
    1973 
    1974 #define ETH_INT_SOFT 0x00001000U
    1975 
    1976 #define ETH_INT_WAKEUP 0x00002000U
    1977 
    1978 /* ETH_RX_FIL_CTRL */
    1979 
    1980 #define ETH_RX_FIL_CTRL_ACCEPT_UNICAST 0x00000001U
    1981 
    1982 #define ETH_RX_FIL_CTRL_ACCEPT_BROADCAST 0x00000002U
    1983 
    1984 #define ETH_RX_FIL_CTRL_ACCEPT_MULTICAST 0x00000004U
    1985 
    1986 #define ETH_RX_FIL_CTRL_ACCEPT_UNICAST_HASH 0x00000008U
    1987 
    1988 #define ETH_RX_FIL_CTRL_ACCEPT_MULTICAST_HASH 0x00000010U
    1989 
    1990 #define ETH_RX_FIL_CTRL_ACCEPT_PERFECT 0x00000020U
    1991 
    1992 #define ETH_RX_FIL_CTRL_MAGIC_PACKET_WOL 0x00001000U
    1993 
    1994 #define ETH_RX_FIL_CTRL_RX_FILTER_WOL 0x00002000U
    1995 
    1996 /* ETH_CMD */
    1997 
    1998 #define ETH_CMD_RX_ENABLE 0x00000001U
    1999 
    2000 #define ETH_CMD_TX_ENABLE 0x00000002U
    2001 
    2002 #define ETH_CMD_REG_RESET 0x00000008U
    2003 
    2004 #define ETH_CMD_TX_RESET 0x00000010U
    2005 
    2006 #define ETH_CMD_RX_RESET 0x00000020U
    2007 
    2008 #define ETH_CMD_PASS_RUNT_FRAME 0x00000040U
    2009 
    2010 #define ETH_CMD_PASS_RX_FILTER 0X00000080U
    2011 
    2012 #define ETH_CMD_TX_FLOW_CONTROL 0x00000100U
    2013 
    2014 #define ETH_CMD_RMII 0x00000200U
    2015 
    2016 #define ETH_CMD_FULL_DUPLEX 0x00000400U
    2017 
    2018 /* ETH_STAT */
    2019 
    2020 #define ETH_STAT_RX_ACTIVE 0x00000001U
    2021 
    2022 #define ETH_STAT_TX_ACTIVE 0x00000002U
    2023 
    20241840/* AHBCFG */
    20251841
  • c/src/lib/libbsp/arm/lpc24xx/preinstall.am

    r29a3d72 r39c8fdb  
    3333        @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    3434PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     35
     36$(PROJECT_INCLUDE)/libcpu/$(dirstamp):
     37        @$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu
     38        @: > $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
     39PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
    3540
    3641$(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp)
     
    122127PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/lpc-clock-config.h
    123128
     129$(PROJECT_INCLUDE)/bsp/lpc-ethernet-config.h: include/lpc-ethernet-config.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     130        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/lpc-ethernet-config.h
     131PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/lpc-ethernet-config.h
     132
    124133$(PROJECT_INCLUDE)/tm27.h: ../../shared/include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp)
    125134        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h
    126135PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h
     136
     137$(PROJECT_INCLUDE)/libcpu/cache.h: ../../../libcpu/arm/shared/include/cache.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
     138        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/cache.h
     139PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/cache.h
    127140
    128141$(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
  • c/src/lib/libbsp/arm/lpc32xx/ChangeLog

    r29a3d72 r39c8fdb  
     12010-01-12      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * include/lpc-ethernet-config.h, include/mmu.h: New files.
     4        * Makefile.am, configure.ac, preinstall.am, include/bsp.h,
     5        include/bspopts.h.in, include/irq.h, include/lpc32xx.h, irq/irq.c,
     6        rtc/rtc-config.c, startup/bspstarthooks.c,
     7        startup/linkcmds.lpc32xx_phycore: Changes throughout.
     8
    192009-12-17      Joel Sherrill <joel.sherrill@oarcorp.com>
    210
  • c/src/lib/libbsp/arm/lpc32xx/Makefile.am

    r29a3d72 r39c8fdb  
    1313
    1414include_bspdir = $(includedir)/bsp
     15include_libcpudir = $(includedir)/libcpu
    1516
    1617dist_project_lib_DATA = bsp_specs
     
    2122
    2223include_HEADERS = include/bsp.h
     24include_HEADERS += ../../shared/include/tm27.h
    2325
    2426nodist_include_HEADERS = ../../shared/include/coverhd.h \
     
    3840include_bsp_HEADERS += include/irq-config.h
    3941include_bsp_HEADERS += include/irq.h
     42include_bsp_HEADERS += include/mmu.h
    4043include_bsp_HEADERS += include/lpc32xx.h
    4144include_bsp_HEADERS += include/lpc-clock-config.h
     45include_bsp_HEADERS += include/lpc-ethernet-config.h
    4246
    43 include_HEADERS += ../../shared/include/tm27.h
     47include_libcpu_HEADERS = ../../../libcpu/arm/shared/include/cache.h \
     48        ../../../libcpu/arm/shared/include/arm-cp15.h
    4449
    4550###############################################################################
     
    6570
    6671libbsp_a_SOURCES =
     72libbsp_a_CPPFLAGS =
     73libbsp_a_LIBADD =
    6774
    6875# Shared
     
    110117# I2C
    111118
     119# Cache
     120libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c \
     121        ../../../libcpu/arm/shared/cache/cache_.h
     122libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include
     123
    112124# Start hooks (FIXME: This is brittle.)
    113125libbsp_a_SOURCES += startup/bspstarthooks.c
    114 bspstarthooks.o: startup/bspstarthooks.c
    115         $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS:-mthumb=) \
    116         -MT bspstarthooks.o -MD -MP -MF $(DEPDIR)/bspstarthooks.Tpo -c -o bspstarthooks.o \
     126libbsp_a-bspstarthooks.o: startup/bspstarthooks.c
     127        $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libbsp_a_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS:-mthumb=) \
     128        -MT libbsp_a-bspstarthooks.o -MD -MP -MF $(DEPDIR)/libbsp_a-bspstarthooks.Tpo -c -o libbsp_a-bspstarthooks.o \
    117129        `test -f 'startup/bspstarthooks.c' || echo '$(srcdir)/'`startup/bspstarthooks.c
     130        $(am__mv) $(DEPDIR)/libbsp_a-bspstarthooks.Tpo $(DEPDIR)/libbsp_a-bspstarthooks.Po
    118131
    119132###############################################################################
     
    123136if HAS_NETWORKING
    124137
    125 # noinst_PROGRAMS = network.rel
     138noinst_PROGRAMS = network.rel
    126139
    127 # network_rel_SOURCES = network/network.c
    128 # network_rel_CPPFLAGS = $(AM_CPPFLAGS) -D__INSIDE_RTEMS_BSD_TCPIP_STACK__ -D__BSD_VISIBLE
    129 # network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
     140network_rel_SOURCES = ../shared/lpc/network/lpc-ethernet.c
     141network_rel_CPPFLAGS = $(AM_CPPFLAGS) -D__INSIDE_RTEMS_BSD_TCPIP_STACK__ -D__BSD_VISIBLE
     142network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
    130143
    131 # libbsp_a_LIBADD = network.rel
     144libbsp_a_LIBADD += network.rel
    132145
    133146endif
  • c/src/lib/libbsp/arm/lpc32xx/configure.ac

    r29a3d72 r39c8fdb  
    3434RTEMS_BSPOPTS_HELP([LPC32XX_HCLK],[AHB bus clock in Hz])
    3535
     36RTEMS_BSPOPTS_SET([LPC32XX_ETHERNET_RMII],[*],[1])
     37RTEMS_BSPOPTS_HELP([LPC32XX_ETHERNET_RMII],[enable RMII for Ethernet])
     38
    3639RTEMS_BSPOPTS_SET([LPC32XX_PERIPH_CLK],[*],[13000000U])
    3740RTEMS_BSPOPTS_HELP([LPC32XX_PERIPH_CLK],[peripheral clock in Hz])
  • c/src/lib/libbsp/arm/lpc32xx/include/bsp.h

    r29a3d72 r39c8fdb  
    5252 * @brief Network driver attach and detach function.
    5353 */
    54 int lpc32xx_eth_attach_detach(
     54int lpc_eth_attach_detach(
    5555  struct rtems_bsdnet_ifconfig *config,
    5656  int attaching
     
    6060 * @brief Standard network driver attach and detach function.
    6161 */
    62 #define RTEMS_BSP_NETWORK_DRIVER_ATTACH lpc32xx_eth_attach_detach
     62#define RTEMS_BSP_NETWORK_DRIVER_ATTACH lpc_eth_attach_detach
    6363
    6464/**
  • c/src/lib/libbsp/arm/lpc32xx/include/bspopts.h.in

    r29a3d72 r39c8fdb  
    3434#undef LPC32XX_CONFIG_UART_CLKMODE
    3535
     36/* enable RMII for Ethernet */
     37#undef LPC32XX_ETHERNET_RMII
     38
    3639/* AHB bus clock in Hz */
    3740#undef LPC32XX_HCLK
  • c/src/lib/libbsp/arm/lpc32xx/include/irq.h

    r29a3d72 r39c8fdb  
    159159lpc32xx_irq_activation_type lpc32xx_irq_get_activation_type(rtems_vector_number vector);
    160160
     161void lpc32xx_set_exception_handler(Arm_symbolic_exception_name exception, void (*handler)(void));
     162
    161163/** @} */
    162164
  • c/src/lib/libbsp/arm/lpc32xx/include/lpc32xx.h

    r29a3d72 r39c8fdb  
    9191#define LPC32XX_UART_LOOP (*(volatile uint32_t *) 0x40054008)
    9292#define LPC32XX_SW_INT (*(volatile uint32_t *) 0x400040a8)
     93#define LPC32XX_MAC_CLK_CTRL (*(volatile uint32_t *) 0x40004090)
    9394
    9495#endif /* LIBBSP_ARM_LPC32XX_LPC32XX_H */
  • c/src/lib/libbsp/arm/lpc32xx/irq/irq.c

    r29a3d72 r39c8fdb  
    2424#include <bsp/irq-generic.h>
    2525#include <bsp/lpc32xx.h>
     26#include <bsp/linker-symbols.h>
     27#include <bsp/mmu.h>
    2628
    2729/*
     
    126128static inline unsigned lpc32xx_irq_get_index(uint32_t val)
    127129{
    128   uint32_t reg;
     130  ARM_SWITCH_REGISTERS;
    129131
    130132  asm volatile (
    131     THUMB_TO_ARM
    132     "clz %1, %1\n"
    133     "rsb %1, %1, #31\n"
    134     ARM_TO_THUMB
    135     : "=&r" (reg), "=r" (val)
    136     : "1" (val)
     133    ARM_SWITCH_TO_ARM
     134    "clz %[val], %[val]\n"
     135    "rsb %[val], %[val], #31\n"
     136    ARM_SWITCH_BACK
     137    : [val] "=r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
     138    : "[val]" (val)
    137139  );
    138140
     
    305307}
    306308
     309void lpc32xx_set_exception_handler(
     310  Arm_symbolic_exception_name exception,
     311  void (*handler)(void)
     312)
     313{
     314  if ((unsigned) exception < MAX_EXCEPTIONS) {
     315    uint32_t *table = (uint32_t *) bsp_section_vector_begin + MAX_EXCEPTIONS;
     316
     317    table [exception] = (uint32_t) handler;
     318
     319    rtems_cache_flush_multiple_data_lines(NULL, 64);
     320    rtems_cache_invalidate_multiple_data_lines(NULL, 64);
     321  }
     322}
     323
    307324rtems_status_code bsp_interrupt_facility_initialize(void)
    308325{
     
    342359  lpc32xx_sic_2->atr = 0x0;
    343360
    344   _CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, arm_exc_interrupt, NULL);
     361  lpc32xx_set_exception_handler(ARM_EXCEPTION_IRQ, arm_exc_interrupt);
    345362
    346363  return RTEMS_SUCCESSFUL;
     
    351368  printk("spurious interrupt: %u\n", vector);
    352369}
    353 
    354 static void lpc32xx_irq_dump_controller(volatile lpc32xx_irq_controller *controller)
    355 {
    356   printk(
    357     "er  %08x\nrsr %08x\nsr  %08x\napr %08x\natr %08x\nitr %08x\n",
    358     controller->er,
    359     controller->rsr,
    360     controller->sr,
    361     controller->apr,
    362     controller->atr,
    363     controller->itr
    364   );
    365 }
    366 
    367 void lpc32xx_irq_dump(void)
    368 {
    369   lpc32xx_irq_dump_controller(lpc32xx_mic);
    370   lpc32xx_irq_dump_controller(lpc32xx_sic_1);
    371   lpc32xx_irq_dump_controller(lpc32xx_sic_2);
    372 }
  • c/src/lib/libbsp/arm/lpc32xx/preinstall.am

    r29a3d72 r39c8fdb  
    3434PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    3535
     36$(PROJECT_INCLUDE)/libcpu/$(dirstamp):
     37        @$(MKDIR_P) $(PROJECT_INCLUDE)/libcpu
     38        @: > $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
     39PREINSTALL_DIRS += $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
     40
    3641$(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp)
    3742        $(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs
     
    4146        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h
    4247PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h
     48
     49$(PROJECT_INCLUDE)/tm27.h: ../../shared/include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp)
     50        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h
     51PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h
    4352
    4453$(PROJECT_INCLUDE)/coverhd.h: ../../shared/include/coverhd.h $(PROJECT_INCLUDE)/$(dirstamp)
     
    94103PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
    95104
     105$(PROJECT_INCLUDE)/bsp/mmu.h: include/mmu.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     106        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/mmu.h
     107PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/mmu.h
     108
    96109$(PROJECT_INCLUDE)/bsp/lpc32xx.h: include/lpc32xx.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    97110        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/lpc32xx.h
     
    102115PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/lpc-clock-config.h
    103116
    104 $(PROJECT_INCLUDE)/tm27.h: ../../shared/include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp)
    105         $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h
    106 PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h
     117$(PROJECT_INCLUDE)/bsp/lpc-ethernet-config.h: include/lpc-ethernet-config.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     118        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/lpc-ethernet-config.h
     119PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/lpc-ethernet-config.h
     120
     121$(PROJECT_INCLUDE)/libcpu/cache.h: ../../../libcpu/arm/shared/include/cache.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
     122        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/cache.h
     123PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/cache.h
     124
     125$(PROJECT_INCLUDE)/libcpu/arm-cp15.h: ../../../libcpu/arm/shared/include/arm-cp15.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
     126        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/arm-cp15.h
     127PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/arm-cp15.h
    107128
    108129$(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp)
  • c/src/lib/libbsp/arm/lpc32xx/rtc/rtc-config.c

    r29a3d72 r39c8fdb  
    2222#include <libchip/rtc.h>
    2323
     24#include <bsp.h>
    2425#include <bsp/lpc32xx.h>
    2526
    26 #define LPC32XX_RTC_COUNT 1
     27#define LPC32XX_RTC_COUNT 1U
     28
     29#define LPC32XX_RTC_COUNTER_DELTA 0xfffffffeU
     30
     31#define LPC32XX_RTC_KEY 0xb5c13f27U
     32
     33#define LPC32XX_RTC_CTRL_FORCE_ONSW (1U << 7)
     34#define LPC32XX_RTC_CTRL_STOP (1U << 6)
     35#define LPC32XX_RTC_CTRL_RESET (1U << 4)
     36#define LPC32XX_RTC_CTRL_MATCH_1_ONSW (1U << 3)
     37#define LPC32XX_RTC_CTRL_MATCH_0_ONSW (1U << 2)
     38#define LPC32XX_RTC_CTRL_MATCH_1_INTR (1U << 1)
     39#define LPC32XX_RTC_CTRL_MATCH_0_INTR (1U << 0)
     40
     41typedef struct {
     42  uint32_t ucount;
     43  uint32_t dcount;
     44  uint32_t match0;
     45  uint32_t match1;
     46  uint32_t ctrl;
     47  uint32_t intstat;
     48  uint32_t key;
     49  uint32_t sram [32];
     50} lpc32xx_rtc_registers;
     51
     52static volatile lpc32xx_rtc_registers *const lpc32xx_rtc =
     53  (volatile lpc32xx_rtc_registers *) LPC32XX_BASE_RTC;
     54
     55static void lpc32xx_rtc_set(uint32_t val)
     56{
     57  unsigned i = LPC32XX_ARM_CLK / LPC32XX_OSCILLATOR_RTC;
     58
     59  lpc32xx_rtc->ctrl |= LPC32XX_RTC_CTRL_STOP;
     60  lpc32xx_rtc->ucount = val;
     61  lpc32xx_rtc->dcount = LPC32XX_RTC_COUNTER_DELTA - val;
     62  lpc32xx_rtc->ctrl &= ~LPC32XX_RTC_CTRL_STOP;
     63
     64  /* It needs some time before we can read the values back */
     65  while (i != 0) {
     66    asm volatile ("nop");
     67    --i;
     68  }
     69}
     70
     71static void lpc32xx_rtc_reset(void)
     72{
     73  lpc32xx_rtc->ctrl = LPC32XX_RTC_CTRL_RESET;
     74  lpc32xx_rtc->ctrl = 0;
     75  lpc32xx_rtc->key = LPC32XX_RTC_KEY;
     76  lpc32xx_rtc_set(0);
     77}
    2778
    2879static void lpc32xx_rtc_initialize(int minor)
    2980{
    30   /* TODO */
     81  uint32_t up_first = 0;
     82  uint32_t up_second = 0;
     83  uint32_t down_first = 0;
     84  uint32_t down_second = 0;
     85
     86  if (lpc32xx_rtc->key != LPC32XX_RTC_KEY) {
     87    lpc32xx_rtc_reset();
     88  }
     89
     90  do {
     91    up_first = lpc32xx_rtc->ucount;
     92    down_first = lpc32xx_rtc->dcount;
     93    up_second = lpc32xx_rtc->ucount;
     94    down_second = lpc32xx_rtc->dcount;
     95  } while (up_first != up_second || down_first != down_second);
     96
     97  if (up_first + down_first != LPC32XX_RTC_COUNTER_DELTA) {
     98    lpc32xx_rtc_reset();
     99  }
    31100}
    32101
    33102static int lpc32xx_rtc_get_time(int minor, rtems_time_of_day *tod)
    34103{
    35   /* TODO */
     104  struct timeval now = {
     105    .tv_sec = lpc32xx_rtc->ucount,
     106    .tv_usec = 0
     107  };
     108  struct tm time;
    36109
    37 #if 0
    38   tod->ticks = 0;
    39   tod->second = RTC_SEC;
    40   tod->minute = RTC_MIN;
    41   tod->hour = RTC_HOUR;
    42   tod->day = RTC_DOM;
    43   tod->month = RTC_MONTH;
    44   tod->year = RTC_YEAR;
    45 #endif
     110  gmtime_r(&now.tv_sec, &time);
    46111
    47   return 0;
     112  tod->year   = time.tm_year + 1900;
     113  tod->month  = time.tm_mon + 1;
     114  tod->day    = time.tm_mday;
     115  tod->hour   = time.tm_hour;
     116  tod->minute = time.tm_min;
     117  tod->second = time.tm_sec;
     118  tod->ticks  = 0;
     119
     120  return RTEMS_SUCCESSFUL;
    48121}
    49122
    50123static int lpc32xx_rtc_set_time(int minor, const rtems_time_of_day *tod)
    51124{
    52   /* TODO */
    53 
    54 #if 0
    55   RTC_SEC = tod->second;
    56   RTC_MIN = tod->minute;
    57   RTC_HOUR = tod->hour;
    58   RTC_DOM = tod->day;
    59   RTC_MONTH = tod->month;
    60   RTC_YEAR = tod->year;
    61 #endif
     125  lpc32xx_rtc_set(_TOD_To_seconds(tod));
    62126
    63127  return 0;
  • c/src/lib/libbsp/arm/lpc32xx/startup/bspstarthooks.c

    r29a3d72 r39c8fdb  
    2525#include <bsp/start.h>
    2626#include <bsp/lpc32xx.h>
     27#include <bsp/mmu.h>
    2728#include <bsp/linker-symbols.h>
    2829
    2930#define BSP_START_SECTION __attribute__((section(".bsp_start")))
     31#define BSP_START_DATA_SECTION __attribute__((section(".bsp_start_data")))
    3032
    3133static void BSP_START_SECTION lpc32xx_clear_bss(void)
     
    4143}
    4244
     45typedef struct {
     46  uint32_t begin;
     47  uint32_t end;
     48  uint32_t flags;
     49} lpc32xx_mmu_config;
     50
     51static const BSP_START_DATA_SECTION lpc32xx_mmu_config
     52  lpc32xx_mmu_config_table [] = {
     53  {
     54    .begin = (uint32_t) bsp_section_start_begin,
     55    .end = (uint32_t) bsp_section_start_end,
     56    .flags = LPC32XX_MMU_READ_WRITE_CACHED
     57  }, {
     58    .begin = (uint32_t) bsp_section_vector_begin,
     59    .end = (uint32_t) bsp_section_vector_end,
     60    .flags = LPC32XX_MMU_READ_WRITE_CACHED
     61  }, {
     62    .begin = (uint32_t) bsp_section_text_begin,
     63    .end = (uint32_t) bsp_section_text_end,
     64    .flags = LPC32XX_MMU_READ_WRITE_CACHED
     65  }, {
     66    .begin = (uint32_t) bsp_section_rodata_begin,
     67    .end = (uint32_t) bsp_section_rodata_end,
     68    .flags = LPC32XX_MMU_READ_ONLY_CACHED
     69  }, {
     70    .begin = (uint32_t) bsp_section_data_begin,
     71    .end = (uint32_t) bsp_section_data_end,
     72    .flags = LPC32XX_MMU_READ_WRITE
     73  }, {
     74    .begin = (uint32_t) bsp_section_fast_begin,
     75    .end = (uint32_t) bsp_section_fast_end,
     76    .flags = LPC32XX_MMU_READ_ONLY_CACHED
     77  }, {
     78    .begin = (uint32_t) bsp_section_bss_begin,
     79    .end = (uint32_t) bsp_section_bss_end,
     80    .flags = LPC32XX_MMU_READ_WRITE
     81  }, {
     82    .begin = (uint32_t) bsp_section_work_begin,
     83    .end = (uint32_t) bsp_section_work_end,
     84    .flags = LPC32XX_MMU_READ_WRITE_CACHED
     85  }, {
     86    .begin = (uint32_t) bsp_section_stack_begin,
     87    .end = (uint32_t) bsp_section_stack_end,
     88    .flags = LPC32XX_MMU_READ_WRITE_CACHED
     89  }, {
     90    .begin = 0x0U,
     91    .end = 0x100000U,
     92    .flags = LPC32XX_MMU_READ_ONLY_CACHED
     93  }, {
     94    .begin = 0x20000000U,
     95    .end = 0x200c0000U,
     96    .flags = LPC32XX_MMU_READ_WRITE
     97  }, {
     98    .begin = 0x30000000U,
     99    .end = 0x32000000U,
     100    .flags = LPC32XX_MMU_READ_WRITE
     101  }, {
     102    .begin = 0x40000000U,
     103    .end = 0x40100000U,
     104    .flags = LPC32XX_MMU_READ_WRITE
     105  }
     106};
     107
     108static void BSP_START_SECTION lpc32xx_mmu_set_entries(
     109  uint32_t *ttb,
     110  const lpc32xx_mmu_config *config
     111)
     112{
     113  uint32_t i = ARM_MMU_SECT_GET_INDEX(config->begin);
     114  uint32_t iend = ARM_MMU_SECT_GET_INDEX(ARM_MMU_SECT_MVA_ALIGN_UP(config->end));
     115
     116  if (config->begin != config->end) {
     117    while (i < iend) {
     118      ttb [i] = (i << ARM_MMU_SECT_BASE_SHIFT) | config->flags;
     119      ++i;
     120    }
     121  }
     122}
     123
     124static void BSP_START_SECTION lpc32xx_mmu_and_cache_setup(void)
     125{
     126  uint32_t const dac =
     127    ARM_CP15_DAC_DOMAIN(LPC32XX_MMU_CLIENT_DOMAIN, ARM_CP15_DAC_CLIENT);
     128  uint32_t ctrl = 0;
     129  uint32_t *const ttb = (uint32_t *) bsp_section_work_end;
     130  size_t const config_entry_count =
     131    sizeof(lpc32xx_mmu_config_table) / sizeof(lpc32xx_mmu_config_table [0]);
     132  size_t i = 0;
     133
     134  /* Disable MMU and cache, basic settings */
     135  ctrl = arm_cp15_get_control();
     136  ctrl &= ~(ARM_CP15_CTRL_I | ARM_CP15_CTRL_R | ARM_CP15_CTRL_C
     137    | ARM_CP15_CTRL_V | ARM_CP15_CTRL_M);
     138  ctrl |= ARM_CP15_CTRL_S | ARM_CP15_CTRL_A;
     139  arm_cp15_set_control(ctrl);
     140
     141  arm_cp15_cache_invalidate();
     142  arm_cp15_tlb_invalidate();
     143
     144  arm_cp15_set_domain_access_control(dac);
     145  arm_cp15_set_translation_table_base(ttb);
     146
     147  /* Initialize translation table with invalid entries */
     148  for (i = 0; i < ARM_MMU_TRANSLATION_TABLE_ENTRY_COUNT; ++i) {
     149    ttb [i] = 0;
     150  }
     151
     152  for (i = 0; i < config_entry_count; ++i) {
     153    lpc32xx_mmu_set_entries(ttb, &lpc32xx_mmu_config_table [i]);
     154  }
     155
     156  /* Enable MMU and cache */
     157  ctrl |= ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M;
     158  arm_cp15_set_control(ctrl);
     159}
     160
    43161void BSP_START_SECTION bsp_start_hook_0(void)
    44162{
     163  lpc32xx_mmu_and_cache_setup();
     164}
     165
     166void BSP_START_SECTION bsp_start_hook_1(void)
     167{
    45168  /* TODO */
    46 }
    47 
    48 void BSP_START_SECTION bsp_start_hook_1(void)
    49 {
    50   /* TODO */
    51169
    52170  /* Copy .text section */
     171  arm_cp15_instruction_cache_invalidate();
    53172  bsp_start_memcpy_arm(
    54173    (int *) bsp_section_text_begin,
     
    58177
    59178  /* Copy .rodata section */
     179  arm_cp15_instruction_cache_invalidate();
    60180  bsp_start_memcpy_arm(
    61181    (int *) bsp_section_rodata_begin,
     
    65185
    66186  /* Copy .data section */
     187  arm_cp15_instruction_cache_invalidate();
    67188  bsp_start_memcpy_arm(
    68189    (int *) bsp_section_data_begin,
     
    72193
    73194  /* Copy .fast section */
     195  arm_cp15_instruction_cache_invalidate();
    74196  bsp_start_memcpy_arm(
    75197    (int *) bsp_section_fast_begin,
  • c/src/lib/libbsp/arm/lpc32xx/startup/linkcmds.lpc32xx_phycore

    r29a3d72 r39c8fdb  
    3737MEMORY {
    3838        RAM_INT (AIW) : ORIGIN = 0x08000000, LENGTH = 256k
    39         RAM_EXT (AIW) : ORIGIN = 0x80000000, LENGTH = 64M /* SDRAM on DYCS0 */
     39        RAM_EXT (AIW) : ORIGIN = 0x80000000, LENGTH = 64M - 16k /* SDRAM on DYCS0 */
    4040        ROM_EXT (RX) : ORIGIN = 0xe0000000, LENGTH = 2M /* NOR flash on CS0 */
    4141        NIRVANA : ORIGIN = 0, LENGTH = 0
     
    5757
    5858bsp_stack_irq_size = DEFINED (bsp_stack_irq_size) ? bsp_stack_irq_size : 4096;
     59bsp_stack_abt_size = DEFINED (bsp_stack_abt_size) ? bsp_stack_abt_size : 1024;
     60
     61bsp_section_robarrier_align = DEFINED (bsp_section_robarrier_align) ? bsp_section_robarrier_align : 1M;
    5962
    6063INCLUDE linkcmds.base
  • c/src/lib/libbsp/arm/shared/abort/abort.c

    r29a3d72 r39c8fdb  
    6464{
    6565    char *mode;
    66     uint32_t prev_sp,prev_lr,cpsr,tmp;
     66    uint32_t prev_sp,prev_lr,cpsr,arm_switch_reg;
    6767    int i;
    6868
     
    7272    if(!mode) mode="unknown";
    7373
    74     asm volatile ("     MRS  %[cpsr], cpsr \n"
    75               " ORR  %[tmp], %[spsr], #0xc0 \n"
    76               " MSR  cpsr_c, %[tmp] \n"
     74    asm volatile (ARM_SWITCH_TO_ARM
     75              " MRS  %[cpsr], cpsr \n"
     76              " ORR  %[arm_switch_reg], %[spsr], #0xc0 \n"
     77              " MSR  cpsr_c, %[arm_switch_reg] \n"
    7778              " MOV  %[prev_sp], sp \n"
    7879              " MOV  %[prev_lr], lr \n"
    7980              " MSR  cpsr_c, %[cpsr] \n"
    80               : [prev_sp] "=&r" (prev_sp), [prev_lr] "=&r" (prev_lr),
    81                 [cpsr] "=&r" (cpsr), [tmp] "=&r" (tmp)
     81              ARM_SWITCH_BACK
     82              : [arm_switch_reg] "=&r" (arm_switch_reg), [prev_sp] "=&r" (prev_sp), [prev_lr] "=&r" (prev_lr),
     83                [cpsr] "=&r" (cpsr)
    8284              : [spsr] "r" (spsr)
    8385              : "cc");
  • c/src/lib/libbsp/arm/shared/abort/simple_abort.c

    r29a3d72 r39c8fdb  
    5757{
    5858  char *mode;
    59   uint32_t prev_sp,prev_lr,cpsr,tmp;
     59  uint32_t prev_sp,prev_lr,cpsr,arm_switch_reg;
    6060  int i, j;
    6161
     
    6666
    6767  asm volatile (
    68     THUMB_TO_ARM
     68    ARM_SWITCH_TO_ARM
    6969    "mrs %[cpsr], cpsr\n"
    70     "orr %[tmp], %[spsr], #0xc0\n"
    71     "msr cpsr_c, %[tmp]\n"
     70    "orr %[arm_switch_reg], %[spsr], #0xc0\n"
     71    "msr cpsr_c, %[arm_switch_reg]\n"
    7272    "mov %[prev_sp], sp\n"
    7373    "mov %[prev_lr], lr\n"
    7474    "msr cpsr_c, %[cpsr]\n"
    75     ARM_TO_THUMB
     75    ARM_SWITCH_BACK
    7676    : [prev_sp] "=&r" (prev_sp), [prev_lr] "=&r" (prev_lr),
    77       [cpsr] "=&r" (cpsr), [tmp] "=&r" (tmp)
     77      [cpsr] "=&r" (cpsr), [arm_switch_reg] "=&r" (arm_switch_reg)
    7878    : [spsr] "r" (spsr)
    7979    : "cc"
  • c/src/lib/libbsp/arm/shared/include/linker-symbols.h

    r29a3d72 r39c8fdb  
    5555LINKER_SYMBOL(bsp_stack_abt_size)
    5656
    57 LINKER_SYMBOL(bsp_stack_undef_begin)
    58 LINKER_SYMBOL(bsp_stack_undef_end)
    59 LINKER_SYMBOL(bsp_stack_undef_size)
     57LINKER_SYMBOL(bsp_stack_und_begin)
     58LINKER_SYMBOL(bsp_stack_und_end)
     59LINKER_SYMBOL(bsp_stack_und_size)
    6060
    6161LINKER_SYMBOL(bsp_stack_svc_begin)
  • c/src/lib/libbsp/arm/shared/start/start.S

    r29a3d72 r39c8fdb  
    1818
    1919#include <rtems/asm.h>
     20#include <rtems/score/cpu.h>
    2021
    2122#include <bspopts.h>
     
    3334.globl start
    3435.globl bsp_start_memcpy
    35 
    36 /* Program Status Register definitions */
    37 
    38 .equ PSR_MODE_USR,   0x10
    39 .equ PSR_MODE_FIQ,   0x11
    40 .equ PSR_MODE_IRQ,   0x12
    41 .equ PSR_MODE_SVC,   0x13
    42 .equ PSR_MODE_ABT,   0x17
    43 .equ PSR_MODE_UNDEF, 0x1b
    44 .equ PSR_MODE_SYS,   0x1f
    45 .equ PSR_I,          0x80
    46 .equ PSR_F,          0x40
    47 .equ PSR_T,          0x20
    4836
    4937.section ".bsp_start", "ax"
     
    118106         * Set SVC mode, disable interrupts and enable ARM instructions.
    119107         */
    120         mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)
     108        mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
    121109        msr     cpsr, r0
    122110
     
    124112
    125113        /* Enter IRQ mode and set up the IRQ stack pointer */
    126         mov     r0, #(PSR_MODE_IRQ | PSR_I | PSR_F)
     114        mov     r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
    127115        msr     cpsr, r0
    128116        ldr     sp, =bsp_stack_irq_end
    129117
    130118        /* Enter FIQ mode and set up the FIQ stack pointer */
    131         mov     r0, #(PSR_MODE_FIQ | PSR_I | PSR_F)
     119        mov     r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
    132120        msr     cpsr, r0
    133121        ldr     sp, =bsp_stack_fiq_end
    134122
    135123        /* Enter ABT mode and set up the ABT stack pointer */
    136         mov     r0, #(PSR_MODE_ABT | PSR_I | PSR_F)
     124        mov     r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
    137125        msr     cpsr, r0
    138126        ldr     sp, =bsp_stack_abt_end
    139127
    140         /* Enter UNDEF mode and set up the UNDEF stack pointer */
    141         mov     r0, #(PSR_MODE_UNDEF | PSR_I | PSR_F)
    142         msr     cpsr, r0
    143         ldr     sp, =bsp_stack_undef_end
     128        /* Enter UND mode and set up the UND stack pointer */
     129        mov     r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
     130        msr     cpsr, r0
     131        ldr     sp, =bsp_stack_und_end
    144132
    145133        /* Enter SVC mode and set up the SVC stack pointer */
    146         mov     r0, #(PSR_MODE_SVC | PSR_I | PSR_F)
     134        mov     r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
    147135        msr     cpsr, r0
    148136        ldr     sp, =bsp_stack_svc_end
     
    179167        bl      bsp_start_hook_1
    180168
     169        SWITCH_FROM_ARM_TO_THUMB        r0
     170
    181171        /* Branch to boot card */
    182172        mov     r0, #0
    183 #ifdef __thumb__
    184         ldr     r3, =boot_card
    185         mov     lr, pc
    186         bx      r3
    187 .thumb
    188         bx      pc
    189         nop
    190 .arm
    191 #else
    192173        bl      boot_card
    193 #endif
    194174
    195175        /* Branch to reset function */
    196 #ifdef __thumb__
    197         ldr     r3, =bsp_reset
    198         mov     lr, pc
    199         bx      r3
    200 .thumb
    201         bx      pc
    202         nop
    203 .arm
    204 #else
    205176        bl      bsp_reset
    206 #endif
     177
     178        SWITCH_FROM_THUMB_TO_ARM
    207179
    208180        /* Spin forever */
  • c/src/lib/libbsp/arm/shared/startup/linkcmds.base

    r29a3d72 r39c8fdb  
    2626
    2727/*
    28  * BSP: Global symbols
     28 * BSP: Global symbols that may be defined externally
    2929 */
    3030
    31 bsp_section_align = 32;
    32 
    33 bsp_stack_align = 4;
    34 
    35 /*
    36  * BSP: Symbols that may be defined externally
    37  */
     31bsp_stack_align = DEFINED (bsp_stack_align) ? bsp_stack_align : 4;
     32
     33bsp_section_align = DEFINED (bsp_section_align) ? bsp_section_align : 32;
     34
     35bsp_section_start_end_align = DEFINED (bsp_section_start_end_align) ? bsp_section_start_end_align : bsp_section_align;
     36bsp_section_vector_end_align = DEFINED (bsp_section_vector_end_align) ? bsp_section_vector_end_align : bsp_section_align;
     37bsp_section_text_end_align = DEFINED (bsp_section_text_end_align) ? bsp_section_text_end_align : bsp_section_align;
     38bsp_section_rodata_end_align = DEFINED (bsp_section_rodata_end_align) ? bsp_section_rodata_end_align : bsp_section_align;
     39bsp_section_data_end_align = DEFINED (bsp_section_data_end_align) ? bsp_section_data_end_align : bsp_section_align;
     40bsp_section_fast_end_align = DEFINED (bsp_section_fast_end_align) ? bsp_section_fast_end_align : bsp_section_align;
     41bsp_section_bss_end_align = DEFINED (bsp_section_bss_end_align) ? bsp_section_bss_end_align : bsp_section_align;
     42
     43bsp_section_vbarrier_align = DEFINED (bsp_section_vbarrier_align) ? bsp_section_vbarrier_align : 1;
     44bsp_section_robarrier_align = DEFINED (bsp_section_robarrier_align) ? bsp_section_robarrier_align : 1;
    3845
    3946bsp_stack_abt_size = DEFINED (bsp_stack_abt_size) ? bsp_stack_abt_size : 128;
     
    4956bsp_stack_svc_size = ALIGN (bsp_stack_svc_size, bsp_stack_align);
    5057
    51 bsp_stack_undef_size = DEFINED (bsp_stack_undef_size) ? bsp_stack_undef_size : 128;
    52 bsp_stack_undef_size = ALIGN (bsp_stack_undef_size, bsp_stack_align);
     58bsp_stack_und_size = DEFINED (bsp_stack_und_size) ? bsp_stack_und_size : 128;
     59bsp_stack_und_size = ALIGN (bsp_stack_und_size, bsp_stack_align);
    5360
    5461SECTIONS {
     
    6370                 */
    6471                KEEP (*(.bsp_start))
    65 
    66                 . = ALIGN (bsp_section_align);
     72                KEEP (*(.bsp_start_data))
     73
     74                . = ALIGN (bsp_section_start_end_align);
    6775
    6876                /*
     
    108116                bsp_stack_svc_end = .;
    109117
    110                 bsp_stack_undef_begin = .;
    111                 . = . + bsp_stack_undef_size;
    112                 bsp_stack_undef_end = .;
     118                bsp_stack_und_begin = .;
     119                . = . + bsp_stack_und_size;
     120                bsp_stack_und_end = .;
    113121
    114122                /*
     
    117125                *(.bsp_vector)
    118126
    119                 . = ALIGN (bsp_section_align);
     127                . = ALIGN (bsp_section_vector_end_align);
    120128
    121129                /*
     
    126134
    127135        bsp_section_vector_size = bsp_section_vector_end - bsp_section_vector_begin;
     136
     137        .vbarrier : {
     138                . = ALIGN (bsp_section_vbarrier_align);
     139        } > REGION_VECTOR
    128140
    129141        .text : {
     
    176188                KEEP (*(.fini))
    177189
    178                 . = ALIGN (bsp_section_align);
     190                . = ALIGN (bsp_section_text_end_align);
    179191
    180192                /*
     
    204216                *(.rodata1)
    205217
    206                 . = ALIGN (bsp_section_align);
     218                . = ALIGN (bsp_section_rodata_end_align);
    207219
    208220                /*
     
    215227
    216228        bsp_section_rodata_load_begin = LOADADDR (.rodata);
     229
     230        .robarrier : {
     231                . = ALIGN (bsp_section_robarrier_align);
     232        } > REGION_RODATA
    217233
    218234        .data : {
     
    265281                SORT(CONSTRUCTORS)
    266282
    267                 . = ALIGN (bsp_section_align);
     283                . = ALIGN (bsp_section_data_end_align);
    268284
    269285                /*
     
    282298                *(.bsp_fast)
    283299
    284                 . = ALIGN (bsp_section_align);
     300                . = ALIGN (bsp_section_fast_end_align);
    285301
    286302                bsp_section_fast_end = .;
     
    301317                *(.bss .bss.* .gnu.linkonce.b.*)
    302318
    303                 . = ALIGN (bsp_section_align);
     319                . = ALIGN (bsp_section_bss_end_align);
    304320
    305321                /*
  • c/src/lib/libcpu/arm/ChangeLog

    r29a3d72 r39c8fdb  
     12010-01-12      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * shared/include/arm-cp15.h, shared/include/cache.h,
     4        shared/include/cache_.h: New files.
     5        * Makefile.am, preinstall.am: Update for new files.
     6        * shared/arm920/mmu.c: Include and use <libcpu/arm-cp15.h>.
     7
    182009-11-30      Fernando Nicodemos <fgnicodemos@terra.com.br>
    29
  • c/src/lib/libcpu/arm/Makefile.am

    r29a3d72 r39c8fdb  
    1616
    1717include_libcpu_HEADERS = shared/include/mmu.h
     18include_libcpu_HEADERS += shared/include/arm-cp15.h
    1819
    1920## shared/arm920
  • c/src/lib/libcpu/arm/preinstall.am

    r29a3d72 r39c8fdb  
    2828        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/mmu.h
    2929PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/mmu.h
     30
     31$(PROJECT_INCLUDE)/libcpu/arm-cp15.h: shared/include/arm-cp15.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
     32        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/arm-cp15.h
     33PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/arm-cp15.h
    3034endif
    3135if pxa255
  • c/src/lib/libcpu/arm/shared/arm920/mmu.c

    r29a3d72 r39c8fdb  
    88 */
    99#include <libcpu/mmu.h>
     10#include <libcpu/arm-cp15.h>
    1011
    1112typedef uint32_t mmu_lvl1_t;
     
    1314extern uint32_t _ttbl_base;
    1415
    15 static inline uint32_t mmu_get_id(void);
    16 static inline uint32_t mmu_get_ctrl(void);
    17 static inline void mmu_set_ctrl(uint32_t val);
    18 static inline uint32_t mmu_get_trans_tbl(void);
    19 static inline void mmu_set_trans_tbl(uint32_t val);
    20 static inline uint32_t mmu_get_domain_ctrl(void);
    21 static inline void mmu_set_domain_ctrl(uint32_t val);
    22 static inline uint32_t mmu_get_fault_stat(void);
    23 static inline void mmu_set_fault_stat(uint32_t val);
    24 static inline uint32_t mmu_get_fault_addr(void);
    25 static inline void mmu_set_fault_addr(uint32_t val);
    26 static inline void mmu_set_cache_inval(void);
    27 static inline void mmu_set_tlb_inval(void);
    28 static inline uint32_t mmu_get_proc_id(void);
    29 static inline void mmu_set_proc_id(uint32_t val);
    3016static void mmu_set_map_inval(mmu_lvl1_t *base);
    3117
     
    5541#define MMU_SECT_AP_ALL (0x3 << 10)
    5642
    57 #define NOP ( { asm volatile ("nop\n" ); } )
    58 
    5943void mmu_init(mmu_sect_map_t *map)
    6044{
     
    6347
    6448    /* flush the cache and TLB */
    65     mmu_set_cache_inval();
    66     mmu_set_tlb_inval();
     49    arm_cp15_cache_invalidate();
     50    arm_cp15_tlb_invalidate();
    6751
    6852    /* set manage mode access for all domains */
    69     mmu_set_domain_ctrl(0xffffffff);
     53    arm_cp15_set_domain_access_control(0xffffffff);
    7054
    7155    lvl1_base = (mmu_lvl1_t *)&_ttbl_base;
     
    7357    /* set up the trans table */
    7458    mmu_set_map_inval(lvl1_base);
    75     mmu_set_trans_tbl((uint32_t) lvl1_base);
     59    arm_cp15_set_translation_table_base(lvl1_base);
    7660
    7761    /* create a 1:1 mapping of the entire address space */
     
    121105
    122106    /* flush the cache and TLB */
    123     mmu_set_cache_inval();
    124     mmu_set_tlb_inval();
    125 
    126     NOP;
    127     NOP;
     107    arm_cp15_cache_invalidate();
     108    arm_cp15_tlb_invalidate();
    128109
    129110    /*  I & D caches turned on */
    130     mmu_set_ctrl(MMU_CTRL_DEFAULT |
    131                  MMU_CTRL_D_CACHE_EN |
    132                  MMU_CTRL_I_CACHE_EN |
    133                  MMU_CTRL_ALIGN_FAULT_EN |
    134                  MMU_CTRL_LITTLE_ENDIAN |
    135                  MMU_CTRL_MMU_EN);
    136 
    137     NOP;
    138     NOP;
     111    arm_cp15_set_control(MMU_CTRL_DEFAULT |
     112                         MMU_CTRL_D_CACHE_EN |
     113                         MMU_CTRL_I_CACHE_EN |
     114                         MMU_CTRL_ALIGN_FAULT_EN |
     115                         MMU_CTRL_LITTLE_ENDIAN |
     116                         MMU_CTRL_MMU_EN);
    139117
    140118    return;
    141 }
    142 
    143 
    144 static inline uint32_t mmu_get_id(void)
    145 {
    146     uint32_t val;
    147     asm volatile ("msr 15, 0, %0, cr0, cr0\n" : "=r" (val));
    148     return val;
    149 }
    150 
    151 static inline uint32_t mmu_get_ctrl(void)
    152 {
    153     uint32_t val;
    154     asm volatile ("mrc 15, 0, %0, cr1, cr0\n" : "=r" (val));
    155     return val;
    156 }
    157 
    158 static inline void mmu_set_ctrl(uint32_t val)
    159 {
    160     asm volatile ("mcr 15, 0, %0, cr1, cr0, 0\n" : :"r" (val));
    161 }
    162 
    163 static inline uint32_t mmu_get_trans_tbl(void)
    164 {
    165     uint32_t val;
    166     asm volatile ("msr 15, 0, %0, cr2, cr0\n" : "=r" (val));
    167     return val;
    168 }
    169 
    170 static inline void mmu_set_trans_tbl(uint32_t val)
    171 {
    172     asm volatile ("mcr 15, 0, %0, cr2, cr0, 0\n" : :"r" (val));
    173 }
    174 
    175 static inline uint32_t mmu_get_domain_ctrl(void)
    176 {
    177     uint32_t val;
    178     asm volatile ("msr 15, 0, %0, cr3, cr0\n" : "=r" (val));
    179     return val;
    180 }
    181 
    182 static inline void mmu_set_domain_ctrl(uint32_t val)
    183 {
    184     asm volatile ("mcr 15, 0, %0, cr3, cr0, 0\n" : :"r" (val));
    185 }
    186 
    187 static inline uint32_t mmu_get_fault_stat(void)
    188 {
    189     uint32_t val;
    190     asm volatile ("msr 15, 0, %0, cr5, cr0\n" : "=r" (val));
    191     return val;
    192 }
    193 
    194 static inline void mmu_set_fault_stat(uint32_t val)
    195 {
    196     asm volatile ("mcr 15, 0, %0, cr5, cr0, 0\n" : :"r" (val));
    197 }
    198 
    199 static inline uint32_t mmu_get_fault_addr(void)
    200 {
    201     uint32_t val;
    202     asm volatile ("msr 15, 0, %0, cr6, cr0\n" : "=r" (val));
    203     return val;
    204 }
    205 
    206 static inline void mmu_set_fault_addr(uint32_t val)
    207 {
    208     asm volatile ("mcr 15, 0, %0, cr6, cr0, 0\n" : :"r" (val));
    209 }
    210 
    211 static inline void mmu_set_cache_inval(void)
    212 {
    213     uint32_t val = 0;
    214     asm volatile ("mcr 15, 0, %0, cr7, cr7, 0\n" : :"r" (val));
    215 }
    216 
    217 static inline void mmu_set_tlb_inval(void)
    218 {
    219     uint32_t val = 0;
    220     asm volatile ("mcr 15, 0, %0, cr8, cr7, 0\n" : :"r" (val));
    221 }
    222 
    223 static inline uint32_t mmu_get_proc_id(void)
    224 {
    225     uint32_t val;
    226     asm volatile ("msr 15, 0, %0, cr13, cr0\n" : "=r" (val));
    227     return val;
    228 }
    229 
    230 static inline void mmu_set_proc_id(uint32_t val)
    231 {
    232     asm volatile ("mcr 15, 0, %0, cr13, cr0, 0\n" : :"r" (val));
    233119}
    234120
     
    242128}
    243129
    244 
    245130void mmu_set_cpu_async_mode(void)
    246131{
    247132    uint32_t reg;
    248     reg = mmu_get_ctrl();
     133    reg = arm_cp15_get_control();
    249134    reg |= 0xc0000000;
    250     mmu_set_ctrl(reg);
     135    arm_cp15_set_control(reg);
    251136}
    252 
  • cpukit/score/cpu/arm/ChangeLog

    r29a3d72 r39c8fdb  
     12010-01-12      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * arm_exc_abort.S: New file.
     4        * Makefile.am: Update for new file.
     5        * arm_exc_interrupt.S, cpu.c, rtems/asm.h, rtems/score/cpu.h: Changed
     6        macros which switch from and to THUMB mode.  Added a default prefetch
     7        and data abort handler which reports the complete processor context.
     8        Added PSR defines.
     9
    1102009-12-15      Sebastian Huber <sebastian.huber@embedded-brains.de>
    211
  • cpukit/score/cpu/arm/Makefile.am

    r29a3d72 r39c8fdb  
    1414libscorecpu_a_SOURCES = cpu.c \
    1515        cpu_asm.S \
     16        arm_exc_abort.S \
    1617        arm_exc_interrupt.S \
    1718        arm_exc_handler_low.S \
  • cpukit/score/cpu/arm/arm_exc_interrupt.S

    r29a3d72 r39c8fdb  
    11/**
    22 * @file
     3 *
     4 * @ingroup arm
    35 *
    46 * @brief ARM interrupt exception prologue and epilogue.
     
    2426 */
    2527
     28#include <rtems/asm.h>
     29
    2630#define EXCHANGE_LR r4
    2731#define EXCHANGE_SPSR r5
     
    4145
    4246.extern bsp_interrupt_dispatch
    43 
    44 .macro SWITCH_FROM_THUMB_TO_ARM
    45 #ifdef __thumb__
    46 .align 2
    47         bx      pc
    48 .arm
    49 #endif /* __thumb__ */
    50 .endm
    51 
    52 .macro SWITCH_FROM_ARM_TO_THUMB REG
    53 #ifdef __thumb__
    54         add     \REG, pc, #1
    55         bx      \REG
    56 .thumb
    57 #endif /* __thumb__ */
    58 .endm
    5947
    6048.arm
  • cpukit/score/cpu/arm/cpu.c

    r29a3d72 r39c8fdb  
    5757void _CPU_ISR_Set_level( uint32_t level )
    5858{
    59   uint32_t reg;
     59  uint32_t arm_switch_reg;
    6060
    6161  asm volatile (
    62     THUMB_TO_ARM
    63     "mrs %0, cpsr\n"
    64     "bic %0, %0, #" _CPU_ISR_LEVEL_STRINGOF( CPU_MODES_INTERRUPT_MASK ) "\n"
    65     "orr %0, %0, %1\n"
     62    ARM_SWITCH_TO_ARM
     63    "mrs %[arm_switch_reg], cpsr\n"
     64    "bic %[arm_switch_reg], #" _CPU_ISR_LEVEL_STRINGOF( CPU_MODES_INTERRUPT_MASK ) "\n"
     65    "orr %[arm_switch_reg], %[level]\n"
    6666    "msr cpsr, %0\n"
    67     ARM_TO_THUMB
    68     : "=r" (reg)
    69     : "r" (level)
     67    ARM_SWITCH_BACK
     68    : [arm_switch_reg] "=&r" (arm_switch_reg)
     69    : [level] "r" (level)
    7070  );
    7171}
     
    7373uint32_t _CPU_ISR_Get_level( void )
    7474{
    75   uint32_t reg;
     75  ARM_SWITCH_REGISTERS;
    7676  uint32_t level;
    7777
    7878  asm volatile (
    79     THUMB_TO_ARM
    80     "mrs %0, cpsr\n"
    81     "and %1, %0, #" _CPU_ISR_LEVEL_STRINGOF( CPU_MODES_INTERRUPT_MASK ) "\n"
    82     ARM_TO_THUMB
    83     : "=r" (reg), "=r" (level)
     79    ARM_SWITCH_TO_ARM
     80    "mrs %[level], cpsr\n"
     81    "and %[level], #" _CPU_ISR_LEVEL_STRINGOF( CPU_MODES_INTERRUPT_MASK ) "\n"
     82    ARM_SWITCH_BACK
     83    : [level] "=&r" (level) ARM_SWITCH_ADDITIONAL_OUTPUT
    8484  );
    8585
  • cpukit/score/cpu/arm/rtems/asm.h

    r29a3d72 r39c8fdb  
    142142#endif
    143143
     144.macro SWITCH_FROM_THUMB_TO_ARM
     145#ifdef __thumb__
     146.align 2
     147        bx      pc
     148.arm
     149#endif /* __thumb__ */
     150.endm
     151
     152.macro SWITCH_FROM_ARM_TO_THUMB REG
     153#ifdef __thumb__
     154        add     \REG, pc, #1
     155        bx      \REG
     156.thumb
     157#endif /* __thumb__ */
     158.endm
     159
    144160#endif /* _RTEMS_ASM_H */
  • cpukit/score/cpu/arm/rtems/score/cpu.h

    r29a3d72 r39c8fdb  
    99 *  processor.
    1010 *
     11 *  Copyright (c) 2009 embedded brains GmbH.
     12 *
    1113 *  Copyright (c) 2007 Ray Xu <Rayx.cn@gmail.com>
    1214 *
     
    4547
    4648#ifdef __thumb__
    47   #define ARM_TO_THUMB "add %0, pc, #1\nbx %0\n.thumb\n"
    48   #define THUMB_TO_ARM ".align 2\nbx pc\n.arm\n"
     49  #define ARM_SWITCH_REGISTERS uint32_t arm_switch_reg
     50  #define ARM_SWITCH_TO_ARM ".align 2\nbx pc\n.arm\n"
     51  #define ARM_SWITCH_BACK "add %[arm_switch_reg], pc, #1\nbx %[arm_switch_reg]\n.thumb\n"
     52  #define ARM_SWITCH_OUTPUT [arm_switch_reg] "=&r" (arm_switch_reg)
     53  #define ARM_SWITCH_ADDITIONAL_OUTPUT , ARM_SWITCH_OUTPUT
    4954#else
    50   #define ARM_TO_THUMB
    51   #define THUMB_TO_ARM
    52 #endif
     55  #define ARM_SWITCH_REGISTERS
     56  #define ARM_SWITCH_TO_ARM
     57  #define ARM_SWITCH_BACK
     58  #define ARM_SWITCH_OUTPUT
     59  #define ARM_SWITCH_ADDITIONAL_OUTPUT
     60#endif
     61
     62#define ARM_PSR_N (1 << 31)
     63#define ARM_PSR_Z (1 << 30)
     64#define ARM_PSR_C (1 << 29)
     65#define ARM_PSR_V (1 << 28)
     66#define ARM_PSR_Q (1 << 27)
     67#define ARM_PSR_J (1 << 24)
     68#define ARM_PSR_GE_SHIFT 16
     69#define ARM_PSR_GE_MASK (0xf << ARM_PSR_GE_SHIFT)
     70#define ARM_PSR_E (1 << 9)
     71#define ARM_PSR_A (1 << 8)
     72#define ARM_PSR_I (1 << 7)
     73#define ARM_PSR_F (1 << 6)
     74#define ARM_PSR_T (1 << 5)
     75#define ARM_PSR_M_SHIFT 0
     76#define ARM_PSR_M_MASK (0x1f << ARM_PSR_M_SHIFT)
     77#define ARM_PSR_M_USR 0x10
     78#define ARM_PSR_M_FIQ 0x11
     79#define ARM_PSR_M_IRQ 0x12
     80#define ARM_PSR_M_SVC 0x13
     81#define ARM_PSR_M_ABT 0x17
     82#define ARM_PSR_M_UND 0x1b
     83#define ARM_PSR_M_SYS 0x1f
    5384
    5485/* If someone uses THUMB we assume she wants minimal code size */
     
    206237static inline uint32_t arm_interrupt_disable( void )
    207238{
    208   uint32_t reg;
     239  uint32_t arm_switch_reg;
    209240  uint32_t level;
    210241
    211242  asm volatile (
    212     THUMB_TO_ARM
    213     "mrs %1, cpsr\n"
    214     "orr %0, %1, #0x80\n"
    215     "msr cpsr, %0\n"
    216     ARM_TO_THUMB
    217     : "=r" (reg), "=r" (level)
     243    ARM_SWITCH_TO_ARM
     244    "mrs %[level], cpsr\n"
     245    "orr %[arm_switch_reg], %[level], #0x80\n"
     246    "msr cpsr, %[arm_switch_reg]\n"
     247    ARM_SWITCH_BACK
     248    : [arm_switch_reg] "=&r" (arm_switch_reg), [level] "=&r" (level)
    218249  );
    219250
     
    223254static inline void arm_interrupt_enable( uint32_t level )
    224255{
    225   #ifdef __thumb__
    226     uint32_t reg;
    227 
    228     asm volatile (
    229       THUMB_TO_ARM
    230       "msr cpsr, %1\n"
    231       ARM_TO_THUMB
    232       : "=r" (reg)
    233       : "r" (level)
    234     );
    235   #else
    236     asm volatile (
    237       "msr cpsr, %0"
    238       :
    239       : "r" (level)
    240     );
    241   #endif
     256  ARM_SWITCH_REGISTERS;
     257
     258  asm volatile (
     259    ARM_SWITCH_TO_ARM
     260    "msr cpsr, %[level]\n"
     261    ARM_SWITCH_BACK
     262    : ARM_SWITCH_OUTPUT
     263    : [level] "r" (level)
     264  );
    242265}
    243266
    244267static inline void arm_interrupt_flash( uint32_t level )
    245268{
    246   uint32_t reg;
     269  uint32_t arm_switch_reg;
    247270
    248271  asm volatile (
    249     THUMB_TO_ARM
    250     "mrs %0, cpsr\n"
    251     "msr cpsr, %1\n"
    252     "msr cpsr, %0\n"
    253     ARM_TO_THUMB
    254     : "=r" (reg)
    255     : "r" (level)
     272    ARM_SWITCH_TO_ARM
     273    "mrs %[arm_switch_reg], cpsr\n"
     274    "msr cpsr, %[level]\n"
     275    "msr cpsr, %[arm_switch_reg]\n"
     276    ARM_SWITCH_BACK
     277    : [arm_switch_reg] "=&r" (arm_switch_reg)
     278    : [level] "r" (level)
    256279  );
    257280}
     
    259282static inline uint32_t arm_status_irq_enable( void )
    260283{
    261   uint32_t reg;
     284  uint32_t arm_switch_reg;
    262285  uint32_t psr;
    263286
     
    265288
    266289  asm volatile (
    267     THUMB_TO_ARM
    268     "mrs %1, cpsr\n"
    269     "bic %0, %1, #0x80\n"
    270     "msr cpsr, %0\n"
    271     ARM_TO_THUMB
    272     : "=r" (reg), "=r" (psr)
     290    ARM_SWITCH_TO_ARM
     291    "mrs %[psr], cpsr\n"
     292    "bic %[arm_switch_reg], %[psr], #0x80\n"
     293    "msr cpsr, %[arm_switch_reg]\n"
     294    ARM_SWITCH_BACK
     295    : [arm_switch_reg] "=&r" (arm_switch_reg), [psr] "=&r" (psr)
    273296  );
    274297
     
    278301static inline void arm_status_restore( uint32_t psr )
    279302{
    280   #ifdef __thumb__
    281     uint32_t reg;
    282 
    283     asm volatile (
    284       THUMB_TO_ARM
    285       "msr cpsr, %1\n"
    286       ARM_TO_THUMB
    287       : "=r" (reg)
    288       : "r" (psr)
    289     );
    290   #else
    291     asm volatile (
    292       "msr cpsr, %0"
    293       :
    294       : "r" (psr)
    295     );
    296   #endif
     303  ARM_SWITCH_REGISTERS;
     304
     305  asm volatile (
     306    ARM_SWITCH_TO_ARM
     307    "msr cpsr, %[psr]\n"
     308    ARM_SWITCH_BACK
     309    : ARM_SWITCH_OUTPUT
     310    : [psr] "r" (psr)
     311  );
    297312
    298313  RTEMS_COMPILER_MEMORY_BARRIER();
     
    403418extern uint32_t arm_cpu_mode;
    404419
    405 void arm_exc_abort_data( void );
    406 
    407 void arm_exc_abort_prefetch( void );
     420typedef struct {
     421  uint32_t r0;
     422  uint32_t r1;
     423  uint32_t r2;
     424  uint32_t r3;
     425  uint32_t r4;
     426  uint32_t r5;
     427  uint32_t r6;
     428  uint32_t r7;
     429  uint32_t r8;
     430  uint32_t r9;
     431  uint32_t r10;
     432  uint32_t r11;
     433  uint32_t r12;
     434  uint32_t sp;
     435  uint32_t lr;
     436  uint32_t pc;
     437  uint32_t cpsr;
     438} arm_cpu_context;
     439
     440typedef void arm_exc_abort_handler( arm_cpu_context *context );
     441
     442void arm_exc_data_abort_set_handler( arm_exc_abort_handler handler );
     443
     444void arm_exc_data_abort( void );
     445
     446void arm_exc_prefetch_abort_set_handler( arm_exc_abort_handler handler );
     447
     448void arm_exc_prefetch_abort( void );
     449
     450void bsp_interrupt_dispatch( void );
    408451
    409452void arm_exc_interrupt( void );
     
    411454void arm_exc_undefined( void );
    412455
    413 void bsp_interrupt_dispatch( void );
    414 
    415456#ifdef __cplusplus
    416457}
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