Changeset 3906b3ea in rtems


Ignore:
Timestamp:
Apr 16, 2004, 9:29:43 PM (16 years ago)
Author:
Ralf Corsepius <ralf.corsepius@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
0fdc099
Parents:
aed742c
Message:

Remove stray white spaces.

Location:
c/src/lib/libcpu/sh
Files:
33 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/sh/sh7032/clock/ckinit.c

    raed742c r3906b3ea  
    1010 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    1111 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
    12  * 
     12 *
    1313 *
    1414 *  COPYRIGHT (c) 1998.
     
    4141#define I_CLK_PHI_8     3
    4242
    43 /* 
     43/*
    4444 * Set I_CLK_PHI to one of the I_CLK_PHI_X values from above to choose
    4545 * a PHI/X clock rate.
    4646 */
    47  
     47
    4848#define I_CLK_PHI       I_CLK_PHI_4
    4949#define CLOCK_SCALE     (1<<I_CLK_PHI)
     
    6363 *
    6464 * This is a very expensive function ;-)
    65  * 
     65 *
    6666 * Below are two variants:
    6767 * 1. A variant applying integer arithmetics, only.
    6868 * 2. A variant applying floating point arithmetics
    6969 *
    70  * The floating point variant pulls in the fmath routines when linking, 
     70 * The floating point variant pulls in the fmath routines when linking,
    7171 * resulting in slightly larger executables for applications that do not
    7272 * apply fmath otherwise. However, the imath variant is significantly slower
     
    7979 * future.
    8080 */
    81 static unsigned int sh_clicks_per_tick( 
     81static unsigned int sh_clicks_per_tick(
    8282  unsigned int clicks_per_sec,
    8383  unsigned int usec_per_tick )
     
    8585#if 1
    8686  unsigned int clicks_per_tick = 0 ;
    87  
     87
    8888  unsigned int b = clicks_per_sec ;
    8989  unsigned int c = 1000000 ;
     
    9999    a = ( ( b / c ) * usec_per_tick ) / d ;
    100100    clicks_per_tick += a ;
    101   } 
     101  }
    102102  return clicks_per_tick ;
    103103#else
    104   double fclicks_per_tick = 
     104  double fclicks_per_tick =
    105105    ((double) clicks_per_sec * (double) usec_per_tick) / 1000000.0 ;
    106106  return (uint32_t) fclicks_per_tick ;
     
    139139 * These are set by clock driver during its init
    140140 */
    141  
     141
    142142rtems_device_major_number rtems_clock_major = ~0;
    143143rtems_device_minor_number rtems_clock_minor;
     
    199199  uint32_t   cclicks_per_tick ;
    200200  uint16_t   Clock_limit ;
    201  
     201
    202202  /*
    203203   *  Initialize the clock tick device driver variables
     
    205205
    206206  Clock_driver_ticks = 0;
    207    
     207
    208208  if ( rtems_configuration_get_microseconds_per_tick() != 0 )
    209209    microseconds_per_tick = rtems_configuration_get_microseconds_per_tick() ;
     
    212212
    213213  /* clock clicks per tick */
    214   cclicks_per_tick = 
     214  cclicks_per_tick =
    215215    sh_clicks_per_tick(
    216216      rtems_cpu_configuration_get_clicks_per_second() / CLOCK_SCALE,
     
    218218
    219219  Clock_isrs_const = cclicks_per_tick >> 16 ;
    220   if ( ( cclicks_per_tick | 0xffff ) > 0 ) 
     220  if ( ( cclicks_per_tick | 0xffff ) > 0 )
    221221    Clock_isrs_const++ ;
    222222  Clock_limit = cclicks_per_tick / Clock_isrs_const ;
     
    227227   *  Hardware specific initialize goes here
    228228   */
    229  
     229
    230230  /* stop Timer 0 */
    231231  temp8 = read8( ITU_TSTR) & ITU0_STARTMASK;
     
    247247
    248248  /* use GRA without I/O - pins  */
    249   write8( ITU0_TIORVAL, ITU_TIOR0); 
    250    
     249  write8( ITU0_TIORVAL, ITU_TIOR0);
     250
    251251  /* reset flags of the status register */
    252252  temp8 = read8( ITU_TSR0) & ITU_STAT_MASK;
     
    263263  /* set counter limits */
    264264  write16( Clock_limit, ITU_GRA0);
    265    
     265
    266266  /* start counter */
    267267  temp8 = read8( ITU_TSTR) |~ITU0_STARTMASK;
     
    313313{
    314314  Install_clock( Clock_isr );
    315  
     315
    316316  /*
    317317   * make major/minor avail to others such as shared memory driver
    318318   */
    319  
     319
    320320  rtems_clock_major = major;
    321321  rtems_clock_minor = minor;
    322  
     322
    323323  return RTEMS_SUCCESSFUL;
    324324}
     
    332332  uint32_t   isrlevel;
    333333  rtems_libio_ioctl_args_t *args = pargp;
    334  
     334
    335335  if (args != 0)
    336336    {
     
    339339       * to do this, it will just be this simple...
    340340       */
    341      
     341
    342342      if (args->command == rtems_build_name('I', 'S', 'R', ' '))
    343343        {
     
    349349          rtems_interrupt_disable( isrlevel );
    350350          rtems_interrupt_catch( args->buffer, CLOCK_VECTOR, &ignored );
    351          
     351
    352352          rtems_interrupt_enable( isrlevel );
    353353        }
  • c/src/lib/libcpu/sh/sh7032/delay/delay.c

    raed742c r3906b3ea  
    1 /* 
     1/*
    22 *  This routine is a simple spin delay
    33 *
     
    3838
    3939void CPU_delay( uint32_t   microseconds )
    40 { 
    41   register uint32_t   clicks_per_usec = 
     40{
     41  register uint32_t   clicks_per_usec =
    4242    rtems_cpu_configuration_get_clicks_per_second() / 1000000 ;
    43   register uint32_t   _delay = 
     43  register uint32_t   _delay =
    4444    (microseconds) * (clicks_per_usec);
    4545  asm volatile (
  • c/src/lib/libcpu/sh/sh7032/include/iosh7032.h

    raed742c r3906b3ea  
    88 *           Bernd Becker (becker@faw.uni-ulm.de)
    99 *
    10  *  Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which 
     10 *  Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which
    1111 *  contained no copyright notice.
    1212 *
     
    1616 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    1717 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
    18  * 
     18 *
    1919 *
    2020 *  COPYRIGHT (c) 1998.
     
    3333/*
    3434 * After each line is explained whether the access is char short or long.
    35  * The functions read/writeb, w, l, 8, 16, 32 can be found 
     35 * The functions read/writeb, w, l, 8, 16, 32 can be found
    3636 * in exec/score/cpu/sh/sh_io.h
    3737 *
  • c/src/lib/libcpu/sh/sh7032/include/ispsh7032.h

    raed742c r3906b3ea  
    1111 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    1212 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
    13  * 
     13 *
    1414 *
    1515 *  COPYRIGHT (c) 1998.
  • c/src/lib/libcpu/sh/sh7032/include/sci.h

    raed742c r3906b3ea  
    1010 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    1111 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
    12  * 
     12 *
    1313 *
    1414 *  COPYRIGHT (c) 1998.
     
    3131/*
    3232 * Devices are set to 9600 bps, 8 databits, 1 stopbit, no
    33  * parity and asynchronous mode by default. 
     33 * parity and asynchronous mode by default.
    3434 *
    3535 * NOTE:
    36  *       The onboard serial devices of the SH do not support hardware 
     36 *       The onboard serial devices of the SH do not support hardware
    3737 *       handshake.
    38  */ 
     38 */
    3939
    4040#define DEVSCI_DRIVER_TABLE_ENTRY \
  • c/src/lib/libcpu/sh/sh7032/include/sh7_pfc.h

    raed742c r3906b3ea  
    105105#define PB0MD1  0x0002
    106106#define PB0MD0  0x0001
    107        
     107
    108108#define PB7MD   PB7MD1|PB7MD0
    109109#define PB6MD   PB6MD1|PB6MD0
  • c/src/lib/libcpu/sh/sh7032/sci/sci.c

    raed742c r3906b3ea  
    99 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    1010 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
    11  * 
     11 *
    1212 *
    1313 *  COPYRIGHT (c) 1998.
     
    3737 * NOTE: Some SH variants have 3 sci devices
    3838 */
    39  
     39
    4040#define SCI_MINOR_DEVICES       2
    41  
     41
    4242#define SH_SCI_BASE_0   SCI0_SMR
    4343#define SH_SCI_BASE_1   SCI1_SMR
     
    6868  uint8_t       smr ;
    6969  uint8_t       brr ;
    70  
     70
    7171  if ( c_cflag & CBAUD )
    7272  {
     
    7474      return -1 ;
    7575  }
    76                    
     76
    7777  if ( c_cflag & CSIZE )
    7878  {
     
    9999  else
    100100    smr &= ~SCI_ODD_PARITY;
    101    
     101
    102102  write8( smr, sci_dev->addr + SCI_SMR );
    103103  write8( brr, sci_dev->addr + SCI_BRR );
    104  
     104
    105105  return 0 ;
    106106}
    107107
    108 static void _sci_init( 
     108static void _sci_init(
    109109  rtems_device_minor_number minor )
    110110{
    111111  uint16_t      temp16 ;
    112112
    113   /* Pin function controller initialisation for asynchronous mode */ 
     113  /* Pin function controller initialisation for asynchronous mode */
    114114  if( minor == 0)
    115115    {
     
    118118      temp16 |= (PB_TXD0 | PB_RXD0);
    119119      write16( temp16, PFC_PBCR1);
    120     } 
     120    }
    121121  else
    122122    {
     
    148148  struct scidev_t *scidev = &sci_device[minor] ;
    149149  int8_t           ssr ;
    150                
     150
    151151  while ( !inb((scidev->addr + SCI_SSR) & SCI_TDRE ))
    152152      ;
     
    156156  ssr &= ~SCI_TDRE ;
    157157  write8(ssr,scidev->addr+SCI_SSR);
    158 } 
     158}
    159159
    160160static int _sci_rx_polled (
     
    162162{
    163163  struct scidev_t *scidev = &sci_device[minor] ;
    164        
     164
    165165  unsigned char c;
    166166  char ssr ;
     
    172172  if ( !(ssr & SCI_RDRF) )
    173173    return -1;
    174                
     174
    175175  c = read8(scidev->addr + SCI_RDR) ;
    176  
     176
    177177  write8(ssr & ~SCI_RDRF,scidev->addr + SCI_SSR);
    178178  return c;
     
    190190  rtems_device_driver status ;
    191191  rtems_device_minor_number     i;
    192  
     192
    193193  /*
    194194   * register all possible devices.
     
    207207
    208208  /* default hardware setup */
    209  
     209
    210210  return RTEMS_SUCCESSFUL;
    211211}
     
    222222{
    223223  uint8_t   temp8;
    224  
     224
    225225 /* check for valid minor number */
    226226   if(( minor > ( SCI_MINOR_DEVICES -1 )) || ( minor < 0 ))
     
    228228     return RTEMS_INVALID_NUMBER;
    229229   }
    230  
     230
    231231 /* device already opened */
    232232  if ( sci_device[minor].opened > 0 )
     
    235235    return RTEMS_SUCCESSFUL ;
    236236  }
    237  
     237
    238238  _sci_init( minor );
    239239
     
    257257/* FIXME: Should be one bit delay */
    258258    CPU_delay(50000); /* microseconds */
    259    
     259
    260260    temp8 |= SCI_RE | SCI_TE;
    261261    write8(temp8, sci_device[minor].addr + SCI_SCR);    /* Enable clock output */
    262   } 
     262  }
    263263
    264264  sci_device[minor].opened++ ;
     
    266266  return RTEMS_SUCCESSFUL ;
    267267}
    268  
     268
    269269/*
    270270 *  Close entry point
     
    283283
    284284  sci_device[minor].opened-- ;
    285    
     285
    286286  return RTEMS_SUCCESSFUL ;
    287287}
     
    298298{
    299299  int count = 0;
    300  
     300
    301301  rtems_libio_rw_args_t *rw_args = (rtems_libio_rw_args_t *) arg;
    302302  char * buffer = rw_args->buffer;
  • c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c

    raed742c r3906b3ea  
    1414 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    1515 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
    16  * 
     16 *
    1717 *
    1818 *  COPYRIGHT (c) 1998.
     
    5050#endif
    5151
    52 register unsigned long  *stack_ptr asm("r15"); 
    53 
    54 /* 
     52register unsigned long  *stack_ptr asm("r15");
     53
     54/*
    5555 * sh_set_irq_priority
    56  * 
     56 *
    5757 * this function sets the interrupt level of the specified interrupt
    5858 *
    5959 * parameters:
    60  *             - irq : interrupt number 
     60 *             - irq : interrupt number
    6161 *             - prio: priority to set for this interrupt number
    6262 *
     
    6565 */
    6666
    67 unsigned int sh_set_irq_priority( 
    68   unsigned int irq, 
     67unsigned int sh_set_irq_priority(
     68  unsigned int irq,
    6969  unsigned int prio )
    7070{
     
    9292      irq = irq - 72;
    9393      shiftcount = 12 - ((irq & ~0x03) % 16);
    94      
     94
    9595      switch( irq / 16)
    9696        {
     
    184184
    185185/*
    186  * FIXME: This is an ugly hack, but we wanted to avoid recalculating 
     186 * FIXME: This is an ugly hack, but we wanted to avoid recalculating
    187187 *        the offset each time Context_Control is changed
    188188 */
     
    198198
    199199"       add     %0,r4\n"
    200  
     200
    201201"       stc.l   sr,@-r4\n"
    202202"       stc.l   gbr,@-r4\n"
     
    252252}
    253253
    254 /* 
     254/*
    255255 *  This routine provides the RTEMS interrupt management.
    256256 */
    257  
     257
    258258void __ISR_Handler( uint32_t   vector)
    259259{
     
    292292  if( _ISR_Nest_level == 0 )
    293293    /* restore old stack pointer */
    294     stack_ptr = _old_stack_ptr; 
     294    stack_ptr = _old_stack_ptr;
    295295#endif
    296296
  • c/src/lib/libcpu/sh/sh7032/score/ispsh7032.c

    raed742c r3906b3ea  
    44 * as argument.
    55 *
    6  * __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in 
    7  * some releases of gcc doesn't properly handle #pragma interrupt, if a 
     6 * __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in
     7 * some releases of gcc doesn't properly handle #pragma interrupt, if a
    88 * file contains both isrs and normal functions.
    99 *
     
    1616 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    1717 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
    18  * 
     18 *
    1919 *
    2020 *  COPYRIGHT (c) 1998.
     
    3939proc_ptr _Hardware_isr_Table[256]={
    4040_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
    41 _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
     41_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
    4242_dummy_isp, _dummy_isp, _dummy_isp,
    43 _nmi_isp, _usb_isp, 
    44 _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
    45 _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
    46 _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
    47 _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
    48 _dummy_isp, _dummy_isp, _dummy_isp, 
     43_nmi_isp, _usb_isp,
     44_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
     45_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
     46_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
     47_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
     48_dummy_isp, _dummy_isp, _dummy_isp,
    4949/* trapa 0 -31 */
    50 _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
    51 _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
    52 _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
    53 _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
    54 _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
    55 _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
    56 _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
    57 _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
     50_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
     51_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
     52_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
     53_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
     54_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
     55_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
     56_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
     57_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
    5858/* irq 64 ... */
    59 _irq0_isp, _irq1_isp, _irq2_isp, _irq3_isp, 
     59_irq0_isp, _irq1_isp, _irq2_isp, _irq3_isp,
    6060_irq4_isp, _irq5_isp, _irq6_isp, _irq7_isp,
    61 _dma0_isp, _dummy_isp, _dma1_isp, _dummy_isp, 
    62 _dma2_isp, _dummy_isp, _dma3_isp, _dummy_isp, 
    63 _imia0_isp, _imib0_isp, _ovi0_isp, _dummy_isp, 
    64 _imia1_isp, _imib1_isp, _ovi1_isp, _dummy_isp, 
    65 _imia2_isp, _imib2_isp, _ovi2_isp, _dummy_isp, 
    66 _imia3_isp, _imib3_isp, _ovi3_isp, _dummy_isp, 
    67 _imia4_isp, _imib4_isp, _ovi4_isp, _dummy_isp, 
     61_dma0_isp, _dummy_isp, _dma1_isp, _dummy_isp,
     62_dma2_isp, _dummy_isp, _dma3_isp, _dummy_isp,
     63_imia0_isp, _imib0_isp, _ovi0_isp, _dummy_isp,
     64_imia1_isp, _imib1_isp, _ovi1_isp, _dummy_isp,
     65_imia2_isp, _imib2_isp, _ovi2_isp, _dummy_isp,
     66_imia3_isp, _imib3_isp, _ovi3_isp, _dummy_isp,
     67_imia4_isp, _imib4_isp, _ovi4_isp, _dummy_isp,
    6868_eri0_isp, _rxi0_isp, _txi0_isp, _tei0_isp,
    6969_eri1_isp, _rxi1_isp, _txi1_isp, _tei1_isp,
    70 _prt_isp, _adu_isp, _dummy_isp, _dummy_isp, 
    71 _wdt_isp, 
     70_prt_isp, _adu_isp, _dummy_isp, _dummy_isp,
     71_wdt_isp,
    7272/* 113 */ _dref_isp
    7373};
     
    7777/*
    7878 * Some versions of gcc and all version of egcs at least until egcs-1.1b
    79  * are not able to handle #pragma interrupt correctly if more than 1 isr is 
     79 * are not able to handle #pragma interrupt correctly if more than 1 isr is
    8080 * contained in a file and when optimizing.
    8181 * We try to work around this problem by using the macro below.
     
    120120
    121121/************************************************
    122  * Dummy interrupt service procedure for 
    123  * interrupts being not allowed --> Trap 34 
     122 * Dummy interrupt service procedure for
     123 * interrupts being not allowed --> Trap 34
    124124 ************************************************/
    125125asm(" .section .text\n\
     
    134134
    135135/*****************************
    136  * Non maskable interrupt 
     136 * Non maskable interrupt
    137137 *****************************/
    138138isp( _nmi_isp, NMI_ISP_V, ___ISR_Handler);
    139139
    140 /***************************** 
    141  * User break controller 
     140/*****************************
     141 * User break controller
    142142 *****************************/
    143143isp( _usb_isp, USB_ISP_V, ___ISR_Handler);
    144144
    145145/*****************************
    146  *  External interrupts 0-7 
     146 *  External interrupts 0-7
    147147 *****************************/
    148148isp( _irq0_isp, IRQ0_ISP_V, ___ISR_Handler);
     
    156156
    157157/*****************************
    158  * DMA - controller 
     158 * DMA - controller
    159159 *****************************/
    160160isp( _dma0_isp, DMA0_ISP_V, ___ISR_Handler);
     
    164164
    165165
    166 /***************************** 
    167  * Interrupt timer unit 
    168  *****************************/
    169 
    170 /*****************************
    171  * Timer 0 
     166/*****************************
     167 * Interrupt timer unit
     168 *****************************/
     169
     170/*****************************
     171 * Timer 0
    172172 *****************************/
    173173isp( _imia0_isp, IMIA0_ISP_V, ___ISR_Handler);
     
    205205
    206206/*****************************
    207  * Serial interfaces 
     207 * Serial interfaces
    208208 *****************************/
    209209
     
    226226
    227227/*****************************
    228  * Parity control unit of 
    229  * the bus state controller 
     228 * Parity control unit of
     229 * the bus state controller
    230230 *****************************/
    231231isp( _prt_isp,  PRT_ISP_V, ___ISR_Handler);
    232232
    233233
    234 /****************************** 
     234/******************************
    235235 * Analog digital converter
    236  * ADC 
     236 * ADC
    237237 ******************************/
    238238isp( _adu_isp,  ADU_ISP_V, ___ISR_Handler);
     
    240240
    241241/******************************
    242  *  Watchdog timer 
     242 *  Watchdog timer
    243243 ******************************/
    244244isp( _wdt_isp,  WDT_ISP_V, ___ISR_Handler);
     
    246246
    247247/******************************
    248  * DRAM refresh control unit 
    249  * of bus state controller 
     248 * DRAM refresh control unit
     249 * of bus state controller
    250250 ******************************/
    251251isp( _dref_isp,  DREF_ISP_V, ___ISR_Handler);
  • c/src/lib/libcpu/sh/sh7032/timer/timer.c

    raed742c r3906b3ea  
    11/*
    2  *  timer for the Hitachi SH 703X 
     2 *  timer for the Hitachi SH 703X
    33 *
    44 *  This file manages the benchmark timer used by the RTEMS Timing Test
     
    4242/*
    4343 * Set I_CLK_PHI to one of the I_CLK_PHI_X values from above to choose
    44  * a PHI/X clock rate. 
    45  */
    46    
     44 * a PHI/X clock rate.
     45 */
     46
    4747#define I_CLK_PHI       I_CLK_PHI_4
    4848#define CLOCK_SCALE     (1<<I_CLK_PHI)
     
    155155   *  Read the timer and see how many clicks it has been since we started.
    156156   */
    157  
     157
    158158
    159159  cclicks = read16( ITU_TCNT1);   /* XXX: read some HW here */
    160  
     160
    161161  /*
    162162   *  Total is calculated by taking into account the number of timer overflow
     
    169169  if ( Timer_driver_Find_average_overhead )
    170170    return total / CLOCK_SCALE;          /* in XXX microsecond units */
    171   else 
     171  else
    172172  {
    173173    if ( total < LEAST_VALID )
  • c/src/lib/libcpu/sh/sh7045/clock/ckinit.c

    raed742c r3906b3ea  
    1010 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    1111 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
    12  * 
     12 *
    1313 *
    1414 *  COPYRIGHT (c) 1998.
     
    9292 * These are set by clock driver during its init
    9393 */
    94  
     94
    9595rtems_device_major_number rtems_clock_major = ~0;
    9696rtems_device_minor_number rtems_clock_minor;
     
    151151  uint8_t   temp8 = 0;
    152152  uint32_t   factor = 1000000;
    153  
    154  
     153
     154
    155155  /*
    156156   *  Initialize the clock tick device driver variables
     
    160160  Clock_isrs_const = rtems_configuration_get_microseconds_per_tick() / 10000;
    161161  Clock_isrs = Clock_isrs_const;
    162  
     162
    163163  factor /= rtems_configuration_get_microseconds_per_tick(); /* minimalization of integer division error */
    164164  Clock_MHZ = rtems_cpu_configuration_get_clicks_per_second() / factor ;
     
    169169   *  Hardware specific initialize goes here
    170170   */
    171    
     171
    172172  /* stop Timer 0 */
    173173  temp8 = read8( MTU_TSTR) & MTU0_STARTMASK;
     
    189189
    190190  /* use GRA without I/O - pins  */
    191   write8( MTU0_TIORVAL, MTU_TIORL0); 
    192    
     191  write8( MTU0_TIORVAL, MTU_TIORL0);
     192
    193193  /* reset flags of the status register */
    194194  temp8 = read8( MTU_TSR0) & MTU0_STAT_MASK;
     
    205205  /* set counter limits */
    206206  write16( _MTU_COUNTER0_MICROSECOND, MTU_GR0A);
    207    
     207
    208208  /* start counter */
    209209  temp8 = read8( MTU_TSTR) |~MTU0_STARTMASK;
     
    255255{
    256256  Install_clock( Clock_isr );
    257  
     257
    258258  /*
    259259   * make major/minor avail to others such as shared memory driver
    260260   */
    261  
     261
    262262  rtems_clock_major = major;
    263263  rtems_clock_minor = minor;
    264  
     264
    265265  return RTEMS_SUCCESSFUL;
    266266}
     
    274274  uint32_t   isrlevel;
    275275  rtems_libio_ioctl_args_t *args = pargp;
    276  
     276
    277277  if (args != 0)
    278278    {
     
    281281       * to do this, it will just be this simple...
    282282       */
    283      
     283
    284284      if (args->command == rtems_build_name('I', 'S', 'R', ' '))
    285285        {
     
    291291          rtems_interrupt_disable( isrlevel );
    292292          rtems_interrupt_catch( args->buffer, CLOCK_VECTOR, &ignored );
    293          
     293
    294294          rtems_interrupt_enable( isrlevel );
    295295        }
  • c/src/lib/libcpu/sh/sh7045/include/io_types.h

    raed742c r3906b3ea  
    3131 *
    3232 ************************************************************************/
    33  
     33
    3434#ifndef _sh_io_types_h
    3535#define _sh_io_types_h
    36  
     36
    3737#include <rtems/score/iosh7045.h>
    3838#include <termios.h>
     
    4747  int      speed_ix;
    4848  dataBits dBits;
    49   int      parEn;       
     49  int      parEn;
    5050  parity   par;
    5151  int      mulPro;
  • c/src/lib/libcpu/sh/sh7045/include/iosh7045.h

    raed742c r3906b3ea  
    88 *           Bernd Becker (becker@faw.uni-ulm.de)
    99 *
    10  *  Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which 
     10 *  Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which
    1111 *  contained no copyright notice.
    1212 *
     
    1616 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    1717 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
    18  * 
     18 *
    1919 *
    2020 *  COPYRIGHT (c) 1998.
     
    2525 *  http://www.rtems.com/license/LICENSE.
    2626 *
    27  *      Modified to reflect on-chip registers for sh7045 processor, based on 
    28  *      "Register.h" distributed with Hitachi's EVB7045F tutorials, and which 
     27 *      Modified to reflect on-chip registers for sh7045 processor, based on
     28 *      "Register.h" distributed with Hitachi's EVB7045F tutorials, and which
    2929 *  contained no copyright notice:
    3030 *      John M. Mills (jmills@tga.com)
     
    4747/*
    4848 * After each line is explained whether the access is char short or long.
    49  * The functions read/writeb, w, l, 8, 16, 32 can be found 
     49 * The functions read/writeb, w, l, 8, 16, 32 can be found
    5050 * in exec/score/cpu/sh/sh_io.h
    5151 *
  • c/src/lib/libcpu/sh/sh7045/include/ispsh7045.h

    raed742c r3906b3ea  
    1111 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    1212 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
    13  * 
     13 *
    1414 *
    1515 *  COPYRIGHT (c) 1998.
     
    2525 *  100 Pinnacle Way, Suite 140
    2626 *  Norcross, GA 30071 U.S.A.
    27  * 
     27 *
    2828 *
    2929 *  This modified file may be copied and distributed in accordance
  • c/src/lib/libcpu/sh/sh7045/include/sci.h

    raed742c r3906b3ea  
    1010 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    1111 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
    12  * 
     12 *
    1313 *
    1414 *  COPYRIGHT (c) 1998.
     
    3333/*
    3434 * Devices are set to 9600 bps, 8 databits, 1 stopbit, no
    35  * parity and asynchronous mode by default. 
     35 * parity and asynchronous mode by default.
    3636 *
    3737 * NOTE:
    38  *       The onboard serial devices of the SH do not support hardware 
     38 *       The onboard serial devices of the SH do not support hardware
    3939 *       handshake.
    40  */ 
     40 */
    4141
    4242#define DEVSCI_DRIVER_TABLE_ENTRY \
     
    7979  void *
    8080);
    81    
    82 extern const rtems_termios_callbacks * sh_sci_get_termios_handlers( 
    83   rtems_boolean poll 
     81
     82extern const rtems_termios_callbacks * sh_sci_get_termios_handlers(
     83  rtems_boolean poll
    8484);
    85    
     85
    8686
    8787#ifdef __cplusplus
  • c/src/lib/libcpu/sh/sh7045/include/sci_termios.h

    raed742c r3906b3ea  
    1919
    2020
    21 int sh_sci_set_attributes( 
     21int sh_sci_set_attributes(
    2222  int minor,
    2323  const struct termios *t
     
    2727
    2828void sh_sci_init(int minor);
    29    
     29
    3030int sh_sci_write_support_int(
    31     int         minor, 
    32     const char *buf, 
     31    int         minor,
     32    const char *buf,
    3333    int         len
    3434);
    35    
     35
    3636int sh_sci_write_support_polled(
    3737  int         minor,
     
    3939  int         len
    4040);
    41    
     41
    4242void sh_sci_write_polled(
    4343    int minor,
     
    4646
    4747int sh_sci_inbyte_nonblocking_polled(int minor);
    48    
     48
    4949
    5050int sh_sci_first_open(
    5151  int major,
    5252  int minor,
    53   void *arg 
     53  void *arg
    5454);
    5555
  • c/src/lib/libcpu/sh/sh7045/include/sh7_pfc.h

    raed742c r3906b3ea  
    192192#define PB0MD1     0x0002
    193193#define PB0MD0     0x0001
    194        
     194
    195195#define PB7MD      PB7MD1|PB7MD0
    196196#define PB6MD      PB6MD1|PB6MD0
  • c/src/lib/libcpu/sh/sh7045/sci/sci.c

    raed742c r3906b3ea  
    22 * /dev/sci[0|1] for Hitachi SH 704X
    33 *
    4  * The SH doesn't have a designated console device. Therefore we "alias" 
    5  * another device as /dev/console and revector all calls to /dev/console 
     4 * The SH doesn't have a designated console device. Therefore we "alias"
     5 * another device as /dev/console and revector all calls to /dev/console
    66 * to this device.
    77 *
    8  * This approach is similar to installing a sym-link from one device to 
    9  * another device. If rtems once will support sym-links for devices files, 
     8 * This approach is similar to installing a sym-link from one device to
     9 * another device. If rtems once will support sym-links for devices files,
    1010 * this implementation could be dropped.
    1111 *
     
    1717 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    1818 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
    19  * 
     19 *
    2020 *
    2121 *  COPYRIGHT (c) 1998.
     
    6262 * NOTE: Some SH variants have 3 sci devices
    6363 */
    64  
     64
    6565#define SCI_MINOR_DEVICES       2
    66  
     66
    6767/*
    6868 * FIXME: sh7045 register names match Hitachi data book,
     
    107107  uint8_t       smr ;
    108108  uint8_t       brr ;
    109  
     109
    110110  if ( c_cflag & CBAUD )
    111111  {
     
    113113      return -1 ;
    114114  }
    115                    
     115
    116116  if ( c_cflag & CSIZE )
    117117  {
     
    138138  else
    139139    smr &= ~SCI_ODD_PARITY;
    140    
     140
    141141  write8( smr, sci_dev->addr + SCI_SMR );
    142142  write8( brr, sci_dev->addr + SCI_BRR );
    143  
     143
    144144  return 0 ;
    145145}
     
    256256{
    257257        char ch;
    258        
     258
    259259        if (minor == 0) /* blocks until char.ready */
    260260                while (rdSCI0(&ch) != TRUE); /* SCI0 */
     
    297297  rtems_device_minor_number i;
    298298  rtems_driver_name_t driver;
    299  
    300  
     299
     300
    301301  /*
    302302   * register all possible devices.
     
    342342  uint8_t   temp8;
    343343  uint16_t   temp16;
    344  
     344
    345345  unsigned      a ;
    346  
     346
    347347 /* check for valid minor number */
    348348   if(( minor > ( SCI_MINOR_DEVICES -1 )) || ( minor < 0 ))
     
    350350     return RTEMS_INVALID_NUMBER;
    351351   }
    352  
     352
    353353  /* device already opened */
    354354  if ( sci_device[minor].opened > 0 )
     
    357357    return RTEMS_SUCCESSFUL ;
    358358  }
    359    
     359
    360360  /* set PFC registers to enable I/O pins */
    361361
     
    365365    temp16 |= (PA_TXD0 | PA_RXD0);       /* enable pins for Tx0, Rx0 */
    366366    write16(temp16, PFC_PACRL2);
    367    
    368   } else if (minor == 1) { 
     367
     368  } else if (minor == 1) {
    369369    temp16 = read16(PFC_PACRL2);          /* disable SCK1, DMA, IRQ */
    370370    temp16 &= ~(PA5MD1 | PA5MD0);
     
    391391        temp8 = read8(sci_device[minor].addr + SCI_RDR);   /* flush input */
    392392        temp8 = read8(sci_device[minor].addr + SCI_SSR); /* clear some flags */
    393         write8(temp8 & ~(SCI_RDRF | SCI_ORER | SCI_FER | SCI_PER), 
     393        write8(temp8 & ~(SCI_RDRF | SCI_ORER | SCI_FER | SCI_PER),
    394394               sci_device[minor].addr + SCI_SSR);
    395395        temp8 = read8(sci_device[minor].addr + SCI_SSR); /* check if everything is OK */
    396     }   
     396    }
    397397    /* Clear RDRF flag */
    398398    write8(0x00, sci_device[minor].addr + SCI_TDR);    /* force output */
     
    400400     temp8 = read8(sci_device[minor].addr + SCI_SSR) & ~SCI_TDRE;
    401401     write8(temp8, sci_device[minor].addr + SCI_SSR);
    402    
     402
    403403    /* add interrupt setup if required */
    404404
    405  
     405
    406406  sci_device[minor].opened++ ;
    407407
    408408  return RTEMS_SUCCESSFUL ;
    409409}
    410  
     410
    411411/*
    412412 *  Close entry point
     
    424424  else
    425425    return RTEMS_INVALID_NUMBER ;
    426    
     426
    427427  return RTEMS_SUCCESSFUL ;
    428428}
     
    442442  int maximum;
    443443  int count = 0;
    444  
     444
    445445  rw_args = (rtems_libio_rw_args_t *) arg;
    446446
     
    461461
    462462/*
    463  * write bytes to the serial port. Stdout and stderr are the same. 
     463 * write bytes to the serial port. Stdout and stderr are the same.
    464464 */
    465465
     
    528528    int value = -1;
    529529    char ch;
    530    
     530
    531531    if( minor == 0 ){
    532532        if( rdSCI0( &ch ) )
     
    540540
    541541/*
    542  * Termios polled write 
     542 * Termios polled write
    543543 */
    544544static int _sh_sci_poll_write(int minor, const char *buf, int len)
    545545{
    546546    int count;
    547    
     547
    548548    for(count = 0; count < len; count++)
    549549        outbyte( minor, buf[count] );
  • c/src/lib/libcpu/sh/sh7045/sci/sci_termios.c

    raed742c r3906b3ea  
    3535
    3636
    37 /* 
     37/*
    3838 * Some handy macros
    3939 */
     
    5252 * NOTE: Some SH variants have 3 sci devices
    5353 */
    54  
     54
    5555#define SCI_MINOR_DEVICES       2
    5656
    5757
    58 /* 
    59  * Automatically generated function imported from scitab.rel 
     58/*
     59 * Automatically generated function imported from scitab.rel
    6060 */
    6161extern int _sci_get_brparms(
     
    6464  unsigned char *brr );
    6565
    66 /* 
     66/*
    6767 * Translate termios flags into SCI settings
    6868 */
    69 int sh_sci_set_attributes( 
     69int sh_sci_set_attributes(
    7070  int minor,
    7171  const struct termios *t
     
    7575    uint8_t     brr ;
    7676    int a;
    77    
     77
    7878    tcflag_t c_cflag = t->c_cflag;
    7979
     
    8383            return -1 ;
    8484    }
    85                    
     85
    8686    if ( c_cflag & CSIZE )
    8787    {
     
    110110
    111111    SH_SCI_REG_MASK((SCI_RE | SCI_TE), minor, SCI_SCR);
    112    
     112
    113113    SH_SCI_REG_DATA(smr, minor, SCI_SMR);
    114114    SH_SCI_REG_DATA(brr, minor, SCI_BRR);
    115    
     115
    116116    for(a=0; a < 10000L; a++) { /* Delay one bit */
    117117        asm volatile ("nop");
     
    119119
    120120    SH_SCI_REG_FLAG((SCI_RE | SCI_TE), minor, SCI_SCR);
    121    
     121
    122122    return 0;
    123123}
    124124
    125 /* 
     125/*
    126126 * Receive-data-full ISR
    127127 *
    128  * The same routine for all interrupt sources of the same type. 
     128 * The same routine for all interrupt sources of the same type.
    129129 */
    130130rtems_isr sh_sci_rx_isr(rtems_vector_number vector)
    131131{
    132132    int minor;
    133    
     133
    134134    for(minor = 0; minor < Console_Port_Count; minor++)
    135135    {
    136136        if(Console_Port_Tbl[minor].ulIntVector == vector)
    137         {             
     137        {
    138138            uint8_t   temp8;
    139            
     139
    140140            /*
    141141             * FIXME: error handling should be added
     
    153153}
    154154
    155 /* 
     155/*
    156156 * Transmit-data-empty ISR
    157157 *
     
    166166        if(Console_Port_Tbl[minor].ulDataPort == vector)
    167167        {
    168             /* 
     168            /*
    169169             * FIXME: Error handling should be added
    170170             */
    171    
    172             /* 
     171
     172            /*
    173173             * Mask end-of-transmission interrupt
    174174             */
     
    178178                   Console_Port_Data[minor].termios_data, 1))
    179179            {
    180                 /* 
     180                /*
    181181                 * More characters to be received - interrupt must be enabled
    182182                 */
     
    189189
    190190
    191 /* 
     191/*
    192192 * Initialization of serial port
    193193 */
     
    195195{
    196196    uint16_t   temp16;
    197    
    198     /* 
    199      * set PFC registers to enable I/O pins 
    200      */
    201     if ((minor == 0)) 
     197
     198    /*
     199     * set PFC registers to enable I/O pins
     200     */
     201    if ((minor == 0))
    202202    {
    203203        temp16 = read16(PFC_PACRL2);         /* disable SCK0, DMA, IRQ */
     
    205205        temp16 |= (PA_TXD0 | PA_RXD0);       /* enable pins for Tx0, Rx0 */
    206206        write16(temp16, PFC_PACRL2);
    207    
    208     } 
    209     else if (minor == 1) 
    210     { 
     207
     208    }
     209    else if (minor == 1)
     210    {
    211211        temp16 = read16(PFC_PACRL2);          /* disable SCK1, DMA, IRQ */
    212212        temp16 &= ~(PA5MD1 | PA5MD0);
    213213        temp16 |= (PA_TXD1 | PA_RXD1);        /* enable pins for Tx1, Rx1 */
    214214        write16(temp16, PFC_PACRL2);
    215     } 
    216 
    217     /* 
     215    }
     216
     217    /*
    218218     * Non-default hardware setup occurs in sh_sci_first_open
    219219     */
    220220}
    221221
    222 /* 
     222/*
    223223 * Initialization of interrupts
    224224 *
     
    232232
    233233    sh_sci_init(minor);
    234     /* 
     234    /*
    235235     * Disable IRQ of SCIx
    236236     */
    237237    status = sh_set_irq_priority(
    238         Console_Port_Tbl[minor].ulIntVector, 0); 
     238        Console_Port_Tbl[minor].ulIntVector, 0);
    239239
    240240    if(status != RTEMS_SUCCESSFUL)
     
    243243    SH_SCI_REG_MASK(SCI_RIE, minor, SCI_SCR);
    244244
    245     /* 
     245    /*
    246246     * Catch apropriate vectors
    247247     */
    248248    status = rtems_interrupt_catch(
    249         sh_sci_rx_isr, 
     249        sh_sci_rx_isr,
    250250        Console_Port_Tbl[minor].ulIntVector,
    251251        &old_isr);
     
    261261    if(status != RTEMS_SUCCESSFUL)
    262262        rtems_fatal_error_occurred(status);
    263    
    264     /* 
    265      * Enable IRQ of SCIx 
     263
     264    /*
     265     * Enable IRQ of SCIx
    266266     */
    267267    SH_SCI_REG_FLAG(SCI_RIE, minor, SCI_SCR);
    268268
    269269    status = sh_set_irq_priority(
    270         Console_Port_Tbl[minor].ulIntVector, 
     270        Console_Port_Tbl[minor].ulIntVector,
    271271        Console_Port_Tbl[minor].ulCtrlPort2);
    272272
     
    288288    uint8_t   temp8;
    289289    unsigned int a ;
    290  
    291     /* 
    292      * check for valid minor number 
     290
     291    /*
     292     * check for valid minor number
    293293     */
    294294    if(( minor > ( SCI_MINOR_DEVICES -1 )) || ( minor < 0 ))
     
    297297    }
    298298
    299     /* 
    300      * set up SCI registers 
     299    /*
     300     * set up SCI registers
    301301     */
    302302    /* Clear SCR - disable Tx and Rx */
    303303    SH_SCI_REG_DATA(0x00, minor, SCI_SCR);
    304    
     304
    305305    /* set SMR and BRR - baudrate and format */
    306306    sh_sci_set_attributes(minor, Console_Port_Tbl[minor].pDeviceParams);
     
    313313           Console_Port_Tbl[minor].ulCtrlPort1 + SCI_SCR);
    314314
    315     /* 
    316      * clear error flags 
     315    /*
     316     * clear error flags
    317317     */
    318318    temp8 = read8(Console_Port_Tbl[minor].ulCtrlPort1 + SCI_SSR);
     
    324324        /* clear some flags */
    325325        SH_SCI_REG_FLAG((SCI_RDRF | SCI_ORER | SCI_FER | SCI_PER), minor, SCI_SSR);
    326        
     326
    327327        /* check if everything is OK */
    328328        temp8 = read8(Console_Port_Tbl[minor].ulCtrlPort1 + SCI_SSR);
    329     }   
    330    
     329    }
     330
    331331    /* Clear RDRF flag */
    332332    SH_SCI_REG_DATA(0x00, minor, SCI_TDR); /* force output */
    333    
     333
    334334    /* Clear the TDRE bit */
    335335    SH_SCI_REG_FLAG(SCI_TDRE, minor, SCI_SSR);
    336    
    337     /* 
    338      * Interrupt setup 
     336
     337    /*
     338     * Interrupt setup
    339339     */
    340340    if(Console_Port_Tbl[minor].pDeviceFns->deviceOutputUsesInterrupts)
     
    342342        SH_SCI_REG_FLAG(SCI_RIE, minor, SCI_SCR);
    343343    }
    344    
     344
    345345    return RTEMS_SUCCESSFUL ;
    346346}
     
    366366}
    367367
    368 /* 
     368/*
    369369 * Interrupt aware write routine
    370370 */
    371371int sh_sci_write_support_int(
    372     int         minor, 
    373     const char *buf, 
     372    int         minor,
     373    const char *buf,
    374374    int         len
    375375)
     
    382382    SH_SCI_REG_DATA(*buf, minor, SCI_TDR);
    383383    SH_SCI_REG_MASK(SCI_TDRE, minor, SCI_SSR);
    384     /* 
     384    /*
    385385     * Enable interrupt
    386386     */
    387387    SH_SCI_REG_FLAG(SCI_TIE, minor, SCI_SCR);
    388    
     388
    389389    return 1;
    390390}
    391391
    392 /* 
     392/*
    393393 * Polled write method
    394394 */
     
    400400{
    401401    int count = 0;
    402    
     402
    403403    while(count < len)
    404404    {
     
    406406        count++;
    407407    }
    408     /* 
     408    /*
    409409     * Return number of bytes written
    410410     */
     
    412412}
    413413
    414 /* 
     414/*
    415415 * Polled write of one character at a time
    416416 */
     
    420420)
    421421{
    422     /* 
     422    /*
    423423     * Wait for end of previous character
    424424     */
    425425    while(!(read8(Console_Port_Tbl[minor].ulCtrlPort1 + SCI_SSR) & SCI_TDRE));
    426     /* 
     426    /*
    427427     * Send the character
    428428     */
    429429    SH_SCI_REG_DATA(c, minor, SCI_TDR);
    430    
    431     /* 
     430
     431    /*
    432432     * Clear TDRE flag
    433433     */
     
    435435}
    436436
    437 /* 
    438  * Non-blocking read 
     437/*
     438 * Non-blocking read
    439439 */
    440440int sh_sci_inbyte_nonblocking_polled(int minor)
     
    442442    uint8_t   inbyte;
    443443
    444     /* 
     444    /*
    445445     * Check if input buffer is full
    446446     */
     
    449449        inbyte = read8(Console_Port_Tbl[minor].ulCtrlPort1 + SCI_RDR);
    450450        SH_SCI_REG_MASK(SCI_RDRF, minor, SCI_SSR);
    451        
    452         /* 
     451
     452        /*
    453453         * Check for errors
    454454         */
    455         if(read8(Console_Port_Tbl[minor].ulCtrlPort1 + SCI_SSR) & 
     455        if(read8(Console_Port_Tbl[minor].ulCtrlPort1 + SCI_SSR) &
    456456           (SCI_ORER | SCI_FER | SCI_PER))
    457457        {
    458458            SH_SCI_REG_MASK((SCI_ORER | SCI_FER | SCI_PER), minor, SCI_SSR);
    459459            return -1;
    460         }     
     460        }
    461461        return (int)inbyte;
    462462    }
  • c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c

    raed742c r3906b3ea  
    1414 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    1515 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
    16  * 
     16 *
    1717 *
    1818 *  COPYRIGHT (c) 1998.
     
    4949#endif
    5050
    51 register unsigned long  *stack_ptr asm("r15"); 
    52 
    53 /* 
     51register unsigned long  *stack_ptr asm("r15");
     52
     53/*
    5454 * sh_set_irq_priority
    55  * 
     55 *
    5656 * this function sets the interrupt level of the specified interrupt
    5757 *
    5858 * parameters:
    59  *             - irq : interrupt number 
     59 *             - irq : interrupt number
    6060 *             - prio: priority to set for this interrupt number
    6161 *
     
    6464 */
    6565
    66 unsigned int sh_set_irq_priority( 
    67   unsigned int irq, 
     66unsigned int sh_set_irq_priority(
     67  unsigned int irq,
    6868  unsigned int prio )
    6969{
     
    9191      irq = irq - 72;
    9292      shiftcount = 12 - ((irq & ~0x03) % 16);
    93      
     93
    9494      switch( irq / 16)
    9595        {
     
    186186
    187187/*
    188  * FIXME: This is an ugly hack, but we wanted to avoid recalculating 
     188 * FIXME: This is an ugly hack, but we wanted to avoid recalculating
    189189 *        the offset each time Context_Control is changed
    190190 */
     
    254254}
    255255
    256 /* 
     256/*
    257257 *  This routine provides the RTEMS interrupt management.
    258258 */
    259  
     259
    260260void __ISR_Handler( uint32_t   vector)
    261261{
     
    294294  if( _ISR_Nest_level == 0 )
    295295    /* restore old stack pointer */
    296     stack_ptr = _old_stack_ptr; 
     296    stack_ptr = _old_stack_ptr;
    297297#endif
    298298
  • c/src/lib/libcpu/sh/sh7045/score/ispsh7045.c

    raed742c r3906b3ea  
    44 * as argument.
    55 *
    6  * __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in 
    7  * some releases of gcc doesn't properly handle #pragma interrupt, if a 
     6 * __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in
     7 * some releases of gcc doesn't properly handle #pragma interrupt, if a
    88 * file contains both isrs and normal functions.
    99 *
     
    1616 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    1717 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
    18  * 
     18 *
    1919 *
    2020 *  COPYRIGHT (c) 1998.
     
    5555proc_ptr _Hardware_isr_Table[256]={
    5656_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,         /* PWRon Reset, Maual Reset,...*/
    57 _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
     57_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
    5858_dummy_isp, _dummy_isp, _dummy_isp,
    5959_nmi_isp, _usb_isp,                               /* irq 11, 12*/
    60 _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
    61 _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
    62 _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
    63 _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
    64 _dummy_isp, _dummy_isp, _dummy_isp, 
     60_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
     61_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
     62_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
     63_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
     64_dummy_isp, _dummy_isp, _dummy_isp,
    6565/* trapa 0 -31 */
    66 _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
    67 _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
    68 _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
    69 _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
    70 _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
    71 _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
    72 _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
    73 _dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
     66_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
     67_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
     68_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
     69_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
     70_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
     71_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
     72_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
     73_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
    7474_irq0_isp, _irq1_isp, _irq2_isp, _irq3_isp,   /* external H/W: irq 64-71 */
    7575_irq4_isp, _irq5_isp, _irq6_isp, _irq7_isp,
     
    7979_dma3_isp, _dummy_isp, _dummy_isp, _dummy_isp,
    8080_mtua0_isp, _mtub0_isp, _mtuc0_isp, _mtud0_isp, /* MTUs: irq 88-127 */
    81 _mtuv0_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
     81_mtuv0_isp, _dummy_isp, _dummy_isp, _dummy_isp,
    8282_mtua1_isp, _mtub1_isp, _dummy_isp, _dummy_isp,
    83 _mtuv1_isp, _mtuu1_isp, _dummy_isp, _dummy_isp, 
     83_mtuv1_isp, _mtuu1_isp, _dummy_isp, _dummy_isp,
    8484_mtua2_isp, _mtub2_isp, _dummy_isp, _dummy_isp,
    85 _mtuv2_isp, _mtuu2_isp, _dummy_isp, _dummy_isp, 
     85_mtuv2_isp, _mtuu2_isp, _dummy_isp, _dummy_isp,
    8686_mtua3_isp, _mtub3_isp, _mtuc3_isp, _mtud3_isp,
    87 _mtuv3_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
     87_mtuv3_isp, _dummy_isp, _dummy_isp, _dummy_isp,
    8888_mtua4_isp, _mtub4_isp, _mtuc4_isp, _mtud4_isp,
    89 _mtuv4_isp, _dummy_isp, _dummy_isp, _dummy_isp, 
     89_mtuv4_isp, _dummy_isp, _dummy_isp, _dummy_isp,
    9090_eri0_isp, _rxi0_isp, _txi0_isp, _tei0_isp, /* SCI0-1: irq 128-135*/
    9191_eri1_isp, _rxi1_isp, _txi1_isp, _tei1_isp,
     
    103103/*
    104104 * Some versions of gcc and all version of egcs at least until egcs-1.1b
    105  * are not able to handle #pragma interrupt correctly if more than 1 isr is 
     105 * are not able to handle #pragma interrupt correctly if more than 1 isr is
    106106 * contained in a file and when optimizing.
    107107 * We try to work around this problem by using the macro below.
     
    149149
    150150/************************************************
    151  * Dummy interrupt service procedure for 
    152  * interrupts being not allowed --> Trap 34 
     151 * Dummy interrupt service procedure for
     152 * interrupts being not allowed --> Trap 34
    153153 ************************************************/
    154154asm(" .section .text\n\
     
    168168
    169169/*****************************
    170  * Non maskable interrupt 
     170 * Non maskable interrupt
    171171 *****************************/
    172172isp( _nmi_isp, NMI_ISP_V, ___ISR_Handler);
    173173
    174 /***************************** 
    175  * User break controller 
     174/*****************************
     175 * User break controller
    176176 *****************************/
    177177isp( _usb_isp, USB_ISP_V, ___ISR_Handler);
    178178
    179179/*****************************
    180  *  External interrupts 0-7 
     180 *  External interrupts 0-7
    181181 *****************************/
    182182isp( _irq0_isp, IRQ0_ISP_V, ___ISR_Handler);
     
    190190
    191191/*****************************
    192  * DMA - controller 
     192 * DMA - controller
    193193 *****************************/
    194194isp( _dma0_isp, DMA0_ISP_V, ___ISR_Handler);
     
    198198
    199199
    200 /***************************** 
    201  * Match timer unit 
    202  *****************************/
    203 
    204 /*****************************
    205  * Timer 0 
     200/*****************************
     201 * Match timer unit
     202 *****************************/
     203
     204/*****************************
     205 * Timer 0
    206206 *****************************/
    207207isp( _mtua0_isp, MTUA0_ISP_V, ___ISR_Handler);
     
    247247
    248248/*****************************
    249  * Serial interfaces 
     249 * Serial interfaces
    250250 *****************************/
    251251
     
    267267
    268268
    269 /****************************** 
     269/******************************
    270270 * A/D converters
    271  * ADC0-1 
     271 * ADC0-1
    272272 ******************************/
    273273isp( _adi0_isp,  ADI0_ISP_V, ___ISR_Handler);
     
    276276
    277277/******************************
    278  *  Data transfer controller 
     278 *  Data transfer controller
    279279 ******************************/
    280280isp( _dtci_isp,  DTC_ISP_V, ___ISR_Handler);
     
    282282
    283283/******************************
    284  *  Counter match timer 
     284 *  Counter match timer
    285285 ******************************/
    286286isp( _cmt0_isp,  CMT0_ISP_V, ___ISR_Handler);
     
    289289
    290290/******************************
    291  *  Watchdog timer 
     291 *  Watchdog timer
    292292 ******************************/
    293293isp( _wdt_isp,  WDT_ISP_V, ___ISR_Handler);
     
    295295
    296296/******************************
    297  * DRAM refresh control unit 
    298  * of bus state controller 
     297 * DRAM refresh control unit
     298 * of bus state controller
    299299 ******************************/
    300300isp( _bsc_isp,  CMI_ISP_V, ___ISR_Handler);
     
    307307
    308308/*****************************
    309  * Parity control unit of 
    310  * the bus state controller 
     309 * Parity control unit of
     310 * the bus state controller
    311311 * NOT PROVIDED IN SH-2
    312312 *****************************/
  • c/src/lib/libcpu/sh/sh7045/timer/timer.c

    raed742c r3906b3ea  
    11/*
    2  *  timer for the Hitachi SH 704X 
     2 *  timer for the Hitachi SH 704X
    33 *
    44 *  This file manages the benchmark timer used by the RTEMS Timing Test
     
    7070
    7171  Timer_MHZ = rtems_cpu_configuration_get_clicks_per_second() / 1000000 ;
    72  
     72
    7373  /*
    7474   *  Timer has never overflowed.  This may not be necessary on some
     
    151151   *  Read the timer and see how many clicks it has been since we started.
    152152   */
    153  
     153
    154154
    155155  clicks = read16( MTU_TCNT1);   /* XXX: read some HW here */
    156  
     156
    157157  /*
    158158   *  Total is calculated by taking into account the number of timer overflow
     
    165165  if ( Timer_driver_Find_average_overhead )
    166166    return total / SCALE;          /* in XXX microsecond units */
    167   else 
     167  else
    168168  {
    169169    if ( total < LEAST_VALID )
  • c/src/lib/libcpu/sh/sh7750/clock/ckinit.c

    raed742c r3906b3ea  
    7171 * PARAMETERS:
    7272 *     vector - interrupt vector number
    73  * 
     73 *
    7474 * RETURNS:
    7575 *     none
    7676 */
    77 rtems_isr 
     77rtems_isr
    7878Clock_isr(rtems_vector_number vector)
    7979{
     
    104104 *     Establish clock interrupt handler, configure Timer 0 hardware
    105105 */
    106 void 
     106void
    107107Install_clock(rtems_isr_entry clock_isr)
    108108{
     
    112112    uint8_t   temp8;
    113113    uint16_t   temp16;
    114  
     114
    115115    /*
    116116     *  Initialize the clock tick device driver variables
     
    125125            cpudiv = 1;
    126126            break;
    127        
     127
    128128        case SH7750_FRQCR_IFCDIV2:
    129129            cpudiv = 2;
    130130            break;
    131            
     131
    132132        case SH7750_FRQCR_IFCDIV3:
    133133            cpudiv = 3;
    134134            break;
    135        
     135
    136136        case SH7750_FRQCR_IFCDIV4:
    137137            cpudiv = 4;
    138138            break;
    139        
     139
    140140        case SH7750_FRQCR_IFCDIV6:
    141141            cpudiv = 6;
    142142            break;
    143        
     143
    144144        case SH7750_FRQCR_IFCDIV8:
    145145            cpudiv = 8;
    146146            break;
    147        
     147
    148148        default:
    149149            rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED);
     
    156156            tidiv = 2 * CLOCK_PRESCALER;
    157157            break;
    158            
     158
    159159        case SH7750_FRQCR_PFCDIV3:
    160160            tidiv = 3 * CLOCK_PRESCALER;
    161161            break;
    162        
     162
    163163        case SH7750_FRQCR_PFCDIV4:
    164164            tidiv = 4 * CLOCK_PRESCALER;
    165165            break;
    166        
     166
    167167        case SH7750_FRQCR_PFCDIV6:
    168168            tidiv = 6 * CLOCK_PRESCALER;
    169169            break;
    170        
     170
    171171        case SH7750_FRQCR_PFCDIV8:
    172172            tidiv = 8 * CLOCK_PRESCALER;
    173173            break;
    174        
     174
    175175        default:
    176176            rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED);
    177177    }
    178     timer_divider = 
    179         (rtems_cpu_configuration_get_clicks_per_second() * 
     178    timer_divider =
     179        (rtems_cpu_configuration_get_clicks_per_second() *
    180180         cpudiv / (tidiv*1000000)) *
    181181        rtems_configuration_get_microseconds_per_tick();
     
    184184     *  Hardware specific initialization
    185185     */
    186  
     186
    187187    /* Stop the Timer 0 */
    188188    temp8 = read8(SH7750_TSTR);
     
    198198    /* Load divider */
    199199    write32(timer_divider, SH7750_TCOR0);
    200    
     200
    201201    write16(
    202202        SH7750_TCR_UNIE |        /* Enable Underflow Interrupt */
     
    234234 *     Stop Timer 0 counting, set timer 0 interrupt priority level to 0.
    235235 */
    236 void 
     236void
    237237Clock_exit(void)
    238238{
     
    265265 *     RTEMS_SUCCESSFUL
    266266 */
    267 rtems_device_driver 
    268 Clock_initialize(rtems_device_major_number major, 
     267rtems_device_driver
     268Clock_initialize(rtems_device_major_number major,
    269269                 rtems_device_minor_number minor,
    270270                 void *pargp)
    271271{
    272272    Install_clock( Clock_isr );
    273  
     273
    274274    /*
    275275     * make major/minor avail to others such as shared memory driver
     
    277277    rtems_clock_major = major;
    278278    rtems_clock_minor = minor;
    279  
     279
    280280    return RTEMS_SUCCESSFUL;
    281281}
     
    292292 *     RTEMS_SUCCESSFUL
    293293 */
    294 rtems_device_driver 
     294rtems_device_driver
    295295Clock_control(rtems_device_major_number major,
    296296              rtems_device_minor_number minor,
     
    299299  uint32_t   isrlevel;
    300300  rtems_libio_ioctl_args_t *args = pargp;
    301  
     301
    302302  if (args != 0)
    303303    {
     
    306306       * to do this, it will just be this simple...
    307307       */
    308      
     308
    309309      if (args->command == rtems_build_name('I', 'S', 'R', ' '))
    310310        {
     
    316316          rtems_interrupt_disable( isrlevel );
    317317          rtems_interrupt_catch( args->buffer, CLOCK_VECTOR, &ignored );
    318          
     318
    319319          rtems_interrupt_enable( isrlevel );
    320320        }
  • c/src/lib/libcpu/sh/sh7750/include/rtems/score/iosh7750.h

    raed742c r3906b3ea  
    88 *           Bernd Becker (becker@faw.uni-ulm.de)
    99 *
    10  *  Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which 
     10 *  Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which
    1111 *  contained no copyright notice.
    1212 *
     
    1616 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    1717 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
    18  * 
     18 *
    1919 *
    2020 *  COPYRIGHT (c) 1998.
     
    2525 *  http://www.rtems.com/license/LICENSE.
    2626 *
    27  *      Modified to reflect on-chip registers for sh7045 processor, based on 
    28  *      "Register.h" distributed with Hitachi's EVB7045F tutorials, and which 
     27 *      Modified to reflect on-chip registers for sh7045 processor, based on
     28 *      "Register.h" distributed with Hitachi's EVB7045F tutorials, and which
    2929 *  contained no copyright notice:
    3030 *      John M. Mills (jmills@tga.com)
  • c/src/lib/libcpu/sh/sh7750/include/rtems/score/ipl.h

    raed742c r3906b3ea  
    2828  { ipl_console_initialize, ipl_console_open, ipl_console_close, \
    2929    ipl_console_read, ipl_console_write, ipl_console_control }
    30    
    31    
     30
     31
    3232#define NULL_SUCCESSFUL RTEMS_SUCCESSFUL
    3333
  • c/src/lib/libcpu/sh/sh7750/include/rtems/score/ispsh7750.h

    raed742c r3906b3ea  
    1515 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    1616 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
    17  * 
     17 *
    1818 *
    1919 *  COPYRIGHT (c) 1998.
     
    2929 *  100 Pinnacle Way, Suite 140
    3030 *  Norcross, GA 30071 U.S.A.
    31  * 
     31 *
    3232 *
    3333 *  This modified file may be copied and distributed in accordance
  • c/src/lib/libcpu/sh/sh7750/include/rtems/score/sh4_regs.h

    raed742c r3906b3ea  
    99 * found in the file LICENSE in this distribution or at
    1010 *  http://www.rtems.com/license/LICENSE.
    11  * 
     11 *
    1212 * @(#) $Id$
    1313 */
     
    2121#define SH4_SR_BL          0x10000000 /* Exeption/interrupt masking bit */
    2222#define SH4_SR_FD          0x00008000 /* FPU disable bit */
    23 #define SH4_SR_M           0x00000200 /* For signed division: 
     23#define SH4_SR_M           0x00000200 /* For signed division:
    2424                                         divisor (module) is negative */
    25 #define SH4_SR_Q           0x00000100 /* For signed division: 
     25#define SH4_SR_Q           0x00000100 /* For signed division:
    2626                                         dividend (and quotient) is negative */
    2727#define SH4_SR_IMASK       0x000000f0 /* Interrupt mask level */
    2828#define SH4_SR_IMASK_S     4
    2929#define SH4_SR_S           0x00000002 /* Saturation for MAC instruction:
    30                                          if set, data in MACH/L register 
     30                                         if set, data in MACH/L register
    3131                                         is restricted to 48/32 bits
    3232                                         for MAC.W/L instructions */
     
    3737#define SH4_FPSCR_FR       0x00200000 /* FPU register bank specifier */
    3838#define SH4_FPSCR_SZ       0x00100000 /* FMOV 64-bit transfer mode */
    39 #define SH4_FPSCR_PR       0x00080000 /* Double-percision floating-point 
     39#define SH4_FPSCR_PR       0x00080000 /* Double-percision floating-point
    4040                                         operations flag */
    4141                                      /* SH4_FPSCR_SZ & SH4_FPSCR_PR != 1 */
  • c/src/lib/libcpu/sh/sh7750/include/rtems/score/sh7750_regs.h

    raed742c r3906b3ea  
    1313 * found in the file LICENSE in this distribution or at
    1414 *  http://www.rtems.com/license/LICENSE.
    15  * 
     15 *
    1616 * @(#) $Id$
    1717 */
     
    2020#define __SH7750_REGS_H__
    2121
    22 /* 
    23  * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address)  and 
     22/*
     23 * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address)  and
    2424 * in 0x1f000000 - 0x1fffffff (area 7 address)
    2525 */
    26 #define SH7750_P4_BASE       0xff000000 /* Accessable only in 
     26#define SH7750_P4_BASE       0xff000000 /* Accessable only in
    2727                                           priveleged mode */
    2828#define SH7750_A7_BASE       0x1f000000 /* Accessable only using TLB */
     
    3131#define SH7750_A7_REG32(ofs) (SH7750_A7_BASE + (ofs))
    3232
    33 /* 
    34  * MMU Registers 
     33/*
     34 * MMU Registers
    3535 */
    3636
     
    6262#define SH7750_PTEL_PR_ROPU   0x00000040 /*   read-only in priv or user mode*/
    6363#define SH7750_PTEL_PR_RWPU   0x00000060 /*   read-write in priv or user mode*/
    64 #define SH7750_PTEL_C         0x00000008 /* Cacheability 
     64#define SH7750_PTEL_C         0x00000008 /* Cacheability
    6565                                            (0 - page not cacheable) */
    66 #define SH7750_PTEL_D         0x00000004 /* Dirty bit (1 - write has been 
     66#define SH7750_PTEL_D         0x00000004 /* Dirty bit (1 - write has been
    6767                                            performed to a page) */
    6868#define SH7750_PTEL_SH        0x00000002 /* Share Status bit (1 - page are
     
    131131
    132132#define SH7750_CCR_IIX      0x00008000 /* IC index enable bit */
    133 #define SH7750_CCR_ICI      0x00000800 /* IC invalidation bit: 
     133#define SH7750_CCR_ICI      0x00000800 /* IC invalidation bit:
    134134                                          set it to clear IC */
    135135#define SH7750_CCR_ICE      0x00000100 /* IC enable bit */
    136136#define SH7750_CCR_OIX      0x00000080 /* OC index enable bit */
    137 #define SH7750_CCR_ORA      0x00000020 /* OC RAM enable bit 
    138                                           if you set OCE = 0, 
     137#define SH7750_CCR_ORA      0x00000020 /* OC RAM enable bit
     138                                          if you set OCE = 0,
    139139                                          you should set ORA = 0 */
    140140#define SH7750_CCR_OCI      0x00000008 /* OC invalidation bit */
     
    167167
    168168/* Exeption event register - EXPEVT */
    169 #define SH7750_EXPEVT_REGOFS  0x000024 
     169#define SH7750_EXPEVT_REGOFS  0x000024
    170170#define SH7750_EXPEVT         SH7750_P4_REG32(SH7750_EXPEVT_REGOFS)
    171171#define SH7750_EXPEVT_A7      SH7750_A7_REG32(SH7750_EXPEVT_REGOFS)
     
    175175
    176176/* Interrupt event register */
    177 #define SH7750_INTEVT_REGOFS  0x000028 
     177#define SH7750_INTEVT_REGOFS  0x000028
    178178#define SH7750_INTEVT         SH7750_P4_REG32(SH7750_INTEVT_REGOFS)
    179179#define SH7750_INTEVT_A7      SH7750_A7_REG32(SH7750_INTEVT_REGOFS)
     
    255255/* Peripheral Module Interrupts - Memory Refresh Unit (REF) */
    256256#define SH7750_EVT_REF_RCMI            0x580 /* Compare-match Interrupt */
    257 #define SH7750_EVT_REF_ROVI            0x5A0 /* Refresh Counter Overflow 
     257#define SH7750_EVT_REF_ROVI            0x5A0 /* Refresh Counter Overflow
    258258                                                interrupt */
    259259
     
    293293                                         0 - normal state
    294294                                         1 - high-impendance state */
    295                                
     295
    296296#define SH7750_STBCR_PPU      0x20 /* Peripheral module pins pull-up controls*/
    297297#define SH7750_STBCR_MSTP4    0x10 /* Stopping the clock supply to DMAC */
     
    332332#define SH7750_FRQCR_A7       SH7750_A7_REG32(SH7750_FRQCR_REGOFS)
    333333
    334 #define SH7750_FRQCR_CKOEN    0x0800 /* Clock Output Enable 
     334#define SH7750_FRQCR_CKOEN    0x0800 /* Clock Output Enable
    335335                                          0 - CKIO pin goes to HiZ/pullup
    336336                                          1 - Clock is output from CKIO */
     
    365365 * Watchdog Timer (WDT)
    366366 */
    367  
     367
    368368/* Watchdog Timer Counter register - WTCNT */
    369369#define SH7750_WTCNT_REGOFS   0xC00008  /* offset */
     
    622622#define SH7750_BCR1_ENDIAN    0x80000000 /* Endianness (1 - little endian) */
    623623#define SH7750_BCR1_MASTER    0x40000000 /* Master/Slave mode (1-master) */
    624 #define SH7750_BCR1_A0MPX     0x20000000 /* Area 0 Memory Type (0-SRAM,1-MPX)*/ 
     624#define SH7750_BCR1_A0MPX     0x20000000 /* Area 0 Memory Type (0-SRAM,1-MPX)*/
    625625#define SH7750_BCR1_IPUP      0x02000000 /* Input Pin Pull-up Control:
    626626                                              0 - pull-up resistor is on for
     
    644644                                              0 - External requests are  not
    645645                                                  accepted
    646                                               1 - External requests are 
     646                                              1 - External requests are
    647647                                                  accepted */
    648648#define SH7750_BCR1_PSHR      0x00040000 /* Partial Sharing Bit:
     
    878878#define SH7750_MCR_TCAS_2     0x00800000 /*    2 */
    879879
    880 #define SH7750_MCR_TPC        0x00380000 /* DRAM: RAS Precharge Period 
     880#define SH7750_MCR_TPC        0x00380000 /* DRAM: RAS Precharge Period
    881881                                            SDRAM: minimum number of cycles
    882882                                            until the next bank active cmd
     
    885885#define SH7750_MCR_TPC_SDRAM_1 0x00000000 /* 1 cycle */
    886886#define SH7750_MCR_TPC_SDRAM_2 0x00080000 /* 2 cycles */
    887 #define SH7750_MCR_TPC_SDRAM_3 0x00100000 /* 3 cycles */ 
     887#define SH7750_MCR_TPC_SDRAM_3 0x00100000 /* 3 cycles */
    888888#define SH7750_MCR_TPC_SDRAM_4 0x00180000 /* 4 cycles */
    889889#define SH7750_MCR_TPC_SDRAM_5 0x00200000 /* 5 cycles */
     
    11491149
    11501150#define SH7750_CHCR_DTC       0x01000000 /* Destination Address Wait Control
    1151                                             Select, specifies CS5 or CS6 
     1151                                            Select, specifies CS5 or CS6
    11521152                                            space wait control for PCMCIA
    11531153                                            access */
     
    11871187                                                 Space -> External Device) */
    11881188#define SH7750_CHCR_RS_ER_SA_ED_TO_EA   0x300 /* External Request, Single
    1189                                                  Address Mode, (External 
    1190                                                  Device -> External Addr 
     1189                                                 Address Mode, (External
     1190                                                 Device -> External Addr
    11911191                                                 Space)*/
    11921192#define SH7750_CHCR_RS_AR_EA_TO_EA      0x400 /* Auto-Request (External Addr
     
    11961196                                                 Space -> On-chip Peripheral
    11971197                                                 Module) */
    1198 #define SH7750_CHCR_RS_AR_OCP_TO_EA     0x600 /* Auto-Request (On-chip 
     1198#define SH7750_CHCR_RS_AR_OCP_TO_EA     0x600 /* Auto-Request (On-chip
    11991199                                                 Peripheral Module ->
    12001200                                                 External Addr Space */
     
    12071207#define SH7750_CHCR_RS_SCIFTX_EA_TO_SC  0xA00 /* SCIF Transmit-Data-Empty intr
    12081208                                                 transfer request (external
    1209                                                  address space -> SCFTDR1) */ 
     1209                                                 address space -> SCFTDR1) */
    12101210#define SH7750_CHCR_RS_SCIFRX_SC_TO_EA  0xB00 /* SCIF Receive-Data-Full intr
    12111211                                                 transfer request (SCFRDR2 ->
     
    13421342#define SH7750_SCSSR1_TDRE    0x80 /* Transmit Data Register Empty */
    13431343#define SH7750_SCSSR1_RDRF    0x40 /* Receive Data Register Full */
    1344 #define SH7750_SCSSR1_ORER    0x20 /* Overrun Error */ 
     1344#define SH7750_SCSSR1_ORER    0x20 /* Overrun Error */
    13451345#define SH7750_SCSSR1_FER     0x10 /* Framing Error */
    13461346#define SH7750_SCSSR1_PER     0x08 /* Parity Error */
     
    15701570
    15711571/* Interrupt Priority Register B - IPRB (half) */
    1572 #define SH7750_IPRB_REGOFS    0xD00008 /* offset */ 
     1572#define SH7750_IPRB_REGOFS    0xD00008 /* offset */
    15731573#define SH7750_IPRB           SH7750_P4_REG32(SH7750_IPRB_REGOFS)
    15741574#define SH7750_IPRB_A7        SH7750_A7_REG32(SH7750_IPRB_REGOFS)
     
    15971597
    15981598
    1599 /* 
     1599/*
    16001600 * User Break Controller registers
    16011601 */
  • c/src/lib/libcpu/sh/sh7750/sci/console.c

    raed742c r3906b3ea  
    158158            minor+1,                /* channel */
    159159            (console_mode == CONSOLE_MODE_INT));
    160    
     160
    161161    if (sc == RTEMS_SUCCESSFUL)
    162162        sc = sh4uart_reset(&sh4_uarts[minor]);
    163    
     163
    164164    return sc;
    165165}
     
    194194console_reserve_resources(rtems_configuration_table *configuration)
    195195{
    196     if ((console_mode != CONSOLE_MODE_RAW) && 
     196    if ((console_mode != CONSOLE_MODE_RAW) &&
    197197            (console_mode != CONSOLE_MODE_IPL))
    198198        rtems_termios_reserve_resources (configuration, 2);
     
    234234                    (console_mode != CONSOLE_MODE_IPL))
    235235        rtems_termios_initialize ();
    236    
     236
    237237    /*
    238238     * Register the devices
     
    266266
    267267        return sc;
    268     }                       
     268    }
    269269
    270270    return RTEMS_SUCCESSFUL;
     
    349349    else
    350350        return RTEMS_SUCCESSFUL;
    351 }   
     351}
    352352
    353353/* console_read --
     
    426426            int count = argp->count;
    427427            int i;
    428            
     428
    429429            for (i = 0; i < count; i++)
    430430            {
  • c/src/lib/libcpu/sh/sh7750/sci/sh4uart.c

    raed742c r3906b3ea  
    7373 * sh4uart_get_Pph --
    7474 *    Get current peripheral module clock.
    75  *   
     75 *
    7676 * PARAMETERS: none;
    77  *    Cpu clock is get from CPU_CLOCK_RATE_HZ marco 
     77 *    Cpu clock is get from CPU_CLOCK_RATE_HZ marco
    7878 *    (defined in bspopts.h, included from bsp.h)
    7979 *
     
    8181 *    peripheral module clock in Hz.
    8282 */
    83 uint32_t 
     83uint32_t
    8484sh4uart_get_Pph(void)
    8585{
     
    115115            break;
    116116    }
    117    
     117
    118118    switch (frqcr & SH7750_FRQCR_PFC)
    119119    {
     
    203203    if (n >= 4)
    204204        sh4uart_set_baudrate(uart, B9600);
    205    
     205
    206206    SCSMR(uart->chn) &= ~SH7750_SCSMR_CKS;
    207207    SCSMR(uart->chn) |= n << SH7750_SCSMR_CKS_S;
     
    241241
    242242    if (chn == SH4_SCIF)
    243         SCFCR2 = SH7750_SCFCR2_TFRST | SH7750_SCFCR2_RFRST | 
     243        SCFCR2 = SH7750_SCFCR2_TFRST | SH7750_SCFCR2_RFRST |
    244244                SH7750_SCFCR2_RTRG_1 | SH7750_SCFCR2_TTRG_4;
    245245
     
    260260            IPRB = ipr;
    261261
    262             rc = rtems_interrupt_catch(sh4uart1_interrupt_transmit, 
    263                     SH7750_EVT_TO_NUM(SH7750_EVT_SCI_TXI), 
     262            rc = rtems_interrupt_catch(sh4uart1_interrupt_transmit,
     263                    SH7750_EVT_TO_NUM(SH7750_EVT_SCI_TXI),
    264264                    &uart->old_handler_transmit);
    265265            if (rc != RTEMS_SUCCESSFUL)
    266266                return rc;
    267             rc = rtems_interrupt_catch(sh4uart1_interrupt_receive, 
    268                     SH7750_EVT_TO_NUM(SH7750_EVT_SCI_RXI), 
     267            rc = rtems_interrupt_catch(sh4uart1_interrupt_receive,
     268                    SH7750_EVT_TO_NUM(SH7750_EVT_SCI_RXI),
    269269                    &uart->old_handler_receive);
    270270            if (rc != RTEMS_SUCCESSFUL)
     
    278278            IPRC = ipr;
    279279
    280             rc = rtems_interrupt_catch(sh4uart2_interrupt_transmit, 
    281                     SH7750_EVT_TO_NUM(SH7750_EVT_SCIF_TXI), 
     280            rc = rtems_interrupt_catch(sh4uart2_interrupt_transmit,
     281                    SH7750_EVT_TO_NUM(SH7750_EVT_SCIF_TXI),
    282282                    &uart->old_handler_transmit);
    283283            if (rc != RTEMS_SUCCESSFUL)
    284284                return rc;
    285             rc = rtems_interrupt_catch(sh4uart2_interrupt_receive, 
    286                     SH7750_EVT_TO_NUM(SH7750_EVT_SCIF_RXI), 
     285            rc = rtems_interrupt_catch(sh4uart2_interrupt_receive,
     286                    SH7750_EVT_TO_NUM(SH7750_EVT_SCIF_RXI),
    287287                    &uart->old_handler_receive);
    288288            if (rc != RTEMS_SUCCESSFUL)
     
    296296                                           it is differ to termios default */
    297297
    298     SCSCR(chn) = SH7750_SCSCR_TE | SH7750_SCSCR_RE | 
    299             (chn == SH4_SCI ? 0x0 : SH7750_SCSCR2_REIE) | 
     298    SCSCR(chn) = SH7750_SCSCR_TE | SH7750_SCSCR_RE |
     299            (chn == SH4_SCI ? 0x0 : SH7750_SCSCR2_REIE) |
    300300            (int_driven ? (SH7750_SCSCR_RIE | SH7750_SCSCR_TIE) : 0x0);
    301                    
     301
    302302    return RTEMS_SUCCESSFUL;
    303303}
     
    325325    if (uart->int_driven)
    326326    {
    327         rc = rtems_interrupt_catch(uart->old_handler_transmit, 
    328                 uart->chn == SH4_SCI ? 
    329                         SH7750_EVT_SCI_TXI : SH7750_EVT_SCIF_TXI, 
     327        rc = rtems_interrupt_catch(uart->old_handler_transmit,
     328                uart->chn == SH4_SCI ?
     329                        SH7750_EVT_SCI_TXI : SH7750_EVT_SCIF_TXI,
    330330                NULL);
    331331        if (rc != RTEMS_SUCCESSFUL)
    332332            return rc;
    333         rc = rtems_interrupt_catch(uart->old_handler_receive, 
    334                 uart->chn == SH4_SCI ? 
    335                         SH7750_EVT_SCI_RXI : SH7750_EVT_SCIF_RXI, 
     333        rc = rtems_interrupt_catch(uart->old_handler_receive,
     334                uart->chn == SH4_SCI ?
     335                        SH7750_EVT_SCI_RXI : SH7750_EVT_SCIF_RXI,
    336336                NULL);
    337337        if (rc != RTEMS_SUCCESSFUL)
     
    360360    speed_t baud;
    361361    uint16_t   smr;
    362    
     362
    363363    smr = (uint16_t)(*(uint8_t*)SH7750_SCSMR(uart->chn));
    364364
     
    474474    if (chn == SH4_SCI)
    475475    {
    476         if ((SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER | 
     476        if ((SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER |
    477477                     SH7750_SCSSR1_ORER)) != 0)
    478478        {
     
    488488    {
    489489        if ((SCSSR2 & (SH7750_SCSSR2_ER | SH7750_SCSSR2_DR |
    490                      SH7750_SCSSR2_BRK)) != 0 || 
     490                     SH7750_SCSSR2_BRK)) != 0 ||
    491491                (SCLSR2 & SH7750_SCLSR2_ORER) != 0)
    492492        {
     
    561561            {
    562562                int i;
    563                 for (i = 0; 
    564                         i < 16 - TRANSMIT_TRIGGER_VALUE(SCFCR2 & 
    565                             SH7750_SCFCR2_TTRG); 
     563                for (i = 0;
     564                        i < 16 - TRANSMIT_TRIGGER_VALUE(SCFCR2 &
     565                            SH7750_SCFCR2_TTRG);
    566566                        i++)
    567567                {
     
    569569                    len--;
    570570                }
    571                 while ((SCSSR2 & SH7750_SCSSR2_TDFE) == 0 || 
     571                while ((SCSSR2 & SH7750_SCSSR2_TDFE) == 0 ||
    572572                        (SCSSR2 & SH7750_SCSSR2_TEND) == 0);
    573573                    SCSSR2 &= ~(SH7750_SCSSR1_TDRE | SH7750_SCSSR2_TEND);
     
    605605        {
    606606            /* Receive character and handle frame/parity errors */
    607             if ((SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER | 
     607            if ((SCSSR1 & (SH7750_SCSSR1_PER | SH7750_SCSSR1_FER |
    608608                            SH7750_SCSSR1_ORER)) != 0)
    609609            {
     
    662662        {
    663663            if ((SCSSR2 & (SH7750_SCSSR2_ER | SH7750_SCSSR2_DR |
    664                             SH7750_SCSSR2_BRK)) != 0 || 
     664                            SH7750_SCSSR2_BRK)) != 0 ||
    665665                    (SH7750_SCLSR2 & SH7750_SCLSR2_ORER) != 0)
    666666            {
     
    688688                        buf[bp++] = 0x00;   /* XXX -- SIGINT */
    689689                }
    690                    
     690
    691691                sh4uart_handle_error(uart);
    692692            }
     
    723723    if (uart->tx_buf != NULL && uart->tx_ptr < uart->tx_buf_len)
    724724    {
    725         while ((SCSSR1 & SH7750_SCSSR1_TDRE) != 0 && 
     725        while ((SCSSR1 & SH7750_SCSSR1_TDRE) != 0 &&
    726726                uart->tx_ptr < uart->tx_buf_len)
    727727        {
     
    765765            {
    766766                int i;
    767                 for (i = 0; 
    768                         i < 16 - TRANSMIT_TRIGGER_VALUE(SCFCR2 & 
    769                             SH7750_SCFCR2_TTRG); 
     767                for (i = 0;
     768                        i < 16 - TRANSMIT_TRIGGER_VALUE(SCFCR2 &
     769                            SH7750_SCFCR2_TTRG);
    770770                        i++)
    771771                    SCTDR2 = uart->tx_buf[uart->tx_ptr++];
     
    808808
    809809    rtems_interrupt_disable(level);
    810    
     810
    811811    uart->tx_buf = buf;
    812812    uart->tx_buf_len = len;
     
    933933{
    934934    int c;
    935     while (len > 0) 
     935    while (len > 0)
    936936    {
    937937        c = (len < 64 ? len : 64);
  • c/src/lib/libcpu/sh/sh7750/score/cpu_asm.c

    raed742c r3906b3ea  
    1414 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    1515 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
    16  * 
     16 *
    1717 *
    1818 *  COPYRIGHT (c) 1998.
     
    4949#endif
    5050
    51 register unsigned long  *stack_ptr asm("r15"); 
     51register unsigned long  *stack_ptr asm("r15");
    5252
    5353/*
     
    6969{
    7070#if SH_HAS_FPU
    71  
     71
    7272asm volatile("\n\
    7373    mov.l   @%0,r4    \n\
     
    9696    fmov    xd2,@-r4\n\
    9797    fmov    xd0,@-r4\n\
    98     " 
     98    "
    9999#endif
    100100   "lds     %4,fpscr\n\
    101101   "
    102     : 
    103     : "r"(fp_context_ptr), "r"(sizeof(Context_Control_fp)), 
     102    :
     103    : "r"(fp_context_ptr), "r"(sizeof(Context_Control_fp)),
    104104      "r"(SH4_FPSCR_SZ), "r"(SH4_FPSCR_PR | SH4_FPSCR_SZ), "r"(SH4_FPSCR_PR)
    105105    : "r4", "r0");
     
    155155    lds.l   @r4+,fpul\n\
    156156    lds.l   @r4+,fpscr\n\
    157     " : 
     157    " :
    158158    : "r"(fp_context_ptr), "r"(SH4_FPSCR_PR | SH4_FPSCR_SZ), "r"(SH4_FPSCR_SZ)
    159159    : "r4", "r0");
     
    183183
    184184/*
    185  * FIXME: This is an ugly hack, but we wanted to avoid recalculating 
     185 * FIXME: This is an ugly hack, but we wanted to avoid recalculating
    186186 *        the offset each time Context_Control is changed
    187187 */
     
    251251}
    252252
    253 /* 
     253/*
    254254 *  This routine provides the RTEMS interrupt management.
    255255 */
    256  
     256
    257257void __ISR_Handler( uint32_t   vector)
    258258{
     
    291291  if( _ISR_Nest_level == 0 )
    292292    /* restore old stack pointer */
    293     stack_ptr = _old_stack_ptr; 
     293    stack_ptr = _old_stack_ptr;
    294294#endif
    295295
  • c/src/lib/libcpu/sh/sh7750/score/ispsh7750.c

    raed742c r3906b3ea  
    1414 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    1515 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
    16  * 
     16 *
    1717 *
    1818 *  COPYRIGHT (c) 1998.
     
    118118     "offset100_k:\n"
    119119     "        .long  0x100\n"
    120      
     120
    121121     "        .org __vbr_base + 0x400\n"
    122122     "vbr_400:\n"
     
    156156     "    mov.l r6,@-r15   \n"
    157157     "    mov.l r7,@-r15   \n"
    158 #if 0     
     158#if 0
    159159     "    mov.l r8,@-r15   \n"
    160160     "    mov.l r9,@-r15   \n"
     
    185185     "    fmov  fr14,@-r15 \n"
    186186     "    fmov  fr15,@-r15 \n"
    187      
     187
    188188     "    sts.l pr,@-r15   \n"
    189189     "    sts.l mach,@-r15 \n"
     
    201201     "    shlr2 r4         \n"
    202202     "    shlr  r4         \n"
    203      
     203
    204204     "    mov.l _ISR_Table_k,r0\n"
    205205     "    mov.l @r0,r0     \n"
     
    248248     "    mov.l @r15+,r8   \n"
    249249#endif
    250      
     250
    251251     "    mov.l @r15+,r7   \n"
    252252     "    mov.l @r15+,r6   \n"
     
    299299     "    lds.l @r15+,fpscr\n"
    300300     "    mov.l @r15+,r14  \n"
    301      
     301
    302302     "    mov.l @r15+,r13  \n"
    303303     "    mov.l @r15+,r12  \n"
     
    306306     "    mov.l @r15+,r9   \n"
    307307     "    mov.l @r15+,r8   \n"
    308      
    309      
     308
     309
    310310     "    mov.l @r15+,r7   \n"
    311311     "    mov.l @r15+,r6   \n"
     
    330330
    331331 );
    332      
     332
    333333
    334334/************************************************
    335  * Dummy interrupt service procedure for 
     335 * Dummy interrupt service procedure for
    336336 * interrupts being not allowed --> Trap 2
    337337 ************************************************/
  • c/src/lib/libcpu/sh/sh7750/timer/timer.c

    raed742c r3906b3ea  
    6363 *     none
    6464 */
    65 void 
     65void
    6666Timer_initialize(void)
    6767{
     
    8282            cpudiv = 1;
    8383            break;
    84        
     84
    8585        case SH7750_FRQCR_IFCDIV2:
    8686            cpudiv = 2;
    8787            break;
    88            
     88
    8989        case SH7750_FRQCR_IFCDIV3:
    9090            cpudiv = 3;
    9191            break;
    92        
     92
    9393        case SH7750_FRQCR_IFCDIV4:
    9494            cpudiv = 4;
    9595            break;
    96        
     96
    9797        case SH7750_FRQCR_IFCDIV6:
    9898            cpudiv = 6;
    9999            break;
    100        
     100
    101101        case SH7750_FRQCR_IFCDIV8:
    102102            cpudiv = 8;
    103103            break;
    104        
     104
    105105        default:
    106106            rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED);
     
    113113            tidiv = 2 * TIMER_PRESCALER;
    114114            break;
    115            
     115
    116116        case SH7750_FRQCR_PFCDIV3:
    117117            tidiv = 3 * TIMER_PRESCALER;
    118118            break;
    119        
     119
    120120        case SH7750_FRQCR_PFCDIV4:
    121121            tidiv = 4 * TIMER_PRESCALER;
    122122            break;
    123        
     123
    124124        case SH7750_FRQCR_PFCDIV6:
    125125            tidiv = 6 * TIMER_PRESCALER;
    126126            break;
    127        
     127
    128128        case SH7750_FRQCR_PFCDIV8:
    129129            tidiv = 8 * TIMER_PRESCALER;
    130130            break;
    131        
     131
    132132        default:
    133133            rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED);
    134134    }
    135135
    136     microseconds_divider = 
    137         rtems_cpu_configuration_get_clicks_per_second() * cpudiv / 
     136    microseconds_divider =
     137        rtems_cpu_configuration_get_clicks_per_second() * cpudiv /
    138138        (tidiv * 1000000);
    139139    microseconds_per_int = 0xFFFFFFFF / microseconds_divider;
     
    154154    write32(0xFFFFFFFF, SH7750_TCOR1);
    155155    write32(0xFFFFFFFF, SH7750_TCNT1);
    156    
     156
    157157    /* Select timer mode */
    158158    write16(
     
    201201 *     number of microseconds since timer has been started
    202202 */
    203 int 
     203int
    204204Read_timer(void)
    205205{
     
    209209    rtems_interrupt_level level;
    210210    uint32_t   tcr;
    211    
     211
    212212
    213213    _CPU_ISR_Disable(level);
     
    216216    tcr = read32(SH7750_TCR1);
    217217    ints = Timer_interrupts;
    218    
     218
    219219    _CPU_ISR_Enable(level);
    220    
     220
    221221    /* Handle the case when timer overflowed but interrupt was not processed */
    222222    if ((clicks > 0xFF000000) && ((tcr & SH7750_TCR_UNF) != 0))
     
    229229    if ( Timer_driver_Find_average_overhead )
    230230        return total;          /* in microsecond units */
    231     else 
     231    else
    232232    {
    233233        if ( total < LEAST_VALID )
     
    250250 *     RTEMS_SUCCESSFUL
    251251 */
    252 rtems_status_code 
     252rtems_status_code
    253253Empty_function( void )
    254254{
     
    268268 *     none
    269269 */
    270 void 
     270void
    271271Set_find_average_overhead(rtems_boolean find_flag)
    272272{
     
    275275
    276276/* timerisr --
    277  *     Timer interrupt handler routine. This function invoked on timer 
     277 *     Timer interrupt handler routine. This function invoked on timer
    278278 *     underflow event; once per 2^32 clocks. It should reset the timer
    279279 *     event and increment timer interrupts counter.
    280280 */
    281 void 
     281void
    282282timerisr(void)
    283283{
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