Changeset 38ca736 in rtems
- Timestamp:
- 02/25/05 05:25:14 (19 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- 8ce50cb
- Parents:
- 6a184ff
- Location:
- c/src/lib/libcpu/mips
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libcpu/mips/ChangeLog
r6a184ff r38ca736 1 2005-02-24 Jay Monkman <jtm@lopingdog.com> 2 3 * au1x00/include/au1x00.h: Converted types to C99 types. 4 1 5 2005-02-24 Jay Monkman <jtm@lopingdog.com> 2 6 -
c/src/lib/libcpu/mips/au1x00/include/au1x00.h
r6a184ff r38ca736 210 210 #define MEM_1MS ((396000000/1000000) * 1000) 211 211 212 #define AU1X00_IC_CFG0RD(x) (*(volatile u nsigned32*)(x + 0x40))213 #define AU1X00_IC_CFG0SET(x) (*(volatile u nsigned32*)(x + 0x40))214 #define AU1X00_IC_CFG0CLR(x) (*(volatile u nsigned32*)(x + 0x44))215 #define AU1X00_IC_CFG1RD(x) (*(volatile u nsigned32*)(x + 0x48))216 #define AU1X00_IC_CFG1SET(x) (*(volatile u nsigned32*)(x + 0x48))217 #define AU1X00_IC_CFG1CLR(x) (*(volatile u nsigned32*)(x + 0x4c))218 #define AU1X00_IC_CFG2RD(x) (*(volatile u nsigned32*)(x + 0x50))219 #define AU1X00_IC_CFG2SET(x) (*(volatile u nsigned32*)(x + 0x50))220 #define AU1X00_IC_CFG2CLR(x) (*(volatile u nsigned32*)(x + 0x54))221 #define AU1X00_IC_REQ0INT(x) (*(volatile u nsigned32*)(x + 0x54))222 #define AU1X00_IC_SRCRD(x) (*(volatile u nsigned32*)(x + 0x58))223 #define AU1X00_IC_SRCSET(x) (*(volatile u nsigned32*)(x + 0x58))224 #define AU1X00_IC_SRCCLR(x) (*(volatile u nsigned32*)(x + 0x5c))225 #define AU1X00_IC_REQ1INT(x) (*(volatile u nsigned32*)(x + 0x5c))226 #define AU1X00_IC_ASSIGNRD(x) (*(volatile u nsigned32*)(x + 0x60))227 #define AU1X00_IC_ASSIGNSET(x) (*(volatile u nsigned32*)(x + 0x60))228 #define AU1X00_IC_ASSIGNCLR(x) (*(volatile u nsigned32*)(x + 0x64))229 #define AU1X00_IC_WAKERD(x) (*(volatile u nsigned32*)(x + 0x68))230 #define AU1X00_IC_WAKESET(x) (*(volatile u nsigned32*)(x + 0x68))231 #define AU1X00_IC_WAKECLR(x) (*(volatile u nsigned32*)(x + 0x6c))232 #define AU1X00_IC_MASKRD(x) (*(volatile u nsigned32*)(x + 0x70))233 #define AU1X00_IC_MASKSET(x) (*(volatile u nsigned32*)(x + 0x70))234 #define AU1X00_IC_MASKCLR(x) (*(volatile u nsigned32*)(x + 0x74))235 #define AU1X00_IC_RISINGRD(x) (*(volatile u nsigned32*)(x + 0x78))236 #define AU1X00_IC_RISINGCLR(x) (*(volatile u nsigned32*)(x + 0x78))237 #define AU1X00_IC_FALLINGRD(x) (*(volatile u nsigned32*)(x + 0x7c))238 #define AU1X00_IC_FALLINGCLR(x) (*(volatile u nsigned32*)(x + 0x7c))239 #define AU1X00_IC_TESTBIT(x) (*(volatile u nsigned32*)(x + 0x80))212 #define AU1X00_IC_CFG0RD(x) (*(volatile uint32_t*)(x + 0x40)) 213 #define AU1X00_IC_CFG0SET(x) (*(volatile uint32_t*)(x + 0x40)) 214 #define AU1X00_IC_CFG0CLR(x) (*(volatile uint32_t*)(x + 0x44)) 215 #define AU1X00_IC_CFG1RD(x) (*(volatile uint32_t*)(x + 0x48)) 216 #define AU1X00_IC_CFG1SET(x) (*(volatile uint32_t*)(x + 0x48)) 217 #define AU1X00_IC_CFG1CLR(x) (*(volatile uint32_t*)(x + 0x4c)) 218 #define AU1X00_IC_CFG2RD(x) (*(volatile uint32_t*)(x + 0x50)) 219 #define AU1X00_IC_CFG2SET(x) (*(volatile uint32_t*)(x + 0x50)) 220 #define AU1X00_IC_CFG2CLR(x) (*(volatile uint32_t*)(x + 0x54)) 221 #define AU1X00_IC_REQ0INT(x) (*(volatile uint32_t*)(x + 0x54)) 222 #define AU1X00_IC_SRCRD(x) (*(volatile uint32_t*)(x + 0x58)) 223 #define AU1X00_IC_SRCSET(x) (*(volatile uint32_t*)(x + 0x58)) 224 #define AU1X00_IC_SRCCLR(x) (*(volatile uint32_t*)(x + 0x5c)) 225 #define AU1X00_IC_REQ1INT(x) (*(volatile uint32_t*)(x + 0x5c)) 226 #define AU1X00_IC_ASSIGNRD(x) (*(volatile uint32_t*)(x + 0x60)) 227 #define AU1X00_IC_ASSIGNSET(x) (*(volatile uint32_t*)(x + 0x60)) 228 #define AU1X00_IC_ASSIGNCLR(x) (*(volatile uint32_t*)(x + 0x64)) 229 #define AU1X00_IC_WAKERD(x) (*(volatile uint32_t*)(x + 0x68)) 230 #define AU1X00_IC_WAKESET(x) (*(volatile uint32_t*)(x + 0x68)) 231 #define AU1X00_IC_WAKECLR(x) (*(volatile uint32_t*)(x + 0x6c)) 232 #define AU1X00_IC_MASKRD(x) (*(volatile uint32_t*)(x + 0x70)) 233 #define AU1X00_IC_MASKSET(x) (*(volatile uint32_t*)(x + 0x70)) 234 #define AU1X00_IC_MASKCLR(x) (*(volatile uint32_t*)(x + 0x74)) 235 #define AU1X00_IC_RISINGRD(x) (*(volatile uint32_t*)(x + 0x78)) 236 #define AU1X00_IC_RISINGCLR(x) (*(volatile uint32_t*)(x + 0x78)) 237 #define AU1X00_IC_FALLINGRD(x) (*(volatile uint32_t*)(x + 0x7c)) 238 #define AU1X00_IC_FALLINGCLR(x) (*(volatile uint32_t*)(x + 0x7c)) 239 #define AU1X00_IC_TESTBIT(x) (*(volatile uint32_t*)(x + 0x80)) 240 240 #define AU1X00_IC_IRQ_MAC0 (bit(28)) 241 241 #define AU1X00_IC_IRQ_MAC1 (bit(29)) … … 246 246 247 247 248 #define AU1X00_SYS_TOYTRIM(x) (*(volatile u nsigned32*)(x + 0x00))249 #define AU1X00_SYS_TOYWRITE(x) (*(volatile u nsigned32*)(x + 0x04))250 #define AU1X00_SYS_TOYMATCH0(x) (*(volatile u nsigned32*)(x + 0x08))251 #define AU1X00_SYS_TOYMATCH1(x) (*(volatile u nsigned32*)(x + 0x0c))252 #define AU1X00_SYS_TOYMATCH2(x) (*(volatile u nsigned32*)(x + 0x10))253 #define AU1X00_SYS_CNTCTRL(x) (*(volatile u nsigned32*)(x + 0x14))254 #define AU1X00_SYS_SCRATCH0(x) (*(volatile u nsigned32*)(x + 0x18))255 #define AU1X00_SYS_SCRATCH1(x) (*(volatile u nsigned32*)(x + 0x1c))256 #define AU1X00_SYS_WAKEMSK(x) (*(volatile u nsigned32*)(x + 0x34))257 #define AU1X00_SYS_ENDIAN(x) (*(volatile u nsigned32*)(x + 0x38))258 #define AU1X00_SYS_POWERCTRL(x) (*(volatile u nsigned32*)(x + 0x3c))259 #define AU1X00_SYS_TOYREAD(x) (*(volatile u nsigned32*)(x + 0x40))260 #define AU1X00_SYS_RTCTRIM(x) (*(volatile u nsigned32*)(x + 0x44))261 #define AU1X00_SYS_RTCWRITE(x) (*(volatile u nsigned32*)(x + 0x48))262 #define AU1X00_SYS_RTCMATCH0(x) (*(volatile u nsigned32*)(x + 0x4c))263 #define AU1X00_SYS_RTCMATCH1(x) (*(volatile u nsigned32*)(x + 0x50))264 #define AU1X00_SYS_RTCMATCH2(x) (*(volatile u nsigned32*)(x + 0x54))265 #define AU1X00_SYS_RTCREAD(x) (*(volatile u nsigned32*)(x + 0x58))266 #define AU1X00_SYS_WAKESRC(x) (*(volatile u nsigned32*)(x + 0x5c))267 #define AU1X00_SYS_SLPPWR(x) (*(volatile u nsigned32*)(x + 0x78))268 #define AU1X00_SYS_SLEEP(x) (*(volatile u nsigned32*)(x + 0x7c))248 #define AU1X00_SYS_TOYTRIM(x) (*(volatile uint32_t*)(x + 0x00)) 249 #define AU1X00_SYS_TOYWRITE(x) (*(volatile uint32_t*)(x + 0x04)) 250 #define AU1X00_SYS_TOYMATCH0(x) (*(volatile uint32_t*)(x + 0x08)) 251 #define AU1X00_SYS_TOYMATCH1(x) (*(volatile uint32_t*)(x + 0x0c)) 252 #define AU1X00_SYS_TOYMATCH2(x) (*(volatile uint32_t*)(x + 0x10)) 253 #define AU1X00_SYS_CNTCTRL(x) (*(volatile uint32_t*)(x + 0x14)) 254 #define AU1X00_SYS_SCRATCH0(x) (*(volatile uint32_t*)(x + 0x18)) 255 #define AU1X00_SYS_SCRATCH1(x) (*(volatile uint32_t*)(x + 0x1c)) 256 #define AU1X00_SYS_WAKEMSK(x) (*(volatile uint32_t*)(x + 0x34)) 257 #define AU1X00_SYS_ENDIAN(x) (*(volatile uint32_t*)(x + 0x38)) 258 #define AU1X00_SYS_POWERCTRL(x) (*(volatile uint32_t*)(x + 0x3c)) 259 #define AU1X00_SYS_TOYREAD(x) (*(volatile uint32_t*)(x + 0x40)) 260 #define AU1X00_SYS_RTCTRIM(x) (*(volatile uint32_t*)(x + 0x44)) 261 #define AU1X00_SYS_RTCWRITE(x) (*(volatile uint32_t*)(x + 0x48)) 262 #define AU1X00_SYS_RTCMATCH0(x) (*(volatile uint32_t*)(x + 0x4c)) 263 #define AU1X00_SYS_RTCMATCH1(x) (*(volatile uint32_t*)(x + 0x50)) 264 #define AU1X00_SYS_RTCMATCH2(x) (*(volatile uint32_t*)(x + 0x54)) 265 #define AU1X00_SYS_RTCREAD(x) (*(volatile uint32_t*)(x + 0x58)) 266 #define AU1X00_SYS_WAKESRC(x) (*(volatile uint32_t*)(x + 0x5c)) 267 #define AU1X00_SYS_SLPPWR(x) (*(volatile uint32_t*)(x + 0x78)) 268 #define AU1X00_SYS_SLEEP(x) (*(volatile uint32_t*)(x + 0x7c)) 269 269 270 270 #define AU1X00_SYS_CNTCTRL_ERS (bit(23)) … … 289 289 #define AU1X00_SYS_WAKEMSK_M20 (bit(8)) 290 290 291 #define AU1X00_MAC_CONTROL(x) (*(volatile u nsigned32*)(x + 0x00))292 #define AU1X00_MAC_ADDRHIGH(x) (*(volatile u nsigned32*)(x + 0x04))293 #define AU1X00_MAC_ADDRLOW(x) (*(volatile u nsigned32*)(x + 0x08))294 #define AU1X00_MAC_HASHHIGH(x) (*(volatile u nsigned32*)(x + 0x0c))295 #define AU1X00_MAC_HASHLOW(x) (*(volatile u nsigned32*)(x + 0x10))296 #define AU1X00_MAC_MIICTRL(x) (*(volatile u nsigned32*)(x + 0x14))297 #define AU1X00_MAC_MIIDATA(x) (*(volatile u nsigned32*)(x + 0x18))298 #define AU1X00_MAC_FLOWCTRL(x) (*(volatile u nsigned32*)(x + 0x1c))299 #define AU1X00_MAC_VLAN1(x) (*(volatile u nsigned32*)(x + 0x20))300 #define AU1X00_MAC_VLAN2(x) (*(volatile u nsigned32*)(x + 0x24))301 #define AU1X00_MAC_EN0 (*(volatile u nsigned32*)(AU1X00_MACEN_ADDR + 0x0))302 #define AU1X00_MAC_EN1 (*(volatile u nsigned32*)(AU1X00_MACEN_ADDR + 0x4))303 #define AU1X00_MAC_DMA_TX0_ADDR(x) (*(volatile u nsigned32*)(x + 0x000))304 #define AU1X00_MAC_DMA_TX1_ADDR(x) (*(volatile u nsigned32*)(x + 0x010))305 #define AU1X00_MAC_DMA_TX2_ADDR(x) (*(volatile u nsigned32*)(x + 0x020))306 #define AU1X00_MAC_DMA_TX3_ADDR(x) (*(volatile u nsigned32*)(x + 0x030))307 #define AU1X00_MAC_DMA_RX0_ADDR(x) (*(volatile u nsigned32*)(x + 0x100))308 #define AU1X00_MAC_DMA_RX 0_ADDR(x) (*(volatile unsigned32*)(x + 0x110))309 #define AU1X00_MAC_DMA_RX 0_ADDR(x) (*(volatile unsigned32*)(x + 0x120))310 #define AU1X00_MAC_DMA_RX 0_ADDR(x) (*(volatile unsigned32*)(x + 0x130))291 #define AU1X00_MAC_CONTROL(x) (*(volatile uint32_t*)(x + 0x00)) 292 #define AU1X00_MAC_ADDRHIGH(x) (*(volatile uint32_t*)(x + 0x04)) 293 #define AU1X00_MAC_ADDRLOW(x) (*(volatile uint32_t*)(x + 0x08)) 294 #define AU1X00_MAC_HASHHIGH(x) (*(volatile uint32_t*)(x + 0x0c)) 295 #define AU1X00_MAC_HASHLOW(x) (*(volatile uint32_t*)(x + 0x10)) 296 #define AU1X00_MAC_MIICTRL(x) (*(volatile uint32_t*)(x + 0x14)) 297 #define AU1X00_MAC_MIIDATA(x) (*(volatile uint32_t*)(x + 0x18)) 298 #define AU1X00_MAC_FLOWCTRL(x) (*(volatile uint32_t*)(x + 0x1c)) 299 #define AU1X00_MAC_VLAN1(x) (*(volatile uint32_t*)(x + 0x20)) 300 #define AU1X00_MAC_VLAN2(x) (*(volatile uint32_t*)(x + 0x24)) 301 #define AU1X00_MAC_EN0 (*(volatile uint32_t*)(AU1X00_MACEN_ADDR + 0x0)) 302 #define AU1X00_MAC_EN1 (*(volatile uint32_t*)(AU1X00_MACEN_ADDR + 0x4)) 303 #define AU1X00_MAC_DMA_TX0_ADDR(x) (*(volatile uint32_t*)(x + 0x000)) 304 #define AU1X00_MAC_DMA_TX1_ADDR(x) (*(volatile uint32_t*)(x + 0x010)) 305 #define AU1X00_MAC_DMA_TX2_ADDR(x) (*(volatile uint32_t*)(x + 0x020)) 306 #define AU1X00_MAC_DMA_TX3_ADDR(x) (*(volatile uint32_t*)(x + 0x030)) 307 #define AU1X00_MAC_DMA_RX0_ADDR(x) (*(volatile uint32_t*)(x + 0x100)) 308 #define AU1X00_MAC_DMA_RX1_ADDR(x) (*(volatile uint32_t*)(x + 0x110)) 309 #define AU1X00_MAC_DMA_RX2_ADDR(x) (*(volatile uint32_t*)(x + 0x120)) 310 #define AU1X00_MAC_DMA_RX3_ADDR(x) (*(volatile uint32_t*)(x + 0x130)) 311 311 312 312 typedef struct { 313 volatile u nsigned32stat;314 volatile u nsigned32addr;315 u nsigned32_rsv0;316 u nsigned32_rsv1;313 volatile uint32_t stat; 314 volatile uint32_t addr; 315 uint32_t _rsv0; 316 uint32_t _rsv1; 317 317 } au1x00_macdma_rx_t; 318 318 319 319 320 320 typedef struct { 321 volatile u nsigned32stat;322 volatile u nsigned32addr;323 volatile u nsigned32len;324 u nsigned32_rsv0;321 volatile uint32_t stat; 322 volatile uint32_t addr; 323 volatile uint32_t len; 324 uint32_t _rsv0; 325 325 } au1x00_macdma_tx_t; 326 326 … … 412 412 413 413 typedef struct { 414 volatile u nsigned longrxdata;415 volatile u nsigned longtxdata;416 volatile u nsigned longinten;417 volatile u nsigned longintcause;418 volatile u nsigned longfifoctrl;419 volatile u nsigned longlinectrl;420 volatile u nsigned longmdmctrl;421 volatile u nsigned longlinestat;422 volatile u nsigned longmdmstat;423 volatile u nsigned longclkdiv;424 volatile u nsigned long_resv[54];425 volatile u nsigned longenable;414 volatile uint32_t rxdata; 415 volatile uint32_t txdata; 416 volatile uint32_t inten; 417 volatile uint32_t intcause; 418 volatile uint32_t fifoctrl; 419 volatile uint32_t linectrl; 420 volatile uint32_t mdmctrl; 421 volatile uint32_t linestat; 422 volatile uint32_t mdmstat; 423 volatile uint32_t clkdiv; 424 volatile uint32_t _resv[54]; 425 volatile uint32_t enable; 426 426 } au1x00_uart_t; 427 427
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