Index: c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog
===================================================================
--- c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog	(revision 9a72334444368218eadc63badcc1bb169447c804)
+++ c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog	(revision 384ba7563aaede68c38be361b9b5edd8bf4b3d0e)
@@ -1,2 +1,11 @@
+2005-10-06	Till Straumann <strauman@slac.stanford.edu>
+
+	PR 833/bsps
+	* irq/irq_asm.S: Currently, all (new exception) BSPs explicitely enable
+	the FPU across the user ISR but DONT save/restore the FPU context.
+	Any use of the FPU fron the user handler (e.g., due to GCC
+	optimizations) result in corruption. The fix results in an exception
+	in such cases (user ISR must explicitely save/enable/restore FPU).
+
 2005-09-12	Thomas Doerfler <Thomas.Doerfler@imd-systems.de>
 
Index: c/src/lib/libbsp/powerpc/mbx8xx/irq/irq_asm.S
===================================================================
--- c/src/lib/libbsp/powerpc/mbx8xx/irq/irq_asm.S	(revision 9a72334444368218eadc63badcc1bb169447c804)
+++ c/src/lib/libbsp/powerpc/mbx8xx/irq/irq_asm.S	(revision 384ba7563aaede68c38be361b9b5edd8bf4b3d0e)
@@ -13,4 +13,6 @@
  *    - store isr nesting level in _ISR_Nest_level rather than
  *      SPRG0 - RTEMS relies on that variable.
+ *  Till Straumann <strauman@slac.stanford.edu>, 2005/4:
+ *    - DONT enable FP across user ISR since fpregs are never saved!!
  *
  * $Id$
@@ -127,9 +129,5 @@
      * saved and restored (using FP instructions)
 	 */
-#if (PPC_HAS_FPU == 0)
 	ori     r3, r3, MSR_RI | MSR_IR | MSR_DR
-#else
-	ori     r3, r3, MSR_RI | MSR_IR | MSR_DR | MSR_FP
-#endif
 	mtmsr   r3
 	SYNC
@@ -338,4 +336,25 @@
 
 switch:
+#if ( PPC_HAS_FPU != 0 )
+#if ! defined( CPU_USE_DEFERRED_FP_SWITCH )
+#error missing include file???
+#endif
+	mfmsr  r4
+#if ( CPU_USE_DEFERRED_FP_SWITCH == TRUE )
+	/* if the executing thread has FP enabled propagate
+	 * this now so _Thread_Dispatch can save/restore the FPREGS
+	 * NOTE: it is *crucial* to disable the FPU across the
+	 *       user ISR [independent of using the 'deferred'
+	 *       strategy or not]. We don't save FP regs across
+	 *       the user ISR and hence we prefer an exception to
+	 *       be raised rather than experiencing corruption.
+	 */
+	lwz    r3, SRR1_FRAME_OFFSET(r1)
+	rlwimi r4, r3, 0, 18, 18 /* MSR_FP */
+#else
+	ori    r4, r4, MSR_FP
+#endif
+	mtmsr  r4
+#endif
 	bl	SYM (_Thread_Dispatch)
 
Index: c/src/lib/libbsp/powerpc/mpc8260ads/ChangeLog
===================================================================
--- c/src/lib/libbsp/powerpc/mpc8260ads/ChangeLog	(revision 9a72334444368218eadc63badcc1bb169447c804)
+++ c/src/lib/libbsp/powerpc/mpc8260ads/ChangeLog	(revision 384ba7563aaede68c38be361b9b5edd8bf4b3d0e)
@@ -1,2 +1,11 @@
+2005-10-06	Till Straumann <strauman@slac.stanford.edu>
+
+	PR 833/bsps
+	* irq/irq_asm.S: Currently, all (new exception) BSPs explicitely enable
+	the FPU across the user ISR but DONT save/restore the FPU context.
+	Any use of the FPU fron the user handler (e.g., due to GCC
+	optimizations) result in corruption. The fix results in an exception
+	in such cases (user ISR must explicitely save/enable/restore FPU).
+
 2005-09-19	Ralf Corsepius <ralf.corsepius@rtems.org>
 
Index: c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq_asm.S
===================================================================
--- c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq_asm.S	(revision 9a72334444368218eadc63badcc1bb169447c804)
+++ c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq_asm.S	(revision 384ba7563aaede68c38be361b9b5edd8bf4b3d0e)
@@ -12,4 +12,7 @@
  *  Modifications to store nesting level in global _ISR_Nest_level
  *  variable instead of SPRG0.  Andy Dachs <a.dachs@sstl.co.uk>
+ *
+ *  Till Straumann <strauman@slac.stanford.edu>, 2005/4:
+ *    - DONT enable FP across user ISR since fpregs are never saved!!
  *
  * $Id$
@@ -93,9 +96,5 @@
          * saved and restored (using FP instructions)
 	 */
-#if (PPC_HAS_FPU == 0)
 	ori     r3, r3, MSR_RI /*| MSR_IR | MSR_DR*/
-#else
-	ori     r3, r3, MSR_RI | /*MSR_IR | MSR_DR |*/ MSR_FP
-#endif
 	mtmsr   r3
 	SYNC
@@ -298,4 +297,25 @@
 
 switch:
+#if ( PPC_HAS_FPU != 0 )
+#if ! defined( CPU_USE_DEFERRED_FP_SWITCH )
+#error missing include file???
+#endif
+	mfmsr  r4
+#if ( CPU_USE_DEFERRED_FP_SWITCH == TRUE )
+	/* if the executing thread has FP enabled propagate
+	 * this now so _Thread_Dispatch can save/restore the FPREGS
+	 * NOTE: it is *crucial* to disable the FPU across the
+	 *       user ISR [independent of using the 'deferred'
+	 *       strategy or not]. We don't save FP regs across
+	 *       the user ISR and hence we prefer an exception to
+	 *       be raised rather than experiencing corruption.
+	 */
+	lwz    r3, SRR1_FRAME_OFFSET(r1)
+	rlwimi r4, r3, 0, 18, 18 /* MSR_FP */
+#else
+	ori    r4, r4, MSR_FP
+#endif
+	mtmsr  r4
+#endif
 	bl		SYM (_Thread_Dispatch)
 
Index: c/src/lib/libbsp/powerpc/shared/ChangeLog
===================================================================
--- c/src/lib/libbsp/powerpc/shared/ChangeLog	(revision 9a72334444368218eadc63badcc1bb169447c804)
+++ c/src/lib/libbsp/powerpc/shared/ChangeLog	(revision 384ba7563aaede68c38be361b9b5edd8bf4b3d0e)
@@ -1,2 +1,11 @@
+2005-10-06	Till Straumann <strauman@slac.stanford.edu>
+
+	PR 833/bsps
+	* irq/irq_asm.S: Currently, all (new exception) BSPs explicitely enable
+	the FPU across the user ISR but DONT save/restore the FPU context.
+	Any use of the FPU fron the user handler (e.g., due to GCC
+	optimizations) result in corruption. The fix results in an exception
+	in such cases (user ISR must explicitely save/enable/restore FPU).
+
 2005-09-16	richard.campbell@OARCorp.com
 
Index: c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S
===================================================================
--- c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S	(revision 9a72334444368218eadc63badcc1bb169447c804)
+++ c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S	(revision 384ba7563aaede68c38be361b9b5edd8bf4b3d0e)
@@ -13,4 +13,7 @@
  *    - store isr nesting level in _ISR_Nest_level rather than
  *      SPRG0 - RTEMS relies on that variable.
+ *  Till Straumann <strauman@slac.stanford.edu>, 2005/4:
+ *    - DONT enable FP across ISR since fpregs are not saved!!
+ *      FPU is used by Thread_Dispatch however...
  *
  * $Id$
@@ -95,9 +98,5 @@
      * saved and restored (using FP instructions)
 	 */
-#if (PPC_HAS_FPU == 0)
 	ori     r3, r3, MSR_RI | MSR_IR | MSR_DR
-#else
-	ori     r3, r3, MSR_RI | MSR_IR | MSR_DR | MSR_FP
-#endif
 	mtmsr   r3
 	SYNC
@@ -302,4 +301,25 @@
 
 switch:
+#if ( PPC_HAS_FPU != 0 )
+#if ! defined( CPU_USE_DEFERRED_FP_SWITCH )
+#error missing include file???
+#endif
+	mfmsr  r4
+#if ( CPU_USE_DEFERRED_FP_SWITCH == TRUE )
+	/* if the executing thread has FP enabled propagate
+	 * this now so _Thread_Dispatch can save/restore the FPREGS
+	 * NOTE: it is *crucial* to disable the FPU across the
+	 *       user ISR [independent of using the 'deferred'
+	 *       strategy or not]. We don't save FP regs across
+	 *       the user ISR and hence we prefer an exception to
+	 *       be raised rather than experiencing corruption.
+	 */
+	lwz    r3, SRR1_FRAME_OFFSET(r1)
+	rlwimi r4, r3, 0, 18, 18 /* MSR_FP */
+#else
+	ori    r4, r4, MSR_FP
+#endif
+	mtmsr  r4
+#endif
 	bl	SYM (_Thread_Dispatch)
 
