Changeset 3848df4d in rtems


Ignore:
Timestamp:
Aug 14, 2011, 7:38:14 AM (10 years ago)
Author:
Chris Johns <chrisj@…>
Branches:
4.11, 5, master
Children:
7b46d7a
Parents:
2a5880f1
Message:

2011-08-14 Chris Johns <chrisj@…>

  • rtems/score/cpu.h: Clear the vector table for simple vectored interrupts.
  • irq.c: Add support for using the IIC with the Altera HAL.
Location:
cpukit/score/cpu/nios2
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/nios2/ChangeLog

    r2a5880f1 r3848df4d  
     12011-08-14      Chris Johns <chrisj@rtems.org>
     2
     3        * rtems/score/cpu.h: Clear the vector table for simple vectored
     4        interrupts.
     5        * irq.c: Add support for using the IIC with the Altera HAL.
     6       
    172011-08-10      Sebastian Huber <sebastian.huber@embedded-brains.de>
    28
  • cpukit/score/cpu/nios2/irq.c

    r2a5880f1 r3848df4d  
    3535register unsigned long  *stack_ptr __asm__ ("sp");
    3636
     37RTEMS_INLINE_ROUTINE void
     38__Dipatch_interrupt_vector(uint32_t vector, proc_ptr pp)
     39{
     40  if ( _ISR_Vector_table[ vector] )
     41  {
     42    (*_ISR_Vector_table[ vector ])(vector, pp);
     43  };
     44}
     45
     46#if (RTEMS_NIOS_USE_ALT_HAL == TRUE)
     47
     48#include <bsp/alt/nios2.h>
     49
     50RTEMS_INLINE_ROUTINE void __IIC_Handler(void)
     51{
     52  uint32_t active;
     53  uint32_t mask;
     54  uint32_t vector;
     55
     56  /*
     57   * Obtain from the interrupt controller a bit list of pending interrupts,
     58   * and then process the highest priority interrupt. This process loops,
     59   * loading the active interrupt list on each pass until alt_irq_pending()
     60   * return zero.
     61   *
     62   * The maximum interrupt latency for the highest priority interrupt is
     63   * reduced by finding out which interrupts are pending as late as possible.
     64   * Consider the case where the high priority interupt is asserted during
     65   * the interrupt entry sequence for a lower priority interrupt to see why
     66   * this is the case.
     67   */
     68
     69  NIOS2_READ_IPENDING (active);
     70
     71  while (active)
     72  {
     73    vector = 0;
     74    mask = 1;
     75
     76    /*
     77     * Test each bit in turn looking for an active interrupt. Once one is
     78     * found, the interrupt handler asigned by a call to alt_irq_register() is
     79     * called to clear the interrupt condition.
     80     */
     81
     82    while (active)
     83    {
     84      if (active & mask)
     85      {
     86        __Dipatch_interrupt_vector(vector, NULL);
     87        active &= ~mask;
     88      }
     89      mask <<= 1;
     90      ++vector;
     91    };
     92
     93    NIOS2_READ_IPENDING (active);
     94  }
     95 
     96}
     97#endif
     98
     99#if (RTEMS_NIOS_USE_ALT_HAL == TRUE)
     100void __ISR_Handler(void)
     101#else
    37102void __ISR_Handler(uint32_t vector, CPU_Interrupt_frame *ifr)
     103#endif
    38104{
    39105  register uint32_t   level;
     
    53119  _Thread_Dispatch_increment_disable_level();
    54120
    55   if ( _ISR_Vector_table[ vector] )
    56   {
    57     (*_ISR_Vector_table[ vector ])(vector, ifr);
    58   };
    59 
     121#if (RTEMS_NIOS_USE_ALT_HAL == TRUE)
     122  __IIC_Handler();
     123#else
     124  __Dipatch_interrupt_vector(vector, ifr);
     125#endif
     126 
    60127  /* Make sure that interrupts are disabled again */
    61128  _CPU_ISR_Disable( level );
     
    88155  _CPU_Fatal_halt(0xECC0);
    89156}
    90 
    91 
  • cpukit/score/cpu/nios2/rtems/score/cpu.h

    r2a5880f1 r3848df4d  
    183183} CPU_Exception_frame;
    184184
     185#if (CPU_SIMPLE_VECTORED_INTERRUPTS == TRUE)
     186#define _CPU_Initialize_vectors() \
     187  memset(_ISR_Vector_table, 0, sizeof(ISR_Handler_entry) * ISR_NUMBER_OF_VECTORS)
     188#else
    185189#define _CPU_Initialize_vectors()
     190#endif
    186191
    187192#define _CPU_ISR_Disable( _isr_cookie ) \
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