Changeset 37885d5d in rtems


Ignore:
Timestamp:
10/10/14 17:23:08 (9 years ago)
Author:
Hesham ALMatary <heshamelmatary@…>
Branches:
4.11, 5, master
Children:
805ee4fa
Parents:
c7d8be5
git-author:
Hesham ALMatary <heshamelmatary@…> (10/10/14 17:23:08)
git-committer:
Joel Sherrill <joel.sherrill@…> (10/13/14 17:02:08)
Message:

libcpu/or1k: Fix warnings.

Location:
c/src/lib/libcpu/or1k/shared/cache
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/or1k/shared/cache/cache.c

    rc7d8be5 r37885d5d  
    7272  _ISR_Disable (level);
    7373
    74   _OR1K_mtspr(CPU_OR1K_SPR_DCBPR, d_addr);
     74  _OR1K_mtspr(CPU_OR1K_SPR_DCBPR, (uintptr_t) d_addr);
    7575
    7676  _ISR_Enable(level);
     
    8282  _ISR_Disable (level);
    8383
    84   _OR1K_mtspr(CPU_OR1K_SPR_DCBFR, d_addr);
     84  _OR1K_mtspr(CPU_OR1K_SPR_DCBFR, (uintptr_t) d_addr);
    8585
    8686  _ISR_Enable(level);
     
    9292  _ISR_Disable (level);
    9393
    94   _OR1K_mtspr(CPU_OR1K_SPR_DCBIR, d_addr);
     94  _OR1K_mtspr(CPU_OR1K_SPR_DCBIR, (uintptr_t) d_addr);
    9595
    9696  _ISR_Enable(level);
     
    102102  _ISR_Disable (level);
    103103
    104   _OR1K_mtspr(CPU_OR1K_SPR_DCBWR, d_addr);
     104  _OR1K_mtspr(CPU_OR1K_SPR_DCBWR, (uintptr_t) d_addr);
    105105
    106106  _ISR_Enable(level);
     
    112112  _ISR_Disable (level);
    113113
    114   _OR1K_mtspr(CPU_OR1K_SPR_DCBLR, d_addr);
     114  _OR1K_mtspr(CPU_OR1K_SPR_DCBLR, (uintptr_t) d_addr);
    115115
    116116  _ISR_Enable(level);
     
    123123  _ISR_Disable (level);
    124124
    125   _OR1K_mtspr(CPU_OR1K_SPR_ICBPR, d_addr);
     125  _OR1K_mtspr(CPU_OR1K_SPR_ICBPR, (uintptr_t) d_addr);
    126126
    127127  _ISR_Enable(level);
     
    134134  _ISR_Disable (level);
    135135
    136   _OR1K_mtspr(CPU_OR1K_SPR_ICBIR, d_addr);
     136  _OR1K_mtspr(CPU_OR1K_SPR_ICBIR, (uintptr_t) d_addr);
    137137
    138138  _ISR_Enable(level);
     
    145145  _ISR_Disable (level);
    146146
    147   _OR1K_mtspr(CPU_OR1K_SPR_ICBLR, d_addr);
     147  _OR1K_mtspr(CPU_OR1K_SPR_ICBLR, (uintptr_t) d_addr);
    148148
    149149  _ISR_Enable(level);
  • c/src/lib/libcpu/or1k/shared/cache/cache_.h

    rc7d8be5 r37885d5d  
    77
    88#include <bsp/cache_.h>
     9#include <libcpu/cache.h>
    910
    1011#endif
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