Changeset 37731c2 in rtems


Ignore:
Timestamp:
Apr 6, 2001, 3:54:20 PM (19 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
bde9bb5
Parents:
35bb69b
Message:

2001-03-30 Eric Valette <valette@…>

  • mpc8xx/exceptions/.cvsignore, mpc8xx/exceptions/Makefile.am, mpc8xx/exceptions/asm_utils.S, mpc8xx/exceptions/raw_exception.c, mpc8xx/exceptions/raw_exception.h: New files.
  • configure.in, mpc6xx/mmu/bat.h, mpc8xx/Makefile.am, mpc8xx/clock/clock.c, mpc8xx/console-generic/console-generic.c, mpc8xx/include/mpc8xx.h, mpc8xx/mmu/mmu.c, new_exception_processing/cpu.h, shared/include/byteorder.h, wrapup/Makefile.am: This is conversion of the mpc8xx CPU to the "new exception processing model."
Location:
c/src/lib
Files:
5 added
12 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/support/new_exception_processing/cpu.h

    r35bb69b r37731c2  
    441441  boolean      exceptions_in_RAM;     /* TRUE if in RAM */
    442442
     443#if (defined(ppc403) || defined(mpc860) || defined(mpc821))
     444  unsigned32   serial_per_sec;         /* Serial clocks per second */
     445  boolean      serial_external_clock;
     446  boolean      serial_xon_xoff;
     447  boolean      serial_cts_rts;
     448  unsigned32   serial_rate;
     449  unsigned32   timer_average_overhead; /* Average overhead of timer in ticks */
     450  unsigned32   timer_least_valid;      /* Least valid number from timer      */
     451  boolean      timer_internal_clock;   /* TRUE, when timer runs with CPU clk */
     452#endif
     453
     454#if (defined(mpc860) || defined(mpc821))
     455  unsigned32   clock_speed;            /* Speed of CPU in Hz */
     456#endif
    443457}   rtems_cpu_table;
    444458
  • c/src/lib/libcpu/powerpc/ChangeLog

    r35bb69b r37731c2  
     12001-03-30      Eric Valette <valette@crf.canon.fr>
     2
     3        * mpc8xx/exceptions/.cvsignore, mpc8xx/exceptions/Makefile.am,
     4        mpc8xx/exceptions/asm_utils.S, mpc8xx/exceptions/raw_exception.c,
     5        mpc8xx/exceptions/raw_exception.h: New files.
     6        * configure.in, mpc6xx/mmu/bat.h, mpc8xx/Makefile.am,
     7        mpc8xx/clock/clock.c,
     8        mpc8xx/console-generic/console-generic.c,
     9        mpc8xx/include/mpc8xx.h, mpc8xx/mmu/mmu.c,
     10        new_exception_processing/cpu.h, shared/include/byteorder.h,
     11        wrapup/Makefile.am:  This is conversion of the
     12        mpc8xx CPU to the "new exception processing model."
     13
    1142001-02-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    215
  • c/src/lib/libcpu/powerpc/configure.in

    r35bb69b r37731c2  
    3838AM_CONDITIONAL(new_exception_processing, \
    3939test "$RTEMS_CPU_MODEL" = "mpc750" || \
    40 test "$RTEMS_CPU_MODEL" = "mpc604")
     40test "$RTEMS_CPU_MODEL" = "mpc604" || \
     41test "$RTEMS_CPU_MODEL" = "mpc8xx" || \
     42test "$RTEMS_CPU_MODEL" = "mpc860")
    4143
    4244## The goal is to get rid of the old exception processing code but
     
    4648test "$RTEMS_CPU_MODEL" = "ppc403" || \
    4749test "$RTEMS_CPU_MODEL" = "mpc505" || \
    48 test "$RTEMS_CPU_MODEL" = "ppc603e" || \
    49 test "$RTEMS_CPU_MODEL" = "mpc8xx" \
     50test "$RTEMS_CPU_MODEL" = "ppc603e" \
    5051)
    5152
     
    7172mpc8xx/console-generic/Makefile
    7273mpc8xx/cpm/Makefile
     74mpc8xx/exceptions/Makefile
    7375mpc8xx/include/Makefile
    7476mpc8xx/mmu/Makefile
    7577mpc8xx/timer/Makefile
    76 mpc8xx/vectors/Makefile
    7778ppc403/Makefile
    7879ppc403/clock/Makefile
  • c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.h

    r35bb69b r37731c2  
    2626#include <libcpu/mmu.h>
    2727#include <libcpu/pgtable.h>
    28 #include <bsp/consoleIo.h>
     28#include <bspIo.h>
    2929
    3030#define IO_PAGE (_PAGE_NO_CACHE | _PAGE_GUARDED | _PAGE_RW)
  • c/src/lib/libcpu/powerpc/mpc8xx/Makefile.am

    r35bb69b r37731c2  
    55AUTOMAKE_OPTIONS = foreign 1.4
    66
    7 SUBDIRS = include console-generic clock timer vectors cpm mmu
     7SUBDIRS = include console-generic clock timer cpm mmu exceptions
    88
    99include $(top_srcdir)/../../../../../automake/subdirs.am
  • c/src/lib/libcpu/powerpc/mpc8xx/clock/clock.c

    r35bb69b r37731c2  
    4646volatile rtems_unsigned32 Clock_driver_ticks;
    4747extern volatile m8xx_t m8xx;
     48extern int BSP_get_clock_irq_level();
     49extern int BSP_connect_clock_handler(rtems_isr_entry);
     50extern int BSP_disconnect_clock_handler();
    4851
    4952void Clock_exit( void );
    50  
     53
    5154/*
    5255 * These are set by clock driver during its init
     
    6669}
    6770
    68 void Install_clock(rtems_isr_entry clock_isr)
     71void clockOn(void* unused)
    6972{
    70 #ifdef EPPCBUG_SMC1
    71   extern unsigned32 simask_copy;
    72 #endif /* EPPCBUG_SMC1 */
    73  
    74   rtems_isr_entry previous_isr;
     73  unsigned desiredLevel;
    7574  rtems_unsigned32 pit_value;
    76  
    77   Clock_driver_ticks = 0;
    7875 
    7976  pit_value = (rtems_configuration_get_microseconds_per_tick() *
     
    8279  if (pit_value > 0xffff) {           /* pit is only 16 bits long */
    8380    rtems_fatal_error_occurred(-1);
    84   } 
    85 
    86   /*
    87    * initialize the interval here
    88    * First tick is set to right amount of time in the future
    89    * Future ticks will be incremented over last value set
    90    * in order to provide consistent clicks in the face of
    91    * interrupt overhead
    92    */
    93  
    94   rtems_interrupt_catch(clock_isr, PPC_IRQ_LVL0, &previous_isr);
    95  
     81  }
    9682  m8xx.sccr &= ~(1<<24);
    9783  m8xx.pitc = pit_value;
    98  
     84
     85  desiredLevel = BSP_get_clock_irq_level();
    9986  /* set PIT irq level, enable PIT, PIT interrupts */
    10087  /*  and clear int. status */
    101   m8xx.piscr = M8xx_PISCR_PIRQ(0) |
    102     M8xx_PISCR_PTE | M8xx_PISCR_PS | M8xx_PISCR_PIE;
    103    
    104 #ifdef EPPCBUG_SMC1
    105   simask_copy = m8xx.simask | M8xx_SIMASK_LVM0;
    106 #endif /* EPPCBUG_SMC1 */
    107   m8xx.simask |= M8xx_SIMASK_LVM0;
    108   atexit(Clock_exit);
     88  m8xx.piscr = M8xx_PISCR_PIRQ(desiredLevel) |
     89    M8xx_PISCR_PTE | M8xx_PISCR_PS | M8xx_PISCR_PIE;
     90}
     91/*
     92 * Called via atexit()
     93 * Remove the clock interrupt handler by setting handler to NULL
     94 */
     95void
     96clockOff(void* unused)
     97{
     98  /* disable PIT and PIT interrupts */
     99  m8xx.piscr &= ~(M8xx_PISCR_PTE | M8xx_PISCR_PIE);
    109100}
    110101
    111 void
    112 ReInstall_clock(rtems_isr_entry new_clock_isr)
     102int clockIsOn(void* unused)
    113103{
    114   rtems_isr_entry previous_isr;
    115   rtems_unsigned32 isrlevel = 0;
    116  
    117   rtems_interrupt_disable(isrlevel);
    118  
    119   rtems_interrupt_catch(new_clock_isr, PPC_IRQ_LVL0, &previous_isr);
    120  
    121   rtems_interrupt_enable(isrlevel);
     104  if (m8xx.piscr & M8xx_PISCR_PIE) return 1;
     105  return 0;
    122106}
    123 
    124107
    125108/*
     
    130113Clock_exit(void)
    131114{
    132   /* disable PIT and PIT interrupts */
    133   m8xx.piscr &= ~(M8xx_PISCR_PTE | M8xx_PISCR_PIE);
    134  
    135   (void) set_vector(0, PPC_IRQ_LVL0, 1);
     115  (void) BSP_disconnect_clock_handler ();
    136116}
     117
     118void Install_clock(rtems_isr_entry clock_isr)
     119{
     120  Clock_driver_ticks = 0;
     121
     122  BSP_connect_clock_handler (clock_isr);
     123  atexit(Clock_exit);
     124}
     125
     126void
     127ReInstall_clock(rtems_isr_entry new_clock_isr)
     128{
     129  BSP_connect_clock_handler (new_clock_isr);
     130}
     131
    137132
    138133rtems_device_driver Clock_initialize(
     
    143138{
    144139  Install_clock( Clock_isr );
    145  
     140  
    146141  /*
    147142   * make major/minor avail to others such as shared memory driver
  • c/src/lib/libcpu/powerpc/mpc8xx/console-generic/console-generic.c

    r35bb69b r37731c2  
    5454#include <unistd.h>
    5555#include <termios.h>
     56#include <bsp/irq.h>
     57#include <bspIo.h>   /* for printk */
    5658
    5759extern rtems_cpu_table Cpu_table;
     
    5961/* BSP supplied routine */
    6062extern int mbx8xx_console_get_configuration();
    61 
    62 #ifdef EPPCBUG_SMC1
    63 extern unsigned32 simask_copy;
    64 #endif
    6563
    6664/*
     
    8987struct rtems_termios_tty *ttyp[NUM_PORTS];
    9088
    91 /* Used to record previous ISR */
    92 static rtems_isr_entry old_handler[NUM_PORTS];
    93 
    9489/*
    9590 * Device-specific routines
     
    10095static int m8xx_smc_set_attributes(int, const struct termios*);
    10196static int m8xx_scc_set_attributes(int, const struct termios*);
    102 static rtems_isr m8xx_smc1_interrupt_handler(rtems_vector_number);
    103 static rtems_isr m8xx_smc2_interrupt_handler(rtems_vector_number);
    104 static rtems_isr m8xx_scc2_interrupt_handler(rtems_vector_number);
     97static void m8xx_smc1_interrupt_handler(void);
     98static void m8xx_smc2_interrupt_handler(void);
     99static void m8xx_scc2_interrupt_handler(void);
    105100#if defined(mpc860)
    106 static rtems_isr m8xx_scc3_interrupt_handler(rtems_vector_number);
    107 static rtems_isr m8xx_scc4_interrupt_handler(rtems_vector_number);
     101static void m8xx_scc3_interrupt_handler(void);
     102static void m8xx_scc4_interrupt_handler(void);
    108103#endif
    109104
     
    388383 * Interrupt handlers
    389384 */
    390 static rtems_isr
    391 m8xx_scc2_interrupt_handler (rtems_vector_number v)
     385static void m8xx_scc2_interrupt_handler ()
    392386{
    393387  int nb_overflow;
     
    426420        (int)TxBd[SCC2_MINOR]->length);
    427421  }
    428   m8xx.cisr = 1UL << 29;  /* Clear SCC2 interrupt-in-service bit */
    429422}
    430423
    431424
    432425#ifdef mpc860
    433 static rtems_isr
    434 m8xx_scc3_interrupt_handler (rtems_vector_number v)
     426static void
     427m8xx_scc3_interrupt_handler (void)
    435428{
    436429  int nb_overflow;
     
    469462        (int)TxBd[SCC3_MINOR]->length);
    470463  }
    471   m8xx.cisr = 1UL << 28;  /* Clear SCC3 interrupt-in-service bit */
    472 }
    473 
    474 
    475 static rtems_isr
    476 m8xx_scc4_interrupt_handler (rtems_vector_number v)
     464}
     465
     466
     467static void
     468m8xx_scc4_interrupt_handler (void)
    477469{
    478470  int nb_overflow;
     
    511503        (int)TxBd[SCC4_MINOR]->length);
    512504  }
    513   m8xx.cisr = 1UL << 27;  /* Clear SCC4 interrupt-in-service bit */
    514505}
    515506#endif
    516507
    517 static rtems_isr
    518 m8xx_smc1_interrupt_handler (rtems_vector_number v)
     508static void
     509m8xx_smc1_interrupt_handler (void)
    519510{
    520511  int nb_overflow;
     
    553544        (int)TxBd[SMC1_MINOR]->length);
    554545  }
    555   m8xx.cisr = 1UL << 4;  /* Clear SMC1 interrupt-in-service bit */
    556 }
    557 
    558 
    559 static rtems_isr
    560 m8xx_smc2_interrupt_handler (rtems_vector_number v)
     546}
     547
     548
     549static void
     550m8xx_smc2_interrupt_handler (void)
    561551{
    562552  int nb_overflow;
     
    595585        (int)TxBd[SMC2_MINOR]->length);
    596586  }
    597   m8xx.cisr = 1UL << 3;  /* Clear SMC2 interrupt-in-service bit */
    598 }
    599 
    600 
     587}
     588
     589void m8xx_scc_enable(const rtems_irq_connect_data* ptr)
     590{
     591  volatile m8xxSCCRegisters_t *sccregs = 0;
     592  switch (ptr->name) {
     593#if defined(mpc860)
     594  case BSP_CPM_IRQ_SCC4 :
     595    sccregs = &m8xx.scc4;
     596    break;
     597  case BSP_CPM_IRQ_SCC3 :
     598    sccregs = &m8xx.scc3;
     599    break;
     600#endif
     601  case BSP_CPM_IRQ_SCC2 :
     602    sccregs = &m8xx.scc2;
     603    break;
     604  case BSP_CPM_IRQ_SCC1 :
     605    sccregs = &m8xx.scc1;
     606    break;
     607  default:
     608    break;
     609  }
     610  sccregs->sccm = 3;
     611}
     612
     613void m8xx_scc_disable(const rtems_irq_connect_data* ptr)
     614{
     615  volatile m8xxSCCRegisters_t *sccregs = 0;
     616  switch (ptr->name) {
     617#if defined(mpc860)
     618  case BSP_CPM_IRQ_SCC4 :
     619    sccregs = &m8xx.scc4;
     620    break;
     621  case BSP_CPM_IRQ_SCC3 :
     622    sccregs = &m8xx.scc3;
     623    break;
     624#endif
     625  case BSP_CPM_IRQ_SCC2 :
     626    sccregs = &m8xx.scc2;
     627    break;
     628  case BSP_CPM_IRQ_SCC1 :
     629    sccregs = &m8xx.scc1;
     630    break;
     631  default:
     632    break;
     633  }
     634  sccregs->sccm &= (~3);
     635}
     636
     637int m8xx_scc_isOn(const rtems_irq_connect_data* ptr)
     638{
     639 return BSP_irq_enabled_at_cpm (ptr->name);
     640}
     641
     642static rtems_irq_connect_data consoleIrqData =
     643{
     644  BSP_CPM_IRQ_SCC2,
     645  (rtems_irq_hdl)m8xx_scc2_interrupt_handler,
     646  (rtems_irq_enable) m8xx_scc_enable,
     647  (rtems_irq_disable) m8xx_scc_disable,
     648  (rtems_irq_is_enabled) m8xx_scc_isOn
     649};
     650       
    601651void
    602652m8xx_uart_scc_initialize (int minor)
     
    605655  volatile m8xxSCCparms_t *sccparms = 0;
    606656  volatile m8xxSCCRegisters_t *sccregs = 0;
     657  int res;
    607658
    608659  /*
     
    778829    switch (minor) {
    779830      case SCC2_MINOR:
    780         rtems_interrupt_catch (m8xx_scc2_interrupt_handler,
    781                                PPC_IRQ_CPM_SCC2,
    782                                &old_handler[minor]);
    783 
    784         sccregs->sccm = 3;            /* Enable SCC2 Rx & Tx interrupts */
    785         m8xx.cimr |= 1UL <<  29;      /* Enable SCC2 interrupts */
    786831        break;
    787832
    788833#ifdef mpc860
    789       case SCC3_MINOR:
    790         rtems_interrupt_catch (m8xx_scc3_interrupt_handler,
    791                                PPC_IRQ_CPM_SCC3,
    792                                &old_handler[minor]);
    793 
    794         sccregs->sccm = 3;            /* Enable SCC2 Rx & Tx interrupts */
    795         m8xx.cimr |= 1UL <<  28;      /* Enable SCC2 interrupts */
    796         break;
     834    case SCC3_MINOR:
     835      consoleIrqData.name = BSP_CPM_IRQ_SCC3;
     836      consoleIrqData.hdl = m8xx_scc3_interrupt_handler;
     837      break;
    797838     
    798       case SCC4_MINOR:
    799         rtems_interrupt_catch (m8xx_scc4_interrupt_handler,
    800                                PPC_IRQ_CPM_SCC4,
    801                                &old_handler[minor]);
    802 
    803         sccregs->sccm = 3;            /* Enable SCC2 Rx & Tx interrupts */
    804         m8xx.cimr |= 1UL <<  27;      /* Enable SCC2 interrupts */
    805         break;
     839    case SCC4_MINOR:
     840      consoleIrqData.name = BSP_CPM_IRQ_SCC4;
     841      consoleIrqData.hdl = m8xx_scc4_interrupt_handler;
     842      break;
    806843#endif /* mpc860 */
    807844    }
    808   }
    809 }
    810 
     845    if (!BSP_install_rtems_irq_handler (&consoleIrqData)) {
     846        printk("Unable to connect SCC Irq handler\n");
     847        rtems_fatal_error_occurred(1);
     848    }
     849  }
     850}
     851
     852void m8xx_smc_enable(const rtems_irq_connect_data* ptr)
     853{
     854  volatile m8xxSMCRegisters_t *smcregs = 0;
     855  switch (ptr->name) {
     856  case BSP_CPM_IRQ_SMC1 :
     857    smcregs = &m8xx.smc1;
     858    break;
     859  case BSP_CPM_IRQ_SMC2_OR_PIP :
     860    smcregs = &m8xx.smc2;
     861    break;
     862  default:
     863    break;
     864  }
     865  smcregs->smcm = 3;
     866}
     867
     868void m8xx_smc_disable(const rtems_irq_connect_data* ptr)
     869{
     870  volatile m8xxSMCRegisters_t *smcregs = 0;
     871  switch (ptr->name) {
     872  case BSP_CPM_IRQ_SMC1 :
     873    smcregs = &m8xx.smc1;
     874    break;
     875  case BSP_CPM_IRQ_SMC2_OR_PIP :
     876    smcregs = &m8xx.smc2;
     877    break;
     878  default:
     879    break;
     880  }
     881  smcregs->smcm &= (~3);
     882}
     883
     884int m8xx_smc_isOn(const rtems_irq_connect_data* ptr)
     885{
     886 return BSP_irq_enabled_at_cpm (ptr->name);
     887}
    811888
    812889void
     
    9241001  smcregs->smcmr |= M8xx_SMCMR_TEN | M8xx_SMCMR_REN;
    9251002  if ( (mbx8xx_console_get_configuration() & 0x06) == 0x02 ) {
     1003    consoleIrqData.on = m8xx_smc_enable;
     1004    consoleIrqData.off = m8xx_smc_disable;
     1005    consoleIrqData.isOn = m8xx_smc_isOn;
    9261006    switch (minor) {
    927       case SMC1_MINOR:
    928         rtems_interrupt_catch (m8xx_smc1_interrupt_handler,
    929                                     PPC_IRQ_CPM_SMC1,
    930                                     &old_handler[minor]);
    931 
    932         smcregs->smcm = 3;            /* Enable SMC1 Rx & Tx interrupts */
    933         m8xx.cimr |= 1UL <<  4;       /* Enable SMC1 interrupts */
    934         break;
     1007        case SMC1_MINOR:
     1008          consoleIrqData.name = BSP_CPM_IRQ_SMC1;
     1009          consoleIrqData.hdl  = m8xx_smc1_interrupt_handler;
     1010          break;
    9351011     
    936       case SMC2_MINOR:
    937         rtems_interrupt_catch (m8xx_smc2_interrupt_handler,
    938                                     PPC_IRQ_CPM_SMC2,
    939                                     &old_handler[minor]);
    940 
    941         smcregs->smcm = 3;            /* Enable SMC2 Rx & Tx interrupts */
    942         m8xx.cimr |= 1UL <<  3;       /* Enable SMC2 interrupts */
    943         break;
     1012        case SMC2_MINOR:
     1013          consoleIrqData.name = BSP_CPM_IRQ_SMC2_OR_PIP;
     1014          consoleIrqData.hdl  = m8xx_smc2_interrupt_handler;
     1015          break;
     1016    }
     1017    if (!BSP_install_rtems_irq_handler (&consoleIrqData)) {
     1018        printk("Unable to connect SMC Irq handler\n");
     1019        rtems_fatal_error_occurred(1);
    9441020    }
    9451021  }
     
    9571033}
    9581034
    959 
    960 void
    961 m8xx_uart_interrupts_initialize(void)
    962 {
    963 #ifdef mpc860
    964   m8xx.cicr = 0x00E43F80;           /* SCaP=SCC1, SCbP=SCC2, SCcP=SCC3,
    965                                        SCdP=SCC4, IRL=1, HP=PC15, IEN=1 */
    966 #else
    967   m8xx.cicr = 0x00043F80;           /* SCaP=SCC1, SCbP=SCC2, IRL=1, HP=PC15, IEN=1 */
    968 #endif
    969   m8xx.simask |= M8xx_SIMASK_LVM1;  /* Enable level interrupts */
    970 #ifdef EPPCBUG_SMC1
    971   simask_copy = m8xx.simask;
    972 #endif
    973 }
    9741035
    9751036
  • c/src/lib/libcpu/powerpc/mpc8xx/include/mpc8xx.h

    r35bb69b r37731c2  
    650650*/
    651651typedef struct m8xxBufferDescriptor_ {
    652   rtems_unsigned16        status;
    653   rtems_unsigned16        length;
    654   volatile void           *buffer;
     652  volatile rtems_unsigned16        status;
     653  rtems_unsigned16                 length;
     654  volatile void                    *buffer;
    655655} m8xxBufferDescriptor_t;
    656656
  • c/src/lib/libcpu/powerpc/mpc8xx/mmu/mmu.c

    r35bb69b r37731c2  
    116116   * Turn on address translation by setting MSR[IR] and MSR[DR].
    117117   */
    118   _CPU_MSR_Value( reg1 );
     118  _CPU_MSR_GET( reg1 );
    119119  reg1 |= PPC_MSR_IR | PPC_MSR_DR;
    120120  _CPU_MSR_SET( reg1 );
  • c/src/lib/libcpu/powerpc/new_exception_processing/cpu.h

    r35bb69b r37731c2  
    441441  boolean      exceptions_in_RAM;     /* TRUE if in RAM */
    442442
     443#if (defined(ppc403) || defined(mpc860) || defined(mpc821))
     444  unsigned32   serial_per_sec;         /* Serial clocks per second */
     445  boolean      serial_external_clock;
     446  boolean      serial_xon_xoff;
     447  boolean      serial_cts_rts;
     448  unsigned32   serial_rate;
     449  unsigned32   timer_average_overhead; /* Average overhead of timer in ticks */
     450  unsigned32   timer_least_valid;      /* Least valid number from timer      */
     451  boolean      timer_internal_clock;   /* TRUE, when timer runs with CPU clk */
     452#endif
     453
     454#if (defined(mpc860) || defined(mpc821))
     455  unsigned32   clock_speed;            /* Speed of CPU in Hz */
     456#endif
    443457}   rtems_cpu_table;
    444458
  • c/src/lib/libcpu/powerpc/shared/include/byteorder.h

    r35bb69b r37731c2  
    1919#ifndef _PPC_BYTEORDER_H
    2020#define _PPC_BYTEORDER_H
    21 
    22 /*
    23  *  $Id$
    24  */
    2521
    2622#ifdef __GNUC__
  • c/src/lib/libcpu/powerpc/wrapup/Makefile.am

    r35bb69b r37731c2  
    1111CPU_SPECIFIC_OBJS = $(wildcard ../$(RTEMS_CPU_MODEL)/*/$(ARCH)/*.o)
    1212FAMILY_OBJS = \
    13     $(wildcard ../shared/$(ARCH)/*.o ../shared/*/$(ARCH)/*.o ../old_exception_processing/*/$(ARCH)/*.o ../new_exception_processing/*/$(ARCH)/*.o ../mpc6xx/*/$(ARCH)/*.o)
     13    $(wildcard ../shared/$(ARCH)/*.o ../shared/*/$(ARCH)/*.o \
     14        ../old_exception_processing/*/$(ARCH)/*.o \
     15        ../new_exception_processing/*/$(ARCH)/*.o \
     16        ../mpc6xx/*/$(ARCH)/*.o)
    1417
    1518LIB = $(ARCH)/libcpu.a
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