Changeset 36e95a87 in rtems


Ignore:
Timestamp:
Jul 18, 2003, 5:23:40 PM (18 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Children:
d5fa273e
Parents:
b997f52
Message:

2003-07-18 Till Straumann <strauman@…>

PR 288/rtems

  • rtems/new-exceptions/cpu.h: _ISR_Nest_level is now properly maintained and does not reside in SPRG0.
Location:
cpukit/score/cpu/powerpc
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/powerpc/ChangeLog

    rb997f52 r36e95a87  
     12003-07-18      Till Straumann <strauman@slac.stanford.edu>
     2
     3        PR 288/rtems
     4        * rtems/new-exceptions/cpu.h: _ISR_Nest_level is now properly
     5        maintained and does not reside in SPRG0.
     6
    172003-03-06      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    28
  • cpukit/score/cpu/powerpc/rtems/new-exceptions/cpu.h

    rb997f52 r36e95a87  
    540540/*
    541541 *  This is defined if the port has a special way to report the ISR nesting
    542  *  level.  Most ports maintain the variable _ISR_Nest_level.
    543  */
    544 
    545 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS TRUE
     542 *  level.  Most ports maintain the variable _ISR_Nest_level. Note that
     543 *  this is not an option - RTEMS/score _relies_ on _ISR_Nest_level
     544 *  being maintained (e.g. watchdog queues).
     545 */
     546
     547#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
    546548
    547549/*
     
    831833 *
    832834 *  This routine performs CPU dependent initialization.
    833  */
     835 *
     836 *  Until all new-exception processing BSPs have fixed
     837 *  PR288, we let the good BSPs pass
     838 *
     839 *  PPC_BSP_HAS_FIXED_PR288
     840 *
     841 *  in SPRG0 and let _CPU_Initialize assert this.
     842 */
     843
     844#define PPC_BSP_HAS_FIXED_PR288 0x600dbabe
    834845
    835846void _CPU_Initialize(
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