Changeset 36e95a87 in rtems

Timestamp:

Jul 18, 2003, 5:23:40 PM (18 years ago)

Author:

Joel Sherrill <joel.sherrill@…>

Children:

d5fa273e

Parents:

b997f52

Message:

2003-07-18 Till Straumann <strauman@…>

PR 288/rtems

• rtems/new-exceptions/cpu.h: _ISR_Nest_level is now properly maintained and does not reside in SPRG0.

Location:

cpukit/score/cpu/powerpc

Files:

• ChangeLog (modified) (1 diff)
• rtems/new-exceptions/cpu.h (modified) (2 diffs)

cpukit/score/cpu/powerpc/ChangeLog

@@ +1 @@
+2003-07-18      Till Straumann <strauman@slac.stanford.edu>
+
+        PR 288/rtems
+        * rtems/new-exceptions/cpu.h: _ISR_Nest_level is now properly
+        maintained and does not reside in SPRG0.
+
 2003-03-06      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
 

cpukit/score/cpu/powerpc/rtems/new-exceptions/cpu.h

@@ -540 +540 @@
 /*
  *  This is defined if the port has a special way to report the ISR nesting
- *  level.  Most ports maintain the variable _ISR_Nest_level.
- */
-
-#define CPU_PROVIDES_ISR_IS_IN_PROGRESS TRUE
+ *  level.  Most ports maintain the variable _ISR_Nest_level. Note that
+ *  this is not an option - RTEMS/score _relies_ on _ISR_Nest_level
+ *  being maintained (e.g. watchdog queues).
+ */
+
+#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
 
 /*
@@ -831 +833 @@
  *
  *  This routine performs CPU dependent initialization.
- */
+ *
+ *  Until all new-exception processing BSPs have fixed
+ *  PR288, we let the good BSPs pass
+ *
+ *  PPC_BSP_HAS_FIXED_PR288
+ *
+ *  in SPRG0 and let _CPU_Initialize assert this.
+ */
+
+#define PPC_BSP_HAS_FIXED_PR288 0x600dbabe
 
 void _CPU_Initialize(