Changeset 367a0e2 in rtems


Ignore:
Timestamp:
Jul 18, 2003, 3:48:54 PM (17 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Children:
734d1c5d
Parents:
cfc257fc
Message:

2003-07-16 Greg Menke <gregory.menke@…>

PR 428/bsps
PR 432/bsps

  • bootloader/pci.c: Re-instated code that prevents remapping small IO regions, which if remapped would cause i8259 registers to move out from under the #define'd base addresses.
  • startup/bspstart.c: Reduced BAT2 PCI memory allocation to 256 megs, I incorrectly had extended it which would cause problems with PCI devices that defined prefetchable memory.
Location:
c/src/lib/libbsp/powerpc/shared
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/shared/ChangeLog

    rcfc257fc r367a0e2  
     12003-07-16      Greg Menke <gregory.menke@gsfc.nasa.gov>
     2
     3        PR 428/bsps
     4        PR 432/bsps
     5        * bootloader/pci.c: Re-instated code that prevents remapping small
     6        IO regions, which if remapped would cause i8259 registers to move
     7        out from under the #define'd base addresses.
     8        * startup/bspstart.c: Reduced BAT2 PCI memory allocation to 256
     9        megs, I incorrectly had extended it which would cause problems with
     10        PCI devices that defined prefetchable memory.
     11       
    1122003-06-13      Greg Menke <gregory.menke@gsfc.nasa.gov>
    213
  • c/src/lib/libbsp/powerpc/shared/bootloader/pci.c

    rcfc257fc r367a0e2  
    3030typedef unsigned int u32;
    3131
    32 /*#define DEBUG*/
     32
     33/*
     34#define DEBUG
     35#define PCI_DEBUG
     36*/
     37
     38
    3339/* Used to reorganize PCI space on stupid machines which spread resources
    3440 * across a wide address space. This is bad when P2P bridges are present
     
    216222    */
    217223
    218 #if 0
     224   /*
     225   ** This is little ugly below.  It seems that at least on the MCP750,
     226   ** the PBC has some default IO space mappings that the bsp #defines
     227   ** that read/write to PCI I/O space assume, particuarly the i8259
     228   ** manipulation code.  So, if we allow the small IO spaces on PCI bus
     229   ** 0 and 1 to be remapped, the registers can shift out from under the
     230   ** #defines.  This is particuarly awful, but short of redefining the
     231   ** PCI I/O primitives to be functions with base addresses read from
     232   ** the hardware, we are stuck with the kludge below.  Note that
     233   ** everything is remapped on the CPCI backplane and any downstream
     234   ** hardware, its just the builtin stuff we're tiptoeing around.
     235   **
     236   ** Gregm, 7/16/2003
     237   */
     238   if( r->dev->bus->number <= 1 )
     239   {
    219240   if ((r->type==PCI_BASE_ADDRESS_SPACE_IO)
    220241       ? (r->base && r->base <0x10000)
    221242       : (r->base && r->base <0x1000000)) {
     243
     244#ifdef PCI_DEBUG
     245         printk("freeing region;  %p:%p %d:%02x (%04x:%04x) %08lx %08lx %d\n",
     246                r, r->next,
     247                r->dev->bus->number, PCI_SLOT(r->dev->devfn),
     248                r->dev->vendor, r->dev->device,
     249                r->base,
     250                r->size,
     251                r->type);
     252#endif
    222253      sfree(r);
    223254      return;
    224255   }
    225 #endif
     256   }
    226257
    227258   if ((r->type==PCI_BASE_ADDRESS_SPACE_IO)
     
    483514#define BUSREST_IO_END          0x7ffff
    484515#define BUSREST_MEM_START       0xb000000
    485 #define BUSREST_MEM_END        0x30000000
     516#define BUSREST_MEM_END        0x10000000
    486517
    487518
     
    11121143
    11131144
    1114 #define MEMORY_IO_GRANULARITY   256
    11151145
    11161146
     
    12481278#ifdef WRITE_BRIDGE_ENABLE
    12491279         pcibios_write_config_word(pdev->bus->number, pdev->devfn, PCI_BRIDGE_CONTROL, (unsigned16)( PCI_BRIDGE_CTL_PARITY |
    1250                                                                                                      PCI_BRIDGE_CTL_SERR |
    1251                                                                                                      PCI_BRIDGE_CTL_FAST_BACK));
     1280                                                                                                     PCI_BRIDGE_CTL_SERR ));
    12521281
    12531282         pcibios_write_config_word(pdev->bus->number, pdev->devfn, PCI_COMMAND, (unsigned16)( PCI_COMMAND_IO |
     
    12551284                                                                                              PCI_COMMAND_MASTER |
    12561285                                                                                              PCI_COMMAND_PARITY |
    1257                                                                                               PCI_COMMAND_WAIT |
    1258                                                                                               PCI_COMMAND_SERR |
    1259                                                                                               PCI_COMMAND_FAST_BACK ));
     1286                                                                                              PCI_COMMAND_SERR ));
    12601287#endif
    12611288      }
     
    13161343
    13171344                  r->base = astart.start_pciio;
    1318                   astart.start_pciio += (alloc= ((r->size / MEMORY_IO_GRANULARITY) + 1) * MEMORY_IO_GRANULARITY);
     1345                  astart.start_pciio += (alloc= ((r->size / PAGE_SIZE) + 1) * PAGE_SIZE);
    13191346#ifdef PCI_DEBUG
    13201347                  printk("pci:      io  %08X, size %08X, alloc %08X\n", r->base, r->size, alloc );
     
    13301357
    13311358                  r->base = astart.start_pcimem;
    1332                   astart.start_pcimem += (alloc= ((r->size / MEMORY_IO_GRANULARITY) + 1) * MEMORY_IO_GRANULARITY);
     1359                  astart.start_pcimem += (alloc= ((r->size / PAGE_SIZE) + 1) * PAGE_SIZE);
    13331360#ifdef PCI_DEBUG
    13341361                  printk("pci:      mem %08X, size %08X, alloc %08X\n", r->base, r->size, alloc );
     
    14061433
    14071434   recursive_bus_reconfigure(NULL);
     1435
    14081436   reconfigure_pci();
    14091437
  • c/src/lib/libbsp/powerpc/shared/pci/pcifinddevice.c

    rcfc257fc r367a0e2  
    1515
    1616int
    17 BSP_pciFindDevice(unsigned short vendorid, unsigned short deviceid,
    18                 int instance, int *pbus, int *pdev, int *pfun)
     17BSP_pciFindDevice( unsigned short vendorid, unsigned short deviceid,
     18                   int instance, int *pbus, int *pdev, int *pfun )
    1919{
    20 unsigned int d;
    21 unsigned short s;
    22 unsigned char bus,dev,fun,hd;
     20   unsigned int d;
     21   unsigned short s;
     22   unsigned char bus,dev,fun,hd;
    2323
    2424        for (bus=0; bus<BusCountPCI(); bus++) {
     
    5454    return -1;
    5555}
     56
     57/* eof */
  • c/src/lib/libbsp/powerpc/shared/startup/bspstart.c

    rcfc257fc r367a0e2  
    254254   */
    255255  /* T. Straumann: give more PCI address space */
    256   setdbat(2, PCI_MEM_BASE, PCI_MEM_BASE, 0x30000000, IO_PAGE);
     256  setdbat(2, PCI_MEM_BASE, PCI_MEM_BASE, 0x10000000, IO_PAGE);
    257257  /*
    258258   * Must have acces to open pic PCI ACK registers
     
    311311    else
    312312       printk("pci : Interrupt routing not available for this bsp\n");
    313 
    314313 }
    315 
    316314
    317315
     
    341339  /* clear hostbridge errors and enable MCP */
    342340  _BSP_clear_hostbridge_errors(1/*enableMCP*/, 0/*quiet*/);
     341
    343342
    344343  /* Allocate and set up the page table mappings
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