Changeset 3652ad35 in rtems for cpukit/score/cpu


Ignore:
Timestamp:
Sep 19, 1995, 2:53:29 PM (26 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
38ffa0c
Parents:
b3ac6a8d
Message:

Minor bug fixes to get all targets compilable and running. The
single biggest changes were the expansion of the workspace size
macro to include other types of objects and the increase in the
minimum stack size for most CPUs.

Location:
cpukit/score/cpu
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/hppa1.1/cpu.c

    rb3ac6a8d r3652ad35  
    194194hppa_external_interrupt_initialize(void)
    195195{
    196     hppa_rtems_isr_entry ignore;
     196    hppa_rtems_isr_entry ignore = 0;
    197197
    198198    /* mark them all unused */
     
    202202
    203203    /* install the external interrupt handler */
    204     rtems_interrupt_catch((rtems_isr_entry) hppa_external_interrupt,
    205                           HPPA_INTERRUPT_EXTERNAL_INTERRUPT, &ignore) ;
     204  _CPU_ISR_install_vector(
     205    HPPA_INTERRUPT_EXTERNAL_INTERRUPT,
     206    (proc_ptr)hppa_external_interrupt,
     207    (proc_ptr *)ignore
     208  );
    206209}
    207210
  • cpukit/score/cpu/i386/cpu.c

    rb3ac6a8d r3652ad35  
    3535{
    3636  register unsigned16  fp_status asm ("ax");
    37   register unsigned8  *fp_context;
     37  register void       *fp_context;
    3838
    3939  _CPU_Table = *cpu_table;
     
    5757  if ( fp_status ==  0 ) {
    5858
    59     fp_context = _CPU_Null_fp_context;
     59    fp_context = &_CPU_Null_fp_context;
    6060
    6161    asm volatile( "fsave (%0)" : "=r" (fp_context)
  • cpukit/score/cpu/unix/cpu.c

    rb3ac6a8d r3652ad35  
    11/*
    2  *  HP PA-RISC CPU Dependent Source
     2 *  UNIX Simulator Dependent Source
    33 *
    44 *
     
    1919#include <rtems/system.h>
    2020#include <rtems/core/isr.h>
     21#include <rtems/core/interr.h>
    2122
    2223#include <stdio.h>
     
    170171
    171172  _CPU_ISR_Set_level( 0 );
    172   setjmp( _CPU_Context_Default_with_ISRs_enabled.regs );
    173   sigprocmask(
    174     SIG_SETMASK,    /* ignored when second arg is NULL */
    175     0,
    176     &_CPU_Context_Default_with_ISRs_enabled.isr_level
     173  _CPU_Context_switch(
     174    &_CPU_Context_Default_with_ISRs_enabled,
     175    &_CPU_Context_Default_with_ISRs_enabled
    177176  );
    178177
    179178  _CPU_ISR_Set_level( 1 );
    180   setjmp( _CPU_Context_Default_with_ISRs_disabled.regs );
    181   sigprocmask(
    182     SIG_SETMASK,    /* ignored when second arg is NULL */
    183     0,
    184     &_CPU_Context_Default_with_ISRs_disabled.isr_level
     179  _CPU_Context_switch(
     180    &_CPU_Context_Default_with_ISRs_disabled,
     181    &_CPU_Context_Default_with_ISRs_disabled
    185182  );
    186 
    187183}
    188184
     
    192188 */
    193189
     190sigset_t GET_old_mask;
     191
    194192unsigned32 _CPU_ISR_Get_level( void )
    195193{
    196   sigset_t sigset;
    197  
    198   sigprocmask( 0, 0, &sigset );
    199 
    200   /*
    201    *  This is an educated guess based on ONLY ONE of the signals we
    202    *  disable/enable to mask ISRs.
    203    */
    204 
    205   if ( sigismember( &sigset, SIGUSR1 ) )
    206     return 1;
    207   else
    208     return 0;
     194/*  sigset_t  old_mask; */
     195   unsigned32 old_level;
     196 
     197  sigprocmask(0, 0, &GET_old_mask);
     198 
     199  if (memcmp((void *)&posix_empty_mask, (void *)&GET_old_mask, sizeof(sigset_t)))
     200    old_level = 1;
     201  else
     202    old_level = 0;
     203
     204  return old_level;
    209205}
    210206
     
    384380    source = _CPU_Context_Default_with_ISRs_disabled.regs;
    385381     
    386   memcpy(_the_context, source, sizeof(jmp_buf));
     382  memcpy(_the_context, source, sizeof(Context_Control) ); /* sizeof(jmp_buf)); */
    387383
    388384  addr = (unsigned32 *)_the_context;
     
    471467)
    472468{
     469  int status;
     470
    473471  /*
    474472   *  Switch levels in one operation
    475473   */
    476474
    477   sigprocmask( SIG_SETMASK, &next->isr_level, &current->isr_level );
     475  status = sigprocmask( SIG_SETMASK, &next->isr_level, &current->isr_level );
     476  if ( status )
     477    _Internal_error_Occurred(
     478      INTERNAL_ERROR_CORE,
     479      TRUE,
     480      status
     481    );
    478482
    479483  if (setjmp(current->regs) == 0) {    /* Save the current context */
    480484     longjmp(next->regs, 0);           /* Switch to the new context */
    481   }
     485     if ( status )
     486       _Internal_error_Occurred(
     487         INTERNAL_ERROR_CORE,
     488         TRUE,
     489         status
     490       );
     491  }
     492
    482493}
    483494 
     
    511522unsigned32 _CPU_ISR_Disable_support(void)
    512523{
     524  int status;
    513525  sigset_t  old_mask;
    514526
    515   sigprocmask(SIG_BLOCK, &_CPU_Signal_mask, &old_mask);
    516 
    517   if (memcmp((void *)&posix_empty_mask, (void *)&old_mask, sizeof(sigset_t)) != 0)
     527  status = sigprocmask(SIG_BLOCK, &_CPU_Signal_mask, &old_mask);
     528  if ( status )
     529    _Internal_error_Occurred(
     530      INTERNAL_ERROR_CORE,
     531      TRUE,
     532      status
     533    );
     534
     535  if (memcmp((void *)&posix_empty_mask, (void *)&old_mask, sizeof(sigset_t)))
    518536    return 1;
    519537
     
    530548)
    531549{
     550  int status;
     551
    532552  if (level == 0)
    533     sigprocmask(SIG_UNBLOCK, &_CPU_Signal_mask, 0);
     553    status = sigprocmask(SIG_UNBLOCK, &_CPU_Signal_mask, 0);
    534554  else
    535     sigprocmask(SIG_BLOCK, &_CPU_Signal_mask, 0);
     555    status = sigprocmask(SIG_BLOCK, &_CPU_Signal_mask, 0);
     556
     557  if ( status )
     558    _Internal_error_Occurred(
     559      INTERNAL_ERROR_CORE,
     560      TRUE,
     561      status
     562    );
    536563}
    537564
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