Changeset 363b1f7 in rtems


Ignore:
Timestamp:
May 8, 2014, 1:42:12 PM (6 years ago)
Author:
Daniel Cederman <cederman@…>
Branches:
4.11, master
Children:
c903fc2
Parents:
97d0b9b
git-author:
Daniel Cederman <cederman@…> (05/08/14 13:42:12)
git-committer:
Daniel Hellstrom <daniel@…> (05/27/14 07:46:13)
Message:

bsps/sparc: Make lines in SPARC BSPs adhere to 80 character limit.

Location:
c/src/lib/libbsp/sparc
Files:
21 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/sparc/configure.ac

    r97d0b9b r363b1f7  
    22
    33AC_PREREQ([2.69])
    4 AC_INIT([rtems-c-src-lib-libbsp-sparc],[_RTEMS_VERSION],[http://www.rtems.org/bugzilla])
     4AC_INIT([rtems-c-src-lib-libbsp-sparc],
     5[_RTEMS_VERSION],[http://www.rtems.org/bugzilla])
    56AC_CONFIG_SRCDIR([shared])
    67RTEMS_TOP(../../../../..)
  • c/src/lib/libbsp/sparc/erc32/configure.ac

    r97d0b9b r363b1f7  
    22
    33AC_PREREQ([2.69])
    4 AC_INIT([rtems-c-src-lib-libbsp-sparc-erc32],[_RTEMS_VERSION],[http://www.rtems.org/bugzilla])
     4AC_INIT([rtems-c-src-lib-libbsp-sparc-erc32],
     5[_RTEMS_VERSION],[http://www.rtems.org/bugzilla])
    56AC_CONFIG_SRCDIR([bsp_specs])
    67RTEMS_TOP(../../../../../..)
     
    2425RTEMS_BSPOPTS_HELP([CONSOLE_USE_INTERRUPTS],
    2526[The erc32 console driver can operate in either polled or interrupt mode.
    26 Under the simulator (especially when FAST_UART is defined), polled seems to operate
    27 better.  It is common for a task to print a line (like the end of test message) and
    28 then exit.  In this case, the program returns control to the simulator command line
    29 before the program has even queued the output to the uart.  Thus sis has no chance
    30 of getting the data out.])
     27Under the simulator (especially when FAST_UART is defined), polled seems
     28to operate better. It is common for a task to print a line (like the end
     29of test message) and then exit.  In this case, the program returns control
     30to the simulator command line before the program has even queued the output
     31to the uart.  Thus sis has no chance of getting the data out.])
    3132
    3233RTEMS_BSPOPTS_SET([SIMSPARC_FAST_IDLE],[*],[])
  • c/src/lib/libbsp/sparc/erc32/console/erc32_console.c

    r97d0b9b r363b1f7  
    148148
    149149#if (CONSOLE_USE_INTERRUPTS)
    150 static ssize_t erc32_console_write_support_int(int minor, const char *buf, size_t len)
     150static ssize_t erc32_console_write_support_int(
     151                int minor, const char *buf, size_t len)
    151152{
    152153  if (len > 0) {
     
    156157    if (minor == 0) { /* uart a */
    157158      for (k = 0;
    158            k < len && (ERC32_MEC.UART_Status & ERC32_MEC_UART_STATUS_THEA); k ++) {
     159           k < len && (ERC32_MEC.UART_Status & ERC32_MEC_UART_STATUS_THEA);
     160           k ++) {
    159161        ERC32_MEC.UART_Channel_A = (unsigned char)buf[k];
    160162      }
     
    162164    } else { /* uart b */
    163165      for (k = 0;
    164            k < len && (ERC32_MEC.UART_Status & ERC32_MEC_UART_STATUS_THEB); k ++) {
     166           k < len && (ERC32_MEC.UART_Status & ERC32_MEC_UART_STATUS_THEB);
     167           k ++) {
    165168        ERC32_MEC.UART_Channel_B = (unsigned char)buf[k];
    166169      }
  • c/src/lib/libbsp/sparc/erc32/erc32sonic/erc32sonic.c

    r97d0b9b r363b1f7  
    9999{
    100100
    101   ERC32_MEC.IO_Configuration |= (0x15 << (((SONIC_BASE_ADDRESS >> 24) & 0x3) * 8));
     101  ERC32_MEC.IO_Configuration |=
     102                  (0x15 << (((SONIC_BASE_ADDRESS >> 24) & 0x3) * 8));
    102103  ERC32_MEC.Control &= ~0x60001; /* Disable DMA time-out, parity & power-down */
    103104  ERC32_MEC.Control |= 0x10000;                 /* Enable DMA */
  • c/src/lib/libbsp/sparc/erc32/include/bsp.h

    r97d0b9b r363b1f7  
    9999/* Allocate 8-byte aligned non-freeable pre-malloc() memory. The function
    100100 * can be called at any time. The work-area will shrink when called before
    101  * bsp_work_area_initialize(). malloc() is called to get memory when this function
    102  * is called after bsp_work_area_initialize().
     101 * bsp_work_area_initialize(). malloc() is called to get memory when this
     102 * function is called after bsp_work_area_initialize().
    103103 */
    104104void *bsp_early_malloc(int size);
  • c/src/lib/libbsp/sparc/erc32/include/erc32.h

    r97d0b9b r363b1f7  
    258258 */
    259259
    260 #define ERC32_MEC_TIMER_CONTROL_GCR    0x00000001 /* 1 = reload at 0 */
    261                                                /* 0 = stop at 0 */
    262 #define ERC32_MEC_TIMER_CONTROL_GCL    0x00000002 /* 1 = load and start */
    263                                                /* 0 = no function */
    264 #define ERC32_MEC_TIMER_CONTROL_GSE    0x00000004 /* 1 = enable counting */
    265                                                /* 0 = hold scalar and counter */
    266 #define ERC32_MEC_TIMER_CONTROL_GSL    0x00000008  /* 1 = load scalar and start */
    267                                                /* 0 = no function */
    268 
    269 #define ERC32_MEC_TIMER_CONTROL_RTCCR  0x00000100 /* 1 = reload at 0 */
    270                                                /* 0 = stop at 0 */
    271 #define ERC32_MEC_TIMER_CONTROL_RTCCL  0x00000200 /* 1 = load and start */
    272                                                /* 0 = no function */
    273 #define ERC32_MEC_TIMER_CONTROL_RTCSE  0x00000400 /* 1 = enable counting */
    274                                                /* 0 = hold scalar and counter */
    275 #define ERC32_MEC_TIMER_CONTROL_RTCSL  0x00000800  /* 1 = load scalar and start */
    276                                                /* 0 = no function */
     260#define ERC32_MEC_TIMER_CONTROL_GCR   0x00000001 /* 1 = reload at 0 */
     261                                              /* 0 = stop at 0 */
     262#define ERC32_MEC_TIMER_CONTROL_GCL   0x00000002 /* 1 = load and start */
     263                                              /* 0 = no function */
     264#define ERC32_MEC_TIMER_CONTROL_GSE   0x00000004 /* 1 = enable counting */
     265                                              /* 0 = hold scalar and counter */
     266#define ERC32_MEC_TIMER_CONTROL_GSL   0x00000008 /* 1 = load scalar and start*/
     267                                              /* 0 = no function */
     268
     269#define ERC32_MEC_TIMER_CONTROL_RTCCR 0x00000100 /* 1 = reload at 0 */
     270                                              /* 0 = stop at 0 */
     271#define ERC32_MEC_TIMER_CONTROL_RTCCL 0x00000200 /* 1 = load and start */
     272                                              /* 0 = no function */
     273#define ERC32_MEC_TIMER_CONTROL_RTCSE 0x00000400 /* 1 = enable counting */
     274                                              /* 0 = hold scalar and counter */
     275#define ERC32_MEC_TIMER_CONTROL_RTCSL 0x00000800 /* 1 = load scalar and start*/
     276                                              /* 0 = no function */
    277277
    278278/*
  • c/src/lib/libbsp/sparc/leon2/cchip/cchip.c

    r97d0b9b r363b1f7  
    167167        printk("AMBA: PCIBAR[%d]: 0x%x, 0x%x\n\r",2,ambab->bar2,pcib->bar2);
    168168#endif
    169         ambab->ambabars[0] = 0x40000000; /* 0xe0000000(AMBA) ==> 0x40000000(PCI) ==> 0x40000000(AT697 AMBA) */
     169        /* 0xe0000000(AMBA) ==> 0x40000000(PCI) ==> 0x40000000(AT697 AMBA) */
     170        ambab->ambabars[0] = 0x40000000;
    170171
    171172        /* Scan bus for AMBA devices */
     
    329330        int_handlers[irqno].arg = arg;
    330331#ifdef DEBUG
    331         printk("Registering IRQ %d to 0x%lx(%d,0x%lx)\n\r",irqno,(unsigned int)handler,irqno,(unsigned int)arg);
     332        printk("Registering IRQ %d to 0x%lx(%d,0x%lx)\n\r",
     333                        irqno,(unsigned int)handler,irqno,(unsigned int)arg);
    332334#endif
    333335        cc1.pcib->imask |= 1<<irqno; /* Enable the registered IRQ */
  • c/src/lib/libbsp/sparc/leon2/clock/ckinit.c

    r97d0b9b r363b1f7  
    4747#define Clock_driver_support_initialize_hardware() \
    4848  do { \
    49     LEON_REG.Timer_Reload_1 = rtems_configuration_get_microseconds_per_tick() - 1; \
     49    LEON_REG.Timer_Reload_1 = \
     50                rtems_configuration_get_microseconds_per_tick() - 1; \
    5051    \
    5152    LEON_REG.Timer_Control_1 = ( \
     
    7879}
    7980
    80 #define Clock_driver_nanoseconds_since_last_tick bsp_clock_nanoseconds_since_last_tick
     81#define Clock_driver_nanoseconds_since_last_tick \
     82    bsp_clock_nanoseconds_since_last_tick
    8183
    8284#include "../../../shared/clockdrv_shell.h"
  • c/src/lib/libbsp/sparc/leon2/configure.ac

    r97d0b9b r363b1f7  
    22
    33AC_PREREQ([2.69])
    4 AC_INIT([rtems-c-src-lib-libbsp-sparc-leon2],[_RTEMS_VERSION],[http://www.rtems.org/bugzilla])
     4AC_INIT([rtems-c-src-lib-libbsp-sparc-leon2],
     5[_RTEMS_VERSION],[http://www.rtems.org/bugzilla])
    56AC_CONFIG_SRCDIR([bsp_specs])
    67RTEMS_TOP(../../../../../..)
     
    2425RTEMS_BSPOPTS_HELP([CONSOLE_USE_INTERRUPTS],
    2526[The leon2 console driver can operate in either polled or interrupt mode.
    26 Under the simulator (especially when FAST_UART is defined), polled seems to operate
    27 better.  It is common for a task to print a line (like the end of test message) and
    28 then exit.  In this case, the program returns control to the simulator command line
    29 before the program has even queued the output to the uart.  Thus sis has no chance
    30 of getting the data out.])
     27Under the simulator (especially when FAST_UART is defined), polled seems
     28to operate better. It is common for a task to print a line (like the end
     29of test message) and then exit.  In this case, the program returns control
     30to the simulator command line before the program has even queued the output
     31to the uart.  Thus sis has no chance of getting the data out.])
    3132
    3233RTEMS_BSPOPTS_SET([SIMSPARC_FAST_IDLE],[*],[])
  • c/src/lib/libbsp/sparc/leon2/include/bsp.h

    r97d0b9b r363b1f7  
    120120/* Allocate 8-byte aligned non-freeable pre-malloc() memory. The function
    121121 * can be called at any time. The work-area will shrink when called before
    122  * bsp_work_area_initialize(). malloc() is called to get memory when this function
    123  * is called after bsp_work_area_initialize().
     122 * bsp_work_area_initialize(). malloc() is called to get memory when this
     123 * function is called after bsp_work_area_initialize().
    124124 */
    125125void *bsp_early_malloc(int size);
  • c/src/lib/libbsp/sparc/leon2/include/leon.h

    r97d0b9b r363b1f7  
    225225
    226226#define LEON_REG_TIMER_CONTROL_EN    0x00000001  /* 1 = enable counting */
    227                                                  /* 0 = hold scalar and counter */
     227                                              /* 0 = hold scalar and counter */
    228228#define LEON_REG_TIMER_CONTROL_RL    0x00000002  /* 1 = reload at 0 */
    229                                                  /* 0 = stop at 0 */
     229                                              /* 0 = stop at 0 */
    230230#define LEON_REG_TIMER_CONTROL_LD    0x00000004  /* 1 = load counter */
    231                                                  /* 0 = no function */
     231                                              /* 0 = no function */
    232232
    233233/*
  • c/src/lib/libbsp/sparc/leon2/include/rasta.h

    r97d0b9b r363b1f7  
    8989
    9090void uart_register(unsigned int baseaddr);
    91 rtems_device_driver uart_initialize(rtems_device_major_number  major, rtems_device_minor_number  minor, void *arg);
    92 rtems_device_driver uart_open(rtems_device_major_number major, rtems_device_minor_number minor, void *arg);
    93 rtems_device_driver uart_close(rtems_device_major_number major, rtems_device_minor_number minor, void *arg);
    94 rtems_device_driver uart_read(rtems_device_major_number major, rtems_device_minor_number minor, void *arg);
    95 rtems_device_driver uart_write(rtems_device_major_number major, rtems_device_minor_number minor, void *arg);
    96 rtems_device_driver uart_control(rtems_device_major_number major, rtems_device_minor_number minor, void *arg);
     91rtems_device_driver uart_initialize(rtems_device_major_number  major,
     92                rtems_device_minor_number  minor, void *arg);
     93rtems_device_driver uart_open(rtems_device_major_number major,
     94                rtems_device_minor_number minor, void *arg);
     95rtems_device_driver uart_close(rtems_device_major_number major,
     96                rtems_device_minor_number minor, void *arg);
     97rtems_device_driver uart_read(rtems_device_major_number major,
     98                rtems_device_minor_number minor, void *arg);
     99rtems_device_driver uart_write(rtems_device_major_number major,
     100                rtems_device_minor_number minor, void *arg);
     101rtems_device_driver uart_control(rtems_device_major_number major,
     102                rtems_device_minor_number minor, void *arg);
    97103
    98104
  • c/src/lib/libbsp/sparc/leon2/pci/pci.c

    r97d0b9b r363b1f7  
    4545/* allow for overriding these definitions */
    4646#ifndef PCI_CONFIG_ADDR
    47 #define PCI_CONFIG_ADDR                 0xcf8
     47#define PCI_CONFIG_ADDR      0xcf8
    4848#endif
    4949#ifndef PCI_CONFIG_DATA
    50 #define PCI_CONFIG_DATA                 0xcfc
     50#define PCI_CONFIG_DATA      0xcfc
    5151#endif
    5252
    5353/* define a shortcut */
    54 #define pci     BSP_pci_configuration
     54#define pci  BSP_pci_configuration
    5555
    5656/*
     
    6060
    6161typedef struct {
    62     volatile unsigned int pciid1;        /* 0x80000100 - PCI Device identification register 1         */
    63     volatile unsigned int pcisc;         /* 0x80000104 - PCI Status & Command                         */
    64     volatile unsigned int pciid2;        /* 0x80000108 - PCI Device identification register 2         */
    65     volatile unsigned int pcibhlc;       /* 0x8000010c - BIST, Header type, Cache line size register  */
    66     volatile unsigned int mbar1;         /* 0x80000110 - Memory Base Address Register 1               */
    67     volatile unsigned int mbar2;         /* 0x80000114 - Memory Base Address Register 2               */
    68     volatile unsigned int iobar3;        /* 0x80000118 - IO Base Address Register 3                   */
    69     volatile unsigned int dummy1[4];     /* 0x8000011c - 0x80000128                                   */
    70     volatile unsigned int pcisid;        /* 0x8000012c - Subsystem identification register            */
    71     volatile unsigned int dummy2;        /* 0x80000130                                                */
    72     volatile unsigned int pcicp;         /* 0x80000134 - PCI capabilities pointer register            */
    73     volatile unsigned int dummy3;        /* 0x80000138                                                */
    74     volatile unsigned int pcili;         /* 0x8000013c - PCI latency interrupt register               */
    75     volatile unsigned int pcirt;         /* 0x80000140 - PCI retry, trdy config                       */
    76     volatile unsigned int pcicw;         /* 0x80000144 - PCI configuration write register             */
    77     volatile unsigned int pcisa;         /* 0x80000148 - PCI Initiator Start Address                  */
    78     volatile unsigned int pciiw;         /* 0x8000014c - PCI Initiator Write Register                 */
    79     volatile unsigned int pcidma;        /* 0x80000150 - PCI DMA configuration register               */
    80     volatile unsigned int pciis;         /* 0x80000154 - PCI Initiator Status Register                */
    81     volatile unsigned int pciic;         /* 0x80000158 - PCI Initiator Configuration                  */
    82     volatile unsigned int pcitpa;        /* 0x8000015c - PCI Target Page Address Register             */
    83     volatile unsigned int pcitsc;        /* 0x80000160 - PCI Target Status-Command Register           */
    84     volatile unsigned int pciite;        /* 0x80000164 - PCI Interrupt Enable Register                */
    85     volatile unsigned int pciitp;        /* 0x80000168 - PCI Interrupt Pending Register               */
    86     volatile unsigned int pciitf;        /* 0x8000016c - PCI Interrupt Force Register                 */
    87     volatile unsigned int pcid;          /* 0x80000170 - PCI Data Register                            */
    88     volatile unsigned int pcibe;         /* 0x80000174 - PCI Burst End Register                       */
    89     volatile unsigned int pcidmaa;       /* 0x80000178 - PCI DMA Address Register                     */
     62  /* 0x80000100 - PCI Device identification register 1         */
     63    volatile unsigned int pciid1;
     64    /* 0x80000104 - PCI Status & Command                         */
     65    volatile unsigned int pcisc;
     66    /* 0x80000108 - PCI Device identification register 2         */
     67    volatile unsigned int pciid2;
     68    /* 0x8000010c - BIST, Header type, Cache line size register  */
     69    volatile unsigned int pcibhlc;
     70    /* 0x80000110 - Memory Base Address Register 1               */
     71    volatile unsigned int mbar1;
     72    /* 0x80000114 - Memory Base Address Register 2               */
     73    volatile unsigned int mbar2;
     74    /* 0x80000118 - IO Base Address Register 3                   */
     75    volatile unsigned int iobar3;
     76    /* 0x8000011c - 0x80000128                                   */
     77    volatile unsigned int dummy1[4];
     78    /* 0x8000012c - Subsystem identification register            */
     79    volatile unsigned int pcisid;
     80    /* 0x80000130                                                */
     81    volatile unsigned int dummy2;
     82    /* 0x80000134 - PCI capabilities pointer register            */
     83    volatile unsigned int pcicp;
     84    /* 0x80000138                                                */
     85    volatile unsigned int dummy3;
     86    /* 0x8000013c - PCI latency interrupt register               */
     87    volatile unsigned int pcili;
     88    /* 0x80000140 - PCI retry, trdy config                       */
     89    volatile unsigned int pcirt;
     90    /* 0x80000144 - PCI configuration write register             */
     91    volatile unsigned int pcicw;
     92    /* 0x80000148 - PCI Initiator Start Address                  */
     93    volatile unsigned int pcisa;
     94    /* 0x8000014c - PCI Initiator Write Register                 */
     95    volatile unsigned int pciiw;
     96    /* 0x80000150 - PCI DMA configuration register               */
     97    volatile unsigned int pcidma;
     98    /* 0x80000154 - PCI Initiator Status Register                */
     99    volatile unsigned int pciis;
     100    /* 0x80000158 - PCI Initiator Configuration                  */
     101    volatile unsigned int pciic;
     102    /* 0x8000015c - PCI Target Page Address Register             */
     103    volatile unsigned int pcitpa;
     104    /* 0x80000160 - PCI Target Status-Command Register           */
     105    volatile unsigned int pcitsc;
     106    /* 0x80000164 - PCI Interrupt Enable Register                */
     107    volatile unsigned int pciite;
     108    /* 0x80000168 - PCI Interrupt Pending Register               */
     109    volatile unsigned int pciitp;
     110    /* 0x8000016c - PCI Interrupt Force Register                 */
     111    volatile unsigned int pciitf;
     112    /* 0x80000170 - PCI Data Register                            */
     113    volatile unsigned int pcid;
     114    /* 0x80000174 - PCI Burst End Register                       */
     115    volatile unsigned int pcibe;
     116    /* 0x80000178 - PCI DMA Address Register                     */
     117    volatile unsigned int pcidmaa;
    90118} AT697_PCI_Map;
    91119
     
    108136
    109137static int
    110 BSP_pci_read_config_dword(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned int *val) {
     138BSP_pci_read_config_dword(unsigned char bus, unsigned char slot,
     139    unsigned char function, unsigned char offset, unsigned int *val) {
    111140
    112141    volatile unsigned int data;
     
    132161        *val = data;
    133162
    134     DBG("pci_read - bus: %d, dev: %d, fn: %d, off: %d => addr: %x, val: %x\n", bus, slot, function, offset,  (1<<(11+slot) ) | ((function & 7)<<8) |  (offset&0x3f), *val);
     163    DBG("pci_read - bus: %d, dev: %d, fn: %d, off: %d => addr: %x, val: %x\n",
     164        bus, slot, function, offset,
     165        (1<<(11+slot) ) | ((function & 7)<<8) |  (offset&0x3f), *val);
    135166
    136167    return PCIBIOS_SUCCESSFUL;
     
    139170
    140171static int
    141 BSP_pci_read_config_word(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned short *val) {
     172BSP_pci_read_config_word(unsigned char bus, unsigned char slot,
     173    unsigned char function, unsigned char offset, unsigned short *val) {
    142174    unsigned int v;
    143175
     
    152184
    153185static int
    154 BSP_pci_read_config_byte(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned char *val) {
     186BSP_pci_read_config_byte(unsigned char bus, unsigned char slot,
     187    unsigned char function, unsigned char offset, unsigned char *val) {
    155188    unsigned int v;
    156189
     
    164197
    165198static int
    166 BSP_pci_write_config_dword(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned int val) {
     199BSP_pci_write_config_dword(unsigned char bus, unsigned char slot,
     200    unsigned char function, unsigned char offset, unsigned int val) {
    167201
    168202    if (offset & 3) return PCIBIOS_BAD_REGISTER_NUMBER;
     
    183217    pcic->pciitp = 0xff; /* clear interrupts */
    184218
    185 /*    DBG("pci write - bus: %d, dev: %d, fn: %d, off: %d => addr: %x, val: %x\n", bus, slot, function, offset, (1<<(11+slot) ) | ((function & 7)<<8) |  (offset&0x3f), val); */
     219/*  DBG("pci write - bus: %d, dev: %d, fn: %d, off: %d => addr: %x, val: %x\n",
     220    bus, slot, function, offset,
     221    (1<<(11+slot) ) | ((function & 7)<<8) |  (offset&0x3f), val); */
    186222
    187223    return PCIBIOS_SUCCESSFUL;
     
    190226
    191227static int
    192 BSP_pci_write_config_word(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned short val) {
     228BSP_pci_write_config_word(unsigned char bus, unsigned char slot,
     229    unsigned char function, unsigned char offset, unsigned short val) {
    193230    unsigned int v;
    194231
     
    204241
    205242static int
    206 BSP_pci_write_config_byte(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned char val) {
     243BSP_pci_write_config_byte(unsigned char bus, unsigned char slot,
     244    unsigned char function, unsigned char offset, unsigned char val) {
    207245    unsigned int v;
    208246
     
    237275    pcic->pciic = 0xffffffff;
    238276
    239     /* Map system RAM at pci address 0x40000000 and system SDRAM to pci address 0x60000000  */
     277    /* Map system RAM at pci address 0x40000000
     278       and system SDRAM to pci address 0x60000000  */
    240279    pcic->mbar1  = 0x40000000;
    241280    pcic->mbar2  = 0x60000000;
     
    248287    pcic->pcibhlc = 0x00004000;
    249288
    250     /* Set Inititator configuration so that AHB slave accesses generate memory read/write commands */
     289    /* Set Inititator configuration so that AHB slave accesses
     290       generate memory read/write commands */
    251291    pcic->pciic = 0x41;
    252292
     
    384424}
    385425
    386 void pci_mem_enable(unsigned char bus, unsigned char slot, unsigned char function) {
     426void pci_mem_enable(unsigned char bus, unsigned char slot,
     427    unsigned char function) {
    387428    unsigned int data;
    388429
    389430    pci_read_config_dword(0, slot, function, PCI_COMMAND, &data);
    390     pci_write_config_dword(0, slot, function, PCI_COMMAND, data | PCI_COMMAND_MEMORY);
    391 
    392 }
    393 
    394 void pci_master_enable(unsigned char bus, unsigned char slot, unsigned char function) {
     431    pci_write_config_dword(0, slot, function, PCI_COMMAND,
     432        data | PCI_COMMAND_MEMORY);
     433
     434}
     435
     436void pci_master_enable(unsigned char bus, unsigned char slot,
     437    unsigned char function) {
    395438    unsigned int data;
    396439
    397440    pci_read_config_dword(0, slot, function, PCI_COMMAND, &data);
    398     pci_write_config_dword(0, slot, function, PCI_COMMAND, data | PCI_COMMAND_MASTER);
     441    pci_write_config_dword(0, slot, function, PCI_COMMAND,
     442        data | PCI_COMMAND_MASTER);
    399443
    400444}
     
    410454/* pci_allocate_resources
    411455 *
    412  * This function scans the bus and assigns PCI addresses to all devices. It handles both
    413  * single function and multi function devices. All allocated devices are enabled and
    414  * latency timers are set to 40.
    415  *
    416  * NOTE that it only allocates PCI memory space devices. IO spaces are not enabled.
    417  * Also, it does not handle pci-pci bridges. They are left disabled.
    418  *
    419  *
    420 */
     456 * This function scans the bus and assigns PCI addresses to all devices. It
     457 * handles both single function and multi function devices. All allocated
     458 * devices are enabled and latency timers are set to 40.
     459 *
     460 * NOTE that it only allocates PCI memory space devices. IO spaces are
     461 * not enabled. Also, it does not handle pci-pci bridges. They are left
     462 * disabled.
     463 *
     464 */
    421465static void pci_allocate_resources(void) {
    422466
    423     unsigned int slot, numfuncs, func, id, pos, size, tmp, i, swapped, addr, dev, fn;
     467    unsigned int slot, numfuncs, func, id, pos, size, tmp;
     468    unsigned int i, swapped, addr, dev, fn;
    424469    unsigned char header;
    425470    struct pci_res **res;
     
    446491        pci_read_config_byte(0, slot, 0, PCI_HEADER_TYPE, &header);
    447492
    448         if(header & PCI_HEADER_TYPE_MULTI_FUNCTION)     {
     493        if(header & PCI_HEADER_TYPE_MULTI_FUNCTION)  {
    449494            numfuncs = PCI_MAX_FUNCTIONS;
    450495        }
     
    467512
    468513            for (pos = 0; pos < 6; pos++) {
    469                 pci_write_config_dword(0, slot, func, PCI_BASE_ADDRESS_0 + (pos<<2), 0xffffffff);
    470                 pci_read_config_dword(0, slot, func, PCI_BASE_ADDRESS_0 + (pos<<2), &size);
     514                pci_write_config_dword(0, slot, func,
     515                    PCI_BASE_ADDRESS_0 + (pos<<2), 0xffffffff);
     516                pci_read_config_dword(0, slot, func,
     517                    PCI_BASE_ADDRESS_0 + (pos<<2), &size);
    471518
    472519                if (size == 0 || size == 0xffffffff || (size & 0xff) != 0) {
    473                     pci_write_config_dword(0, slot, func, PCI_BASE_ADDRESS_0 + (pos<<2), 0);
     520                    pci_write_config_dword(0, slot, func,
     521                        PCI_BASE_ADDRESS_0 + (pos<<2), 0);
    474522                    continue;
    475523                }
     
    480528                    res[slot*8*6+func*6+pos]->bar   = pos;
    481529
    482                     DBG("Slot: %d, function: %d, bar%d size: %x\n", slot, func, pos, ~size+1);
     530                    DBG("Slot: %d, function: %d, bar%d size: %x\n",
     531                        slot, func, pos, ~size+1);
    483532                }
    484533            }
     
    517566        fn  = res[i]->devfn & 7;
    518567
    519         DBG("Assigning PCI addr %x to device %d, function %d, bar %d\n", addr, dev, fn, res[i]->bar);
    520         pci_write_config_dword(0, dev, fn, PCI_BASE_ADDRESS_0+res[i]->bar*4, addr);
     568        DBG("Assigning PCI addr %x to device %d, function %d, bar %d\n",
     569            addr, dev, fn, res[i]->bar);
     570        pci_write_config_dword(0, dev, fn,
     571            PCI_BASE_ADDRESS_0+res[i]->bar*4, addr);
    521572        addr += res[i]->size;
    522573
     
    539590        pci_read_config_byte(0, slot, 0, PCI_HEADER_TYPE, &header);
    540591
    541         if(header & PCI_HEADER_TYPE_MULTI_FUNCTION)     {
     592        if(header & PCI_HEADER_TYPE_MULTI_FUNCTION)  {
    542593            numfuncs = PCI_MAX_FUNCTIONS;
    543594        }
     
    556607                if (id == PCI_INVALID_VENDORDEVICEID || id == 0) continue;
    557608
    558                 printk("\nSlot %d function: %d\nVendor id: 0x%x, device id: 0x%x\n", slot, func, id & 0xffff, id>>16);
     609                printk("\nSlot %d function: %d\nVendor id: 0x%x, "
     610                    "device id: 0x%x\n", slot, func, id & 0xffff, id>>16);
    559611
    560612                for (pos = 0; pos < 6; pos++) {
    561                     pci_read_config_dword(0, slot, func, PCI_BASE_ADDRESS_0 + pos*4, &tmp);
     613                    pci_read_config_dword(0, slot, func,
     614                        PCI_BASE_ADDRESS_0 + pos*4, &tmp);
    562615
    563616                    if (tmp != 0 && tmp != 0xffffffff && (tmp & 0xff) == 0) {
     
    621674                                   PCI_HEADER_TYPE,
    622675                                   &ucHeader);
    623         if(ucHeader&PCI_HEADER_TYPE_MULTI_FUNCTION)     {
     676        if(ucHeader&PCI_HEADER_TYPE_MULTI_FUNCTION)  {
    624677            ucNumFuncs=PCI_MAX_FUNCTIONS;
    625678        }
  • c/src/lib/libbsp/sparc/leon2/rasta/rasta.c

    r97d0b9b r363b1f7  
    5858/* static rtems_isr pci_interrupt_handler (rtems_vector_number v) { */
    5959
    60 /*     volatile unsigned int *pci_int = (volatile unsigned int *) 0x80000168; */
    61 /*     volatile unsigned int *pci_mem = (volatile unsigned int *) 0xb0400000; */
     60/*     volatile unsigned int *pci_int = (volatile unsigned int *) 0x80000168;*/
     61/*     volatile unsigned int *pci_mem = (volatile unsigned int *) 0xb0400000;*/
    6262
    6363/*     if (*pci_int & 0x20) { */
     
    244244
    245245    /* Search old PCI vendor/device id. */
    246     if ( (!found) && (BSP_pciFindDevice(0x16E3, 0x0210, 0, &bus, &dev, &fun) == 0) ) {
     246    if ( (!found) &&
     247            (BSP_pciFindDevice(0x16E3, 0x0210, 0, &bus, &dev, &fun) == 0) ) {
    247248      found = 1;
    248249    }
     
    258259
    259260    page0 = (unsigned int *)(bar0 + 0x400000);
    260     *page0 = 0x80000000;                  /* Point PAGE0 to start of APB       */
     261    *page0 = 0x80000000;                  /* Point PAGE0 to start of APB     */
    261262
    262263    apb_base = (unsigned int *)(bar0+APB2_OFFSET);
     
    280281    irq->iclear = 0xffff;
    281282    irq->ilevel = 0;
    282     irq->mask[0] = 0xffff & ~(UART0_IRQ|UART1_IRQ|SPW0_IRQ|SPW1_IRQ|SPW2_IRQ|GRCAN_IRQ|BRM_IRQ);
     283    irq->mask[0] = 0xffff &
     284           ~(UART0_IRQ|UART1_IRQ|SPW0_IRQ|SPW1_IRQ|SPW2_IRQ|GRCAN_IRQ|BRM_IRQ);
    283285
    284286    /* Configure AT697 ioport bit 7 to input pci irq */
  • c/src/lib/libbsp/sparc/leon3/Makefile.am

    r97d0b9b r363b1f7  
    3636    ../../shared/bsppost.c ../../shared/bootcard.c startup/bspstart.c \
    3737    ../../sparc/shared/bsppretaskinghook.c startup/bsppredriver.c \
    38     ../../sparc/shared/startup/bspgetworkarea.c ../../shared/sbrk.c startup/setvec.c \
     38    ../../sparc/shared/startup/bspgetworkarea.c ../../shared/sbrk.c \
     39    startup/setvec.c \
    3940    startup/spurious.c startup/bspidle.S startup/bspdelay.c \
    4041    ../../shared/bspinit.c ../../sparc/shared/startup/early_malloc.c
  • c/src/lib/libbsp/sparc/leon3/configure.ac

    r97d0b9b r363b1f7  
    22
    33AC_PREREQ([2.69])
    4 AC_INIT([rtems-c-src-lib-libbsp-sparc-leon3],[_RTEMS_VERSION],[http://www.rtems.org/bugzilla])
     4AC_INIT([rtems-c-src-lib-libbsp-sparc-leon3],
     5[_RTEMS_VERSION],[http://www.rtems.org/bugzilla])
    56AC_CONFIG_SRCDIR([bsp_specs])
    67RTEMS_TOP(../../../../../..)
     
    2425RTEMS_BSPOPTS_HELP([CONSOLE_USE_INTERRUPTS],
    2526[The leon3 console driver can operate in either polled or interrupt mode.
    26 Under the simulator (especially when FAST_UART is defined), polled seems to operate
    27 better.])
     27Under the simulator (especially when FAST_UART is defined), polled seems
     28to operate better.])
    2829
    2930RTEMS_BSPOPTS_SET([SIMSPARC_FAST_IDLE],[*],[])
  • c/src/lib/libbsp/sparc/leon3/include/bsp.h

    r97d0b9b r363b1f7  
    8181
    8282#define RTEMS_BSP_NETWORK_DRIVER_NAME_OPENETH   "open_eth1"
    83 #define RTEMS_BSP_NETWORK_DRIVER_ATTACH_OPENETH  rtems_leon_open_eth_driver_attach
     83#define RTEMS_BSP_NETWORK_DRIVER_ATTACH_OPENETH  \
     84    rtems_leon_open_eth_driver_attach
    8485#define RTEMS_BSP_NETWORK_DRIVER_NAME_SMC91111  "smc_eth1"
    85 #define RTEMS_BSP_NETWORK_DRIVER_ATTACH_SMC91111 rtems_smc91111_driver_attach_leon3
     86#define RTEMS_BSP_NETWORK_DRIVER_ATTACH_SMC91111 \
     87    rtems_smc91111_driver_attach_leon3
    8688#define RTEMS_BSP_NETWORK_DRIVER_NAME_GRETH      "gr_eth1"
    87 #define RTEMS_BSP_NETWORK_DRIVER_ATTACH_GRETH    rtems_leon_greth_driver_attach
     89#define RTEMS_BSP_NETWORK_DRIVER_ATTACH_GRETH \
     90    rtems_leon_greth_driver_attach
    8891
    8992#ifndef RTEMS_BSP_NETWORK_DRIVER_NAME
     
    132135/* Allocate 8-byte aligned non-freeable pre-malloc() memory. The function
    133136 * can be called at any time. The work-area will shrink when called before
    134  * bsp_work_area_initialize(). malloc() is called to get memory when this function
    135  * is called after bsp_work_area_initialize().
     137 * bsp_work_area_initialize(). malloc() is called to get memory when this
     138 * function is called after bsp_work_area_initialize().
    136139 */
    137140void *bsp_early_malloc(int size);
  • c/src/lib/libbsp/sparc/leon3/include/leon.h

    r97d0b9b r363b1f7  
    8181
    8282#define LEON_REG_TIMER_CONTROL_EN    0x00000001  /* 1 = enable counting */
    83                                                  /* 0 = hold scalar and counter */
     83                                              /* 0 = hold scalar and counter */
    8484#define LEON_REG_TIMER_CONTROL_RL    0x00000002  /* 1 = reload at 0 */
    85                                                  /* 0 = stop at 0 */
     85                                              /* 0 = stop at 0 */
    8686#define LEON_REG_TIMER_CONTROL_LD    0x00000004  /* 1 = load counter */
    87                                                  /* 0 = no function */
     87                                              /* 0 = no function */
    8888
    8989/*
     
    120120#define LEON_REG_UART_CTRL_LB     0x00000080 /* Loop Back enable */
    121121
    122 extern volatile struct irqmp_regs *LEON3_IrqCtrl_Regs;  /* LEON3 Interrupt Controller */
    123 extern volatile struct gptimer_regs *LEON3_Timer_Regs; /* LEON3 GP Timer */
     122/* LEON3 Interrupt Controller */
     123extern volatile struct irqmp_regs *LEON3_IrqCtrl_Regs;
     124/* LEON3 GP Timer */
     125extern volatile struct gptimer_regs *LEON3_Timer_Regs;
    124126
    125127/* LEON3 CPU Index of boot CPU */
     
    271273#if defined(RTEMS_MULTIPROCESSING)
    272274  #define LEON3_CLOCK_INDEX \
    273     (rtems_configuration_get_user_multiprocessing_table() ? LEON3_Cpu_Index : 0)
     275   (rtems_configuration_get_user_multiprocessing_table() ? LEON3_Cpu_Index : 0)
    274276#else
    275277  #define LEON3_CLOCK_INDEX 0
  • c/src/lib/libbsp/sparc/leon3/leon_smc91111/leon_smc91111.c

    r97d0b9b r363b1f7  
    7575
    7676  /* Setup memory controller I/O waitstates */
    77   *((volatile unsigned int *) addr_mctrl) |= 0x10f80000;        /* enable I/O area access */
     77  *((volatile unsigned int *) addr_mctrl) |=
     78                  0x10f80000;   /* enable I/O area access */
    7879
    7980  return _rtems_smc91111_driver_attach(config, &leon_scmv91111_configuration);
  • c/src/lib/libbsp/sparc/leon3/pci/pci.c

    r97d0b9b r363b1f7  
    5050/* allow for overriding these definitions */
    5151#ifndef PCI_CONFIG_ADDR
    52 #define PCI_CONFIG_ADDR                 0xcf8
     52#define PCI_CONFIG_ADDR      0xcf8
    5353#endif
    5454#ifndef PCI_CONFIG_DATA
    55 #define PCI_CONFIG_DATA                 0xcfc
     55#define PCI_CONFIG_DATA      0xcfc
    5656#endif
    5757
    5858/* define a shortcut */
    59 #define pci     BSP_pci_configuration
     59#define pci  BSP_pci_configuration
    6060
    6161/*
     
    6464unsigned char ucMaxPCIBus;
    6565typedef struct {
    66         volatile unsigned int cfg_stat;
    67         volatile unsigned int bar0;
    68         volatile unsigned int page0;
    69         volatile unsigned int bar1;
    70         volatile unsigned int page1;
    71         volatile unsigned int iomap;
    72         volatile unsigned int stat_cmd;
     66  volatile unsigned int cfg_stat;
     67  volatile unsigned int bar0;
     68  volatile unsigned int page0;
     69  volatile unsigned int bar1;
     70  volatile unsigned int page1;
     71  volatile unsigned int iomap;
     72  volatile unsigned int stat_cmd;
    7373} LEON3_GRPCI_Regs_Map;
    7474
     
    8484static inline unsigned int flip_dword (unsigned int l)
    8585{
    86         return ((l&0xff)<<24) | (((l>>8)&0xff)<<16) | (((l>>16)&0xff)<<8)| ((l>>24)&0xff);
     86        return ((l&0xff)<<24) | (((l>>8)&0xff)<<16) |
     87                (((l>>16)&0xff)<<8)| ((l>>24)&0xff);
    8788}
    8889
     
    124125    }
    125126
    126    DBG("pci_read - bus: %d, dev: %d, fn: %d, off: %d => addr: %x, val: %x\n", bus, slot, function, offset,  (1<<(11+slot) ) | ((function & 7)<<8) |  (offset&0x3f), *val);
     127   DBG("pci_read - bus: %d, dev: %d, fn: %d, off: %d => addr: %x, val: %x\n",
     128       bus, slot, function, offset,
     129       (1<<(11+slot) ) | ((function & 7)<<8) |  (offset&0x3f), *val);
    127130
    128131    return PCIBIOS_SUCCESSFUL;
     
    131134
    132135static int
    133 BSP_pci_read_config_word(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned short *val) {
     136BSP_pci_read_config_word(unsigned char bus, unsigned char slot,
     137    unsigned char function, unsigned char offset, unsigned short *val) {
    134138    uint32_t v;
    135139
     
    144148
    145149static int
    146 BSP_pci_read_config_byte(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned char *val) {
     150BSP_pci_read_config_byte(unsigned char bus, unsigned char slot,
     151    unsigned char function, unsigned char offset, unsigned char *val) {
    147152    uint32_t v;
    148153
     
    156161
    157162static int
    158 BSP_pci_write_config_dword(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, uint32_t val) {
     163BSP_pci_write_config_dword(unsigned char bus, unsigned char slot,
     164    unsigned char function, unsigned char offset, uint32_t val) {
    159165
    160166    volatile unsigned int *pci_conf;
     
    175181    *pci_conf = value;
    176182
    177     DBG("pci write - bus: %d, dev: %d, fn: %d, off: %d => addr: %x, val: %x\n", bus, slot, function, offset, (1<<(11+slot) ) | ((function & 7)<<8) |  (offset&0x3f), value);
     183    DBG("pci write - bus: %d, dev: %d, fn: %d, off: %d => addr: %x, val: %x\n",
     184        bus, slot, function, offset,
     185        (1<<(11+slot) ) | ((function & 7)<<8) |  (offset&0x3f), value);
    178186
    179187    return PCIBIOS_SUCCESSFUL;
     
    182190
    183191static int
    184 BSP_pci_write_config_word(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned short val) {
     192BSP_pci_write_config_word(unsigned char bus, unsigned char slot,
     193    unsigned char function, unsigned char offset, unsigned short val) {
    185194    uint32_t v;
    186195
     
    196205
    197206static int
    198 BSP_pci_write_config_byte(unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, unsigned char val) {
     207BSP_pci_write_config_byte(unsigned char bus, unsigned char slot,
     208    unsigned char function, unsigned char offset, unsigned char val) {
    199209    uint32_t v;
    200210
     
    235245    pci_write_config_dword(0,0,0,0x10, 0xffffffff);
    236246    pci_read_config_dword(0,0,0,0x10, &addr);
    237     pci_write_config_dword(0,0,0,0x10, flip_dword(0x10000000));    /* Setup bar0 to nonzero value (grpci considers BAR==0 as invalid) */
    238     addr = (~flip_dword(addr)+1)>>1;                               /* page0 is accessed through upper half of bar0 */
    239     pcic->cfg_stat |= 0x10000000;                                  /* Setup mmap reg so we can reach bar0 */
    240     page0[addr/4] = 0;                                             /* Disable bytetwisting ... */
     247    /* Setup bar0 to nonzero value (grpci considers BAR==0 as invalid) */
     248    pci_write_config_dword(0,0,0,0x10, flip_dword(0x10000000));
     249    /* page0 is accessed through upper half of bar0 */
     250    addr = (~flip_dword(addr)+1)>>1;
     251    /* Setup mmap reg so we can reach bar0 */
     252    pcic->cfg_stat |= 0x10000000;
     253    /* Disable bytetwisting ... */
     254    page0[addr/4] = 0;
    241255#endif
    242256
     
    256270
    257271/* DMA functions which uses GRPCIs optional DMA controller (len in words) */
    258 int dma_to_pci(unsigned int ahb_addr, unsigned int pci_addr, unsigned int len) {
     272int dma_to_pci(unsigned int ahb_addr, unsigned int pci_addr,
     273    unsigned int len) {
    259274    int ret = 0;
    260275
     
    277292}
    278293
    279 int dma_from_pci(unsigned int ahb_addr, unsigned int pci_addr, unsigned int len) {
     294int dma_from_pci(unsigned int ahb_addr, unsigned int pci_addr,
     295    unsigned int len) {
    280296    int ret = 0;
    281297
     
    299315
    300316
    301 void pci_mem_enable(unsigned char bus, unsigned char slot, unsigned char function) {
     317void pci_mem_enable(unsigned char bus, unsigned char slot,
     318    unsigned char function) {
    302319    uint32_t data;
    303320
    304321    pci_read_config_dword(0, slot, function, PCI_COMMAND, &data);
    305     pci_write_config_dword(0, slot, function, PCI_COMMAND, data | PCI_COMMAND_MEMORY);
    306 
    307 }
    308 
    309 void pci_master_enable(unsigned char bus, unsigned char slot, unsigned char function) {
     322    pci_write_config_dword(0, slot, function, PCI_COMMAND,
     323        data | PCI_COMMAND_MEMORY);
     324
     325}
     326
     327void pci_master_enable(unsigned char bus, unsigned char slot,
     328    unsigned char function) {
    310329    uint32_t data;
    311330
    312331    pci_read_config_dword(0, slot, function, PCI_COMMAND, &data);
    313     pci_write_config_dword(0, slot, function, PCI_COMMAND, data | PCI_COMMAND_MASTER);
     332    pci_write_config_dword(0, slot, function, PCI_COMMAND,
     333        data | PCI_COMMAND_MASTER);
    314334
    315335}
     
    325345/* pci_allocate_resources
    326346 *
    327  * This function scans the bus and assigns PCI addresses to all devices. It handles both
    328  * single function and multi function devices. All allocated devices are enabled and
    329  * latency timers are set to 40.
    330  *
    331  * NOTE that it only allocates PCI memory space devices (that are at least 1 KB).
    332  * IO spaces are not enabled. Also, it does not handle pci-pci bridges. They are left disabled.
    333  *
     347 * This function scans the bus and assigns PCI addresses to all devices.
     348 * It handles both single function and multi function devices. All
     349 * allocated devices are enabled and latency timers are set to 40.
     350 *
     351 * NOTE that it only allocates PCI memory space devices (that are at
     352 * least 1 KB). IO spaces are not enabled. Also, it does not handle
     353 * pci-pci bridges. They are left disabled.
    334354 *
    335355*/
     
    362382        pci_read_config_byte(0, slot, 0, PCI_HEADER_TYPE, &header);
    363383
    364         if(header & PCI_HEADER_TYPE_MULTI_FUNCTION)     {
     384        if(header & PCI_HEADER_TYPE_MULTI_FUNCTION)  {
    365385            numfuncs = PCI_MAX_FUNCTIONS;
    366386        }
     
    383403
    384404            for (pos = 0; pos < 6; pos++) {
    385                 pci_write_config_dword(0, slot, func, PCI_BASE_ADDRESS_0 + (pos<<2), 0xffffffff);
    386                 pci_read_config_dword(0, slot, func, PCI_BASE_ADDRESS_0 + (pos<<2), &size);
     405                pci_write_config_dword(0, slot, func,
     406                    PCI_BASE_ADDRESS_0 + (pos<<2), 0xffffffff);
     407                pci_read_config_dword(0, slot, func,
     408                    PCI_BASE_ADDRESS_0 + (pos<<2), &size);
    387409
    388410                if (size == 0 || size == 0xffffffff || (size & 0x3f1) != 0){
    389                     pci_write_config_dword(0, slot, func, PCI_BASE_ADDRESS_0 + (pos<<2), 0);
     411                    pci_write_config_dword(0, slot, func,
     412                        PCI_BASE_ADDRESS_0 + (pos<<2), 0);
    390413                    continue;
    391414
     
    396419                    res[slot*8*6+func*6+pos]->bar   = pos;
    397420
    398                     DBG("Slot: %d, function: %d, bar%d size: %x\n", slot, func, pos, ~size+1);
     421                    DBG("Slot: %d, function: %d, bar%d size: %x\n",
     422                        slot, func, pos, ~size+1);
    399423                }
    400424            }
     
    431455        fn  = res[i]->devfn & 7;
    432456
    433         DBG("Assigning PCI addr %x to device %d, function %d, bar %d\n", addr, dev, fn, res[i]->bar);
    434         pci_write_config_dword(0, dev, fn, PCI_BASE_ADDRESS_0+res[i]->bar*4, addr);
     457        DBG("Assigning PCI addr %x to device %d, function %d, bar %d\n",
     458            addr, dev, fn, res[i]->bar);
     459        pci_write_config_dword(0, dev, fn,
     460            PCI_BASE_ADDRESS_0+res[i]->bar*4, addr);
    435461        addr += res[i]->size;
    436462
     
    453479        pci_read_config_byte(0, slot, 0, PCI_HEADER_TYPE, &header);
    454480
    455         if(header & PCI_HEADER_TYPE_MULTI_FUNCTION)     {
     481        if(header & PCI_HEADER_TYPE_MULTI_FUNCTION)  {
    456482            numfuncs = PCI_MAX_FUNCTIONS;
    457483        }
     
    470496                if (id == PCI_INVALID_VENDORDEVICEID || id == 0) continue;
    471497
    472                 printk("\nSlot %d function: %d\nVendor id: 0x%x, device id: 0x%x\n", slot, func, id & 0xffff, id>>16);
     498                printk("\nSlot %d function: %d\nVendor id: 0x%x, "
     499                    "device id: 0x%x\n", slot, func, id & 0xffff, id>>16);
    473500
    474501                for (pos = 0; pos < 6; pos++) {
    475                     pci_read_config_dword(0, slot, func, PCI_BASE_ADDRESS_0 + pos*4, &tmp);
     502                    pci_read_config_dword(0, slot, func,
     503                        PCI_BASE_ADDRESS_0 + pos*4, &tmp);
    476504
    477505                    if (tmp != 0 && tmp != 0xffffffff && (tmp & 0x3f1) == 0) {
     
    531559                                   PCI_HEADER_TYPE,
    532560                                   &ucHeader);
    533         if(ucHeader&PCI_HEADER_TYPE_MULTI_FUNCTION)     {
     561        if(ucHeader&PCI_HEADER_TYPE_MULTI_FUNCTION)  {
    534562            ucNumFuncs=PCI_MAX_FUNCTIONS;
    535563        }
  • c/src/lib/libbsp/sparc/leon3/shmsupp/getcfg.c

    r97d0b9b r363b1f7  
    7373  int i;
    7474  unsigned int tmp;
     75  rtems_multiprocessing_table *mptable;
    7576
    7677  BSP_shm_cfgtbl.format       = SHM_BIG;
     
    9899  if (LEON3_Cpu_Index == 0) {
    99100    tmp = 0;
    100     for (i = 1;
    101          i < (rtems_configuration_get_user_multiprocessing_table())->maximum_nodes; i++)
     101    mptable = rtems_configuration_get_user_multiprocessing_table();
     102    for (i = 1; i < mptable->maximum_nodes; i++)
    102103      tmp |= (1 << i);
    103104    LEON3_IrqCtrl_Regs->mpstat = tmp;
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