Changeset 35f97010 in rtems
- Timestamp:
- 03/31/04 02:02:23 (20 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- 66c373bf
- Parents:
- e96a950b
- Location:
- c/src/lib/libcpu/mips
- Files:
-
- 11 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libcpu/mips/ChangeLog
re96a950b r35f97010 1 2004-03-30 Ralf Corsepius <ralf_corsepius@rtems.org> 2 3 * clock/ckinit.c, clock/clock.h, mongoosev/duart/mg5uart.c, 4 mongoosev/duart/mg5uart.h, mongoosev/duart/mg5uart_reg.c, 5 mongoosev/include/mongoose-v.h, mongoosev/vectorisrs/vectorisrs.c, 6 shared/interrupts/vectorexceptions.c, timer/timer.c, 7 tx39/include/tx3904.h: Convert to using c99 fixed size types. 8 1 9 2004-03-26 Ralf Corsepius <ralf_corsepius@rtems.org> 2 10 -
c/src/lib/libcpu/mips/clock/ckinit.c
re96a950b r35f97010 75 75 */ 76 76 77 volatile rtems_unsigned32Clock_driver_ticks;77 volatile uint32_t Clock_driver_ticks; 78 78 79 79 /* … … 85 85 */ 86 86 87 rtems_unsigned32Clock_isrs; /* ISRs until next tick */87 uint32_t Clock_isrs; /* ISRs until next tick */ 88 88 89 89 /* … … 102 102 void Clock_exit( void ); 103 103 104 static u nsigned32mips_timer_rate = 0;104 static uint32_t mips_timer_rate = 0; 105 105 106 106 /* … … 218 218 ) 219 219 { 220 rtems_unsigned32isrlevel;220 uint32_t isrlevel; 221 221 rtems_libio_ioctl_args_t *args = pargp; 222 222 -
c/src/lib/libcpu/mips/clock/clock.h
re96a950b r35f97010 23 23 /* @(#)clock.h 08/20/96 1.2 */ 24 24 25 extern void mips_set_timer( u nsigned32timer_clock_interval );25 extern void mips_set_timer( uint32_t timer_clock_interval ); -
c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.c
re96a950b r35f97010 82 82 ) 83 83 { 84 u nsigned32pMG5UART_port;85 u nsigned32pMG5UART;86 u nsigned32cmd, cmdSave;87 u nsigned32baudcmd;88 u nsigned32shift;84 uint32_t pMG5UART_port; 85 uint32_t pMG5UART; 86 uint32_t cmd, cmdSave; 87 uint32_t baudcmd; 88 uint32_t shift; 89 89 rtems_interrupt_level Irql; 90 90 … … 221 221 MG5UART_STATIC void mg5uart_init(int minor) 222 222 { 223 u nsigned32pMG5UART_port;224 u nsigned32pMG5UART;225 u nsigned32cmdSave;226 u nsigned32shift;223 uint32_t pMG5UART_port; 224 uint32_t pMG5UART; 225 uint32_t cmdSave; 226 uint32_t shift; 227 227 228 228 mg5uart_context *pmg5uartContext; … … 270 270 ) 271 271 { 272 u nsigned32pMG5UART;273 u nsigned32pMG5UART_port;274 u nsigned32vector;275 u nsigned32cmd, cmdSave;276 u nsigned32baudcmd;277 u nsigned32shift;272 uint32_t pMG5UART; 273 uint32_t pMG5UART_port; 274 uint32_t vector; 275 uint32_t cmd, cmdSave; 276 uint32_t baudcmd; 277 uint32_t shift; 278 278 279 279 rtems_interrupt_level Irql; … … 327 327 ) 328 328 { 329 u nsigned32pMG5UART;330 u nsigned32pMG5UART_port;331 u nsigned32cmd, cmdSave;332 u nsigned32shift;329 uint32_t pMG5UART; 330 uint32_t pMG5UART_port; 331 uint32_t cmd, cmdSave; 332 uint32_t shift; 333 333 rtems_interrupt_level Irql; 334 334 … … 375 375 ) 376 376 { 377 u nsigned32pMG5UART;378 u nsigned32pMG5UART_port;379 u nsigned32status;377 uint32_t pMG5UART; 378 uint32_t pMG5UART_port; 379 uint32_t status; 380 380 int shift; 381 381 int timeout; … … 475 475 MG5UART_STATIC void mg5uart_process_isr_rx_error( 476 476 int minor, 477 u nsigned32mask478 ) 479 { 480 u nsigned32pMG5UART;477 uint32_t mask 478 ) 479 { 480 uint32_t pMG5UART; 481 481 int shift; 482 482 … … 520 520 MG5UART_STATIC void mg5uart_process_tx_isr( 521 521 int minor, 522 u nsigned32source523 ) 524 { 525 u nsigned32pMG5UART;522 uint32_t source 523 ) 524 { 525 uint32_t pMG5UART; 526 526 int shift; 527 527 … … 580 580 ) 581 581 { 582 u nsigned32pMG5UART_port;582 uint32_t pMG5UART_port; 583 583 unsigned char c; 584 584 … … 639 639 ) 640 640 { 641 u nsigned32Irql;642 u nsigned32pMG5UART_port;641 uint32_t Irql; 642 uint32_t pMG5UART_port; 643 643 644 644 pMG5UART_port = Console_Port_Tbl[minor].ulCtrlPort2; … … 713 713 ) 714 714 { 715 u nsigned32pMG5UART;716 u nsigned32pMG5UART_port;717 u nsigned32status;718 u nsigned32tmp,shift;715 uint32_t pMG5UART; 716 uint32_t pMG5UART_port; 717 uint32_t status; 718 uint32_t tmp,shift; 719 719 720 720 pMG5UART = Console_Port_Tbl[minor].ulCtrlPort1; … … 755 755 ) 756 756 { 757 rtems_unsigned32clock;758 rtems_unsigned32tmp_code;759 rtems_unsigned32baud_requested;757 uint32_t clock; 758 uint32_t tmp_code; 759 uint32_t baud_requested; 760 760 761 761 baud_requested = baud & CBAUD; … … 765 765 baud_requested = termios_baud_to_number( baud_requested ); 766 766 767 clock = ( rtems_unsigned32) Console_Port_Tbl[minor].ulClock;767 clock = (uint32_t ) Console_Port_Tbl[minor].ulClock; 768 768 if (!clock) 769 769 rtems_fatal_error_occurred(RTEMS_INVALID_NUMBER); … … 811 811 ) 812 812 { 813 u nsigned32pMG5UART;814 u nsigned32maskSave;815 u nsigned32shift;813 uint32_t pMG5UART; 814 uint32_t maskSave; 815 uint32_t shift; 816 816 rtems_interrupt_level Irql; 817 817 -
c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.h
re96a950b r35f97010 83 83 */ 84 84 85 u nsigned32mg5uart_get_register( /* registers are on 32-bit boundaries */86 u nsigned32ulCtrlPort, /* and accessed as word */87 u nsigned32ucRegNum85 uint32_t mg5uart_get_register( /* registers are on 32-bit boundaries */ 86 uint32_t ulCtrlPort, /* and accessed as word */ 87 uint32_t ucRegNum 88 88 ); 89 89 90 90 void mg5uart_set_register( 91 u nsigned32ulCtrlPort,92 u nsigned32ucRegNum,93 u nsigned32ucData91 uint32_t ulCtrlPort, 92 uint32_t ucRegNum, 93 uint32_t ucData 94 94 ); 95 95 -
c/src/lib/libcpu/mips/mongoosev/duart/mg5uart_reg.c
re96a950b r35f97010 3 3 * used with the mg5uart chip if accesses to the chip are as follows: 4 4 * 5 * + registers are accessed as u nsigned32's5 * + registers are accessed as uint32_t 's 6 6 * + registers are only u32-aligned (no address gaps) 7 7 * … … 21 21 #define _MG5UART_MULTIPLIER 1 22 22 #define _MG5UART_NAME(_X) _X 23 #define _MG5UART_TYPE u nsigned3223 #define _MG5UART_TYPE uint32_t 24 24 #endif 25 25 … … 31 31 */ 32 32 33 u nsigned8_MG5UART_NAME(mg5uart_get_register)(34 u nsigned32ulCtrlPort,35 u nsigned8ucRegNum33 uint8_t _MG5UART_NAME(mg5uart_get_register)( 34 uint32_t ulCtrlPort, 35 uint8_t ucRegNum 36 36 ) 37 37 { … … 48 48 49 49 void _MG5UART_NAME(mg5uart_set_register)( 50 u nsigned32ulCtrlPort,51 u nsigned8ucRegNum,52 u nsigned8ucData50 uint32_t ulCtrlPort, 51 uint8_t ucRegNum, 52 uint8_t ucData 53 53 ) 54 54 { -
c/src/lib/libcpu/mips/mongoosev/include/mongoose-v.h
re96a950b r35f97010 21 21 22 22 #define MONGOOSEV_READ( _base ) \ 23 ( *((volatile u nsigned32*)(_base)) )23 ( *((volatile uint32_t *)(_base)) ) 24 24 25 25 #define MONGOOSEV_WRITE( _base, _value ) \ 26 ( *((volatile u nsigned32*)(_base)) = (_value) )26 ( *((volatile uint32_t *)(_base)) = (_value) ) 27 27 28 28 #define MONGOOSEV_READ_REGISTER( _base, _register ) \ 29 ( *((volatile u nsigned32*)((_base) + (_register))) )29 ( *((volatile uint32_t *)((_base) + (_register))) ) 30 30 31 31 #define MONGOOSEV_WRITE_REGISTER( _base, _register, _value ) \ 32 ( *((volatile u nsigned32*)((_base) + (_register))) = (_value) )32 ( *((volatile uint32_t *)((_base) + (_register))) = (_value) ) 33 33 34 34 -
c/src/lib/libcpu/mips/mongoosev/vectorisrs/vectorisrs.c
re96a950b r35f97010 42 42 /* userspace routine to assert either software interrupt */ 43 43 44 int assertSoftwareInterrupt( u nsigned32n )44 int assertSoftwareInterrupt( uint32_t n ) 45 45 { 46 46 if( n<2 ) 47 47 { 48 u nsigned32c;48 uint32_t c; 49 49 50 50 mips_get_cause(c); … … 77 77 78 78 #if 0 79 #define SET_ISR_FLAG( offset ) *((u nsigned32*)(0x8001e000+offset)) = 1;80 #define CLR_ISR_FLAG( offset ) *((u nsigned32*)(0x8001e000+offset)) = 0;79 #define SET_ISR_FLAG( offset ) *((uint32_t *)(0x8001e000+offset)) = 1; 80 #define CLR_ISR_FLAG( offset ) *((uint32_t *)(0x8001e000+offset)) = 0; 81 81 #else 82 82 #define SET_ISR_FLAG( offset ) … … 89 89 90 90 91 static volatile u nsigned32_ivcause, _ivsr;92 93 94 static u nsigned32READ_CAUSE(void)91 static volatile uint32_t _ivcause, _ivsr; 92 93 94 static uint32_t READ_CAUSE(void) 95 95 { 96 96 mips_get_cause( _ivcause ); … … 117 117 void mips_vector_isr_handlers( CPU_Interrupt_frame *frame ) 118 118 { 119 u nsigned32cshifted;119 uint32_t cshifted; 120 120 121 121 /* mips_get_sr( sr ); */ … … 191 191 if ( cshifted & 0x80 ) /* IP[5] ==> INT5, peripheral interrupt */ 192 192 { 193 u nsigned32bit;194 u nsigned32pf_icr, pf_mask, pf_reset = 0;195 u nsigned32i, m;193 uint32_t bit; 194 uint32_t pf_icr, pf_mask, pf_reset = 0; 195 uint32_t i, m; 196 196 197 197 pf_icr = MONGOOSEV_READ( MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_CAUSE_REGISTER ); -
c/src/lib/libcpu/mips/shared/interrupts/vectorexceptions.c
re96a950b r35f97010 72 72 int i, j; 73 73 74 frame_u32 = (u nsigned32*)frame;74 frame_u32 = (uint32_t *)frame; 75 75 for(i=0; dumpregs[i].offset > -1; i++) 76 76 { … … 113 113 void mips_vector_exceptions( CPU_Interrupt_frame *frame ) 114 114 { 115 u nsigned32cause;116 u nsigned32exc;115 uint32_t cause; 116 uint32_t exc; 117 117 118 118 mips_get_cause( cause ); -
c/src/lib/libcpu/mips/timer/timer.c
re96a950b r35f97010 51 51 #define TIMER_MAX_VALUE 0xffffffff 52 52 53 extern u nsigned32mips_read_timer( void );53 extern uint32_t mips_read_timer( void ); 54 54 55 55 static rtems_boolean Timer_driver_Find_average_overhead; 56 static u nsigned32Timer_initial_value = 0;56 static uint32_t Timer_initial_value = 0; 57 57 58 58 void Timer_initialize( void ) … … 83 83 int Read_timer( void ) 84 84 { 85 u nsigned64clicks;86 u nsigned32total;85 uint64_t clicks; 86 uint32_t total; 87 87 88 88 /* -
c/src/lib/libcpu/mips/tx39/include/tx3904.h
re96a950b r35f97010 29 29 30 30 #define TX3904_TIMER_READ( _base, _register ) \ 31 *((volatile u nsigned32*)((_base) + (_register)))31 *((volatile uint32_t *)((_base) + (_register))) 32 32 33 33 #define TX3904_TIMER_WRITE( _base, _register, _value ) \ 34 *((volatile u nsigned32*)((_base) + (_register))) = (_value)34 *((volatile uint32_t *)((_base) + (_register))) = (_value) 35 35 36 36 /*
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