Changeset 359e537 in rtems for c/src/lib/libcpu/arm


Ignore:
Timestamp:
Nov 30, 2009, 5:09:41 AM (10 years ago)
Author:
Ralf Corsepius <ralf.corsepius@…>
Branches:
4.10, 4.11, master
Children:
023f1dd9
Parents:
ac7af4a
Message:

Whitespace removal.

Location:
c/src/lib/libcpu/arm
Files:
47 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/arm/at91rm9200/clock/clock.c

    rac7af4a r359e537  
    3535{
    3636    /* enable timer interrupt */
    37     ST_REG(ST_IER) = ST_SR_PITS; 
     37    ST_REG(ST_IER) = ST_SR_PITS;
    3838}
    3939
     
    5959{
    6060    /* check timer interrupt */
    61     return ST_REG(ST_IMR) & ST_SR_PITS; 
     61    return ST_REG(ST_IMR) & ST_SR_PITS;
    6262}
    6363
     
    6565
    6666/* Replace the first value with the clock's interrupt name. */
    67 rtems_irq_connect_data clock_isr_data = {AT91RM9200_INT_SYSIRQ,   
     67rtems_irq_connect_data clock_isr_data = {AT91RM9200_INT_SYSIRQ,
    6868                                         (rtems_irq_hdl)Clock_isr,
    6969                                         clock_isr_on,
     
    8989  st_pimr_reload = st_pimr_value;
    9090
    91   /* read the status to clear the int */ 
     91  /* read the status to clear the int */
    9292  st_str = ST_REG(ST_SR);
    93    
     93
    9494  /* set priority */
    95   AIC_SMR_REG(AIC_SMR_SYSIRQ) = AIC_SMR_PRIOR(0x7); 
     95  AIC_SMR_REG(AIC_SMR_SYSIRQ) = AIC_SMR_PRIOR(0x7);
    9696
    9797  /* set the timer value */
  • c/src/lib/libcpu/arm/at91rm9200/dbgu/dbgu.c

    rac7af4a r359e537  
    22 *  Console driver for AT91RM9200 DBGU port
    33 *
    4  *  This driver uses the shared console driver in 
     4 *  This driver uses the shared console driver in
    55 *  ...../libbsp/shared/console.c
    66 *
     
    3939
    4040/* Pointers to functions for handling the UART. */
    41 console_fns dbgu_fns = 
    42 { 
     41console_fns dbgu_fns =
     42{
    4343    libchip_serial_default_probe,
    4444    dbgu_first_open,
     
    5555/*********************************************************************/
    5656
    57 /* 
     57/*
    5858 * This is called the first time each device is opened. Since
    59  * the driver is polled, we don't have to do anything. If the driver 
    60  * were interrupt driven, we'd enable interrupts here. 
    61  */
    62 static int dbgu_first_open(int major, int minor, void *arg) 
     59 * the driver is polled, we don't have to do anything. If the driver
     60 * were interrupt driven, we'd enable interrupts here.
     61 */
     62static int dbgu_first_open(int major, int minor, void *arg)
    6363{
    6464    return 0;
     
    6666
    6767
    68 /* 
     68/*
    6969 * This is called the last time each device is closed.  Since
    70  * the driver is polled, we don't have to do anything. If the driver 
    71  * were interrupt driven, we'd disable interrupts here. 
    72  */
    73 static int dbgu_last_close(int major, int minor, void *arg) 
     70 * the driver is polled, we don't have to do anything. If the driver
     71 * were interrupt driven, we'd disable interrupts here.
     72 */
     73static int dbgu_last_close(int major, int minor, void *arg)
    7474{
    7575    return 0;
     
    8383 * the character in lowest 8 bits of returned int.
    8484 */
    85 static int dbgu_read(int minor) 
     85static int dbgu_read(int minor)
    8686{
    8787    char c;
     
    100100        return -1;
    101101    }
    102    
    103     c  = dbgu->rhr & 0xff; 
    104    
     102
     103    c  = dbgu->rhr & 0xff;
     104
    105105    return c;
    106106}
    107107
    108108
    109 /* 
    110  * Write buffer to UART 
     109/*
     110 * Write buffer to UART
    111111 *
    112112 * return 1 on success, -1 on error
     
    134134            }
    135135        }
    136        
     136
    137137        c = (char) buf[i];
    138138        dbgu->thr = c;
    139        
     139
    140140        /* the TXRDY flag does not seem to update right away (is this true?) */
    141141        /* so we wait a bit before continuing */
     
    144144        }
    145145    }
    146    
     146
    147147    return 1;
    148148}
     
    187187
    188188/* This is for setting baud rate, bits, etc. */
    189 static int dbgu_set_attributes(int minor, const struct termios *t) 
     189static int dbgu_set_attributes(int minor, const struct termios *t)
    190190{
    191191    return 0;
     
    198198 */
    199199/***********************************************************************/
    200 /* 
     200/*
    201201 * Read from UART. This is used in the exit code, and can't
    202202 * rely on interrupts.
     
    209209
    210210/*
    211  * Write a character to the console. This is used by printk() and 
     211 * Write a character to the console. This is used by printk() and
    212212 * maybe other low level functions. It should not use interrupts or any
    213213 * RTEMS system calls. It needs to be very simple
  • c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200.h

    rac7af4a r359e537  
    3333
    3434/* Control Register - 32 of them */
    35 #define AIC_CTL_BASE            0xFFFFF100     
     35#define AIC_CTL_BASE            0xFFFFF100
    3636#define AIC_CTL_REG(_x_)        *(vulong *)(AIC_CTL_BASE + (_x_ & 0x7f))
    3737
     
    104104#define AIC_SMR_PRIOR(_x_)      ((_x_ & 0x07) << 0)
    105105#define AIC_SMR_SRC_LVL_LOW     (0 << 5)        /* Are these right? docs don't say which is high/low     */
    106 #define AIC_SMR_SRC_EDGE_LOW    (1 << 5)       
    107 #define AIC_SMR_SRC_LVL_HI      (2 << 5)       
    108 #define AIC_SMR_SRC_EDGE_HI     (3 << 5)       
     106#define AIC_SMR_SRC_EDGE_LOW    (1 << 5)
     107#define AIC_SMR_SRC_LVL_HI      (2 << 5)
     108#define AIC_SMR_SRC_EDGE_HI     (3 << 5)
    109109
    110110/**************************************************************************/
     
    193193 * set of these registers starting at offset 0x100 from it's
    194194 * base address: DBGU, SPI, USART and SSC
    195  * To access the DMA for a peripheral, use the macro for that 
     195 * To access the DMA for a peripheral, use the macro for that
    196196 * peripheral but with these register offsets
    197197 **************************************************************************/
  • c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_dbgu.h

    rac7af4a r359e537  
    44 * Copyright (c) 2003 by Cogent Computer Systems
    55 * Written by Mike Kelly <mike@cogcomp.com>
    6  *     
     6 *
    77 *  The license and distribution terms for this file may be
    88 *  found in the file LICENSE in this distribution or at
  • c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_emac.h

    rac7af4a r359e537  
    44 * Copyright (c) 2003 by Cogent Computer Systems
    55 * Written by Mike Kelly <mike@cogcomp.com>
    6  *     
     6 *
    77 *  The license and distribution terms for this file may be
    88 *  found in the file LICENSE in this distribution or at
     
    105105#define EMAC_TSR_COMP   BIT5          /* 1 = Transmit complete */
    106106#define EMAC_TSR_UND    BIT6          /* 1 = Transmit underrun */
    107  
     107
    108108/* Receive Status Register, EMAC_RSR, Offset 0x20 */
    109109#define EMAC_RSR_BNA    BIT0          /* 1 = Buffer not available */
     
    138138#define EMAC_MAN_READ           (0x2 << 28)           /* Transfer is a read */
    139139#define EMAC_MAN_HIGH           BIT30                 /* Must be set */
    140 #define EMAC_MAN_LOW            BIT31 
     140#define EMAC_MAN_LOW            BIT31
    141141
    142142/*
  • c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_gpio.h

    rac7af4a r359e537  
    44 * Copyright (c) 2002 by Cogent Computer Systems
    55 * Written by Mike Kelly <mike@cogcomp.com>
    6  *     
     6 *
    77 *  The license and distribution terms for this file may be
    88 *  found in the file LICENSE in this distribution or at
     
    6060 * PORT A
    6161 */
    62 #define GPIO_0          BIT0   
    63 #define GPIO_1          BIT1   
    64 #define GPIO_2          BIT2   
    65 #define GPIO_3          BIT3   
    66 #define GPIO_4          BIT4   
    67 #define GPIO_5          BIT5   
    68 #define GPIO_6          BIT6   
    69 #define GPIO_7          BIT7   
    70 #define GPIO_8          BIT8   
    71 #define GPIO_9          BIT9   
     62#define GPIO_0          BIT0
     63#define GPIO_1          BIT1
     64#define GPIO_2          BIT2
     65#define GPIO_3          BIT3
     66#define GPIO_4          BIT4
     67#define GPIO_5          BIT5
     68#define GPIO_6          BIT6
     69#define GPIO_7          BIT7
     70#define GPIO_8          BIT8
     71#define GPIO_9          BIT9
    7272#define GPIO_10         BIT10
    7373#define GPIO_11         BIT11
     
    9393#define GPIO_31         BIT31
    9494/* PORT B */
    95 #define GPIO_32         BIT0   
    96 #define GPIO_33         BIT1   
    97 #define GPIO_34         BIT2   
    98 #define GPIO_35         BIT3   
    99 #define GPIO_36         BIT4   
    100 #define GPIO_37         BIT5   
    101 #define GPIO_38         BIT6   
    102 #define GPIO_39         BIT7   
    103 #define GPIO_40         BIT8   
    104 #define GPIO_41         BIT9   
     95#define GPIO_32         BIT0
     96#define GPIO_33         BIT1
     97#define GPIO_34         BIT2
     98#define GPIO_35         BIT3
     99#define GPIO_36         BIT4
     100#define GPIO_37         BIT5
     101#define GPIO_38         BIT6
     102#define GPIO_39         BIT7
     103#define GPIO_40         BIT8
     104#define GPIO_41         BIT9
    105105#define GPIO_42         BIT10
    106106#define GPIO_43         BIT11
     
    126126#define GPIO_63         BIT31
    127127/* PORT C */
    128 #define GPIO_64         BIT0   
    129 #define GPIO_65         BIT1   
    130 #define GPIO_66         BIT2   
    131 #define GPIO_67         BIT3   
    132 #define GPIO_68         BIT4   
    133 #define GPIO_69         BIT5   
    134 #define GPIO_70         BIT6   
    135 #define GPIO_71         BIT7   
    136 #define GPIO_72         BIT8   
    137 #define GPIO_73         BIT9   
     128#define GPIO_64         BIT0
     129#define GPIO_65         BIT1
     130#define GPIO_66         BIT2
     131#define GPIO_67         BIT3
     132#define GPIO_68         BIT4
     133#define GPIO_69         BIT5
     134#define GPIO_70         BIT6
     135#define GPIO_71         BIT7
     136#define GPIO_72         BIT8
     137#define GPIO_73         BIT9
    138138#define GPIO_74         BIT10
    139139#define GPIO_75         BIT11
     
    159159#define GPIO_95         BIT31
    160160/* PORT D */
    161 #define GPIO_96         BIT0   
    162 #define GPIO_97         BIT1   
    163 #define GPIO_98         BIT2   
    164 #define GPIO_99         BIT3   
    165 #define GPIO_100        BIT4   
    166 #define GPIO_101        BIT5   
    167 #define GPIO_102        BIT6   
    168 #define GPIO_103        BIT7   
    169 #define GPIO_104        BIT8   
    170 #define GPIO_105        BIT9   
     161#define GPIO_96         BIT0
     162#define GPIO_97         BIT1
     163#define GPIO_98         BIT2
     164#define GPIO_99         BIT3
     165#define GPIO_100        BIT4
     166#define GPIO_101        BIT5
     167#define GPIO_102        BIT6
     168#define GPIO_103        BIT7
     169#define GPIO_104        BIT8
     170#define GPIO_105        BIT9
    171171#define GPIO_106        BIT10
    172172#define GPIO_107        BIT11
     
    377377#define PIOD_ASR_RTS3   BIT24   /* USART 3 RTS */
    378378#define PIOD_ASR_DTR1   BIT25   /* USART 1 DTR */
    379                    
     379
    380380/* Port D, Alternate Function B */
    381                
     381
    382382#define PIOC_ASR_TSYNC  BIT7    /* ETM Sync      */
    383383#define PIOC_ASR_TCLK   BIT8    /* ETM Clock */
  • c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_mem.h

    rac7af4a r359e537  
    44 * Copyright (c) 2002 by Cogent Computer Systems
    55 * Written by Mike Kelly <mike@cogcomp.com>
    6  *     
     6 *
    77 *  The license and distribution terms for this file may be
    88 *  found in the file LICENSE in this distribution or at
  • c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_pmc.h

    rac7af4a r359e537  
    44 * Copyright (c) 2002 by Cogent Computer Systems
    55 * Written by Mike Kelly <mike@cogcomp.com>
    6  *     
     6 *
    77 *  The license and distribution terms for this file may be
    88 *  found in the file LICENSE in this distribution or at
  • c/src/lib/libcpu/arm/at91rm9200/include/bits.h

    rac7af4a r359e537  
    44 * Copyright (c) 2002 by Cogent Computer Systems
    55 * Written by Mike Kelly <mike@cogcomp.com>
    6  *     
     6 *
    77 *  The license and distribution terms for this file may be
    88 *  found in the file LICENSE in this distribution or at
  • c/src/lib/libcpu/arm/at91rm9200/irq/bsp_irq_asm.S

    rac7af4a r359e537  
    33 *
    44 * Copyright (c) 2004 by Jay Monkman <jtm@lopgindog.com>
    5  *     
     5 *
    66 *  The license and distribution terms for this file may be
    77 *  found in the file LICENSE in this distribution or at
     
    1313 */
    1414#define __asm__
    15        
     15
    1616        .globl bsp_interrupt_dispatch
    1717bsp_interrupt_dispatch :
     
    2222 */
    2323        ldr     r0, =0xFFFFF100   /* AIC_CTL_BASE + AIC_IVR */
    24         ldr     r1, [r0]               
     24        ldr     r1, [r0]
    2525        str     r1, [r0]          /* write back in case we are using protect */
    2626
     
    3636        ldr   r2, =0xFFFFF130     /* AIC_CTL_BASE + AIC_EIOCR */
    3737        str   r1, [r2]
    38        
     38
    3939        ldmia sp!,{lr}
    4040
  • c/src/lib/libcpu/arm/at91rm9200/irq/bsp_irq_init.c

    rac7af4a r359e537  
    33 *
    44 * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
    5  *     
     5 *
    66 *  The license and distribution terms for this file may be
    77 *  found in the file LICENSE in this distribution or at
     
    1818extern void default_int_handler(void);
    1919
    20 /* 
    21  * Interrupt system initialization. Disable interrupts, clear 
     20/*
     21 * Interrupt system initialization. Disable interrupts, clear
    2222 * any that are pending.
    2323 */
  • c/src/lib/libcpu/arm/at91rm9200/irq/irq.c

    rac7af4a r359e537  
    33 *
    44 * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
    5  *     
     5 *
    66 *  The license and distribution terms for this file may be
    77 *  found in the file LICENSE in this distribution or at
     
    3535{
    3636    rtems_interrupt_level level;
    37    
     37
    3838    if (!isValidInterrupt(irq->name)) {
    3939        return 0;
    4040    }
    41    
     41
    4242    /*
    43      * Check if default handler is actually connected. If not, issue 
    44      * an error. Note: irq->name is a number corresponding to the 
    45      * sources PID (see the at91rm9200_pid for this mapping).  We 
    46      * convert it to a long word offset to get source's vector register 
     43     * Check if default handler is actually connected. If not, issue
     44     * an error. Note: irq->name is a number corresponding to the
     45     * sources PID (see the at91rm9200_pid for this mapping).  We
     46     * convert it to a long word offset to get source's vector register
    4747     */
    4848    if (AIC_SVR_REG(irq->name * 4) != (uint32_t) default_int_handler) {
    4949        return 0;
    5050    }
    51    
     51
    5252    rtems_interrupt_disable(level);
    53    
     53
    5454    /*
    5555     * store the new handler
    5656     */
    5757    AIC_SVR_REG(irq->name * 4) = (uint32_t) irq->hdl;
    58    
     58
    5959    /*
    6060     * unmask interrupt
    6161     */
    6262    AIC_CTL_REG(AIC_IECR) = 1 << irq->name;
    63    
     63
    6464    /*
    6565     * Enable interrupt on device
     
    6868        irq->on(irq);
    6969    }
    70    
     70
    7171    rtems_interrupt_enable(level);
    72    
     72
    7373    return 1;
    7474}
    7575
    76 /* 
     76/*
    7777 * Remove and interrupt handler
    7878 */
     
    8080{
    8181    rtems_interrupt_level level;
    82  
     82
    8383    if (!isValidInterrupt(irq->name)) {
    8484        return 0;
     
    9797     */
    9898    AIC_CTL_REG(AIC_IDCR) = 1 << irq->name;
    99    
     99
    100100    /*
    101101     * Disable interrupt on device
     
    109109     */
    110110    AIC_SVR_REG(irq->name * 4) = (uint32_t) default_int_handler;
    111    
     111
    112112    rtems_interrupt_enable(level);
    113113
  • c/src/lib/libcpu/arm/at91rm9200/irq/irq.h

    rac7af4a r359e537  
    33 *
    44 * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
    5  *     
     5 *
    66 *  The license and distribution terms for this file may be
    77 *  found in the file LICENSE in this distribution or at
     
    2525 * Include some preprocessor value also used by assember code
    2626 */
    27  
     27
    2828#include <rtems.h>
    2929#include <at91rm9200.h>
     
    3636#define AT91RM9200_INT_FIQ        0
    3737#define AT91RM9200_INT_SYSIRQ     1
    38 #define AT91RM9200_INT_PIOA       2 
     38#define AT91RM9200_INT_PIOA       2
    3939#define AT91RM9200_INT_PIOB       3
    4040#define AT91RM9200_INT_PIOC       4
     
    7272/* a vector table */
    7373#define VECTOR_TABLE AIC_SVR_BASE
    74                                                                                            
     74
    7575typedef unsigned char  rtems_irq_level;
    7676typedef unsigned char  rtems_irq_trigger;
     
    118118
    119119/*
    120  * function to get the current RTEMS irq handler for ptr->name. 
     120 * function to get the current RTEMS irq handler for ptr->name.
    121121 */
    122122int BSP_get_current_rtems_irq_handler   (rtems_irq_connect_data* ptr);
  • c/src/lib/libcpu/arm/at91rm9200/pmc/pmc.c

    rac7af4a r359e537  
    33 *
    44 * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
    5  *     
     5 *
    66 *  The license and distribution terms for this file may be
    77 *  found in the file LICENSE in this distribution or at
  • c/src/lib/libcpu/arm/at91rm9200/timer/timer.c

    rac7af4a r359e537  
    55 *
    66 * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
    7  *     
     7 *
    88 *  The license and distribution terms for this file may be
    99 *  found in the file LICENSE in this distribution or at
     
    1717 *  the number of microseconds since benchmark_timer_initialize() exitted.
    1818 *
    19  *  It is important that the timer start/stop overhead be determined 
     19 *  It is important that the timer start/stop overhead be determined
    2020 *  when porting or modifying this code.
    2121 *
     
    3232uint32_t tick_time;
    3333/*
    34  * Set up TC0 - 
     34 * Set up TC0 -
    3535 *   timer_clock2 (MCK/8)
    3636 *   capture mode - this shouldn't matter
  • c/src/lib/libcpu/arm/at91rm9200/usart/usart.c

    rac7af4a r359e537  
    22 *  Driver for AT91RM9200 USART ports
    33 *
    4  * COPYRIGHT (c) 2006-2009. 
     4 * COPYRIGHT (c) 2006-2009.
    55 * NCB - Sistemas Embarcados Ltda. (Brazil)
    66 * Fernando Nicodemos <fgnicodemos@terra.com.br>
    7  * 
     7 *
    88 * and
    99 *
     
    6161  if (console_entry == NULL)
    6262    return 0;
    63  
     63
    6464  port = (at91rm9200_usart_regs_t *) console_entry->ulCtrlPort1;
    6565  //printk( "minor=%d entry=%p port=%p\n", minor, console_entry, port );
     
    242242
    243243  baud_requested = t->c_cflag & CBAUD;
    244  
     244
    245245  /* If not, set the dbgu console baud as USART baud default */
    246246  if (!baud_requested)
    247     baud_requested = BSP_get_baud(); 
    248  
     247    baud_requested = BSP_get_baud();
     248
    249249  baud = rtems_termios_baud_to_number(baud_requested);
    250250
  • c/src/lib/libcpu/arm/lpc22xx/clock/clockdrv.c

    rac7af4a r359e537  
    3636                                         0 };   /* unused for ARM cpus */
    3737
    38 /* If you follow the code, this is never used, so any value 
     38/* If you follow the code, this is never used, so any value
    3939 * should work
    4040 */
     
    7373 *   - clear any pending interrupts
    7474 *
    75  * Since you may want the clock always running, you can 
     75 * Since you may want the clock always running, you can
    7676 * enable interrupts here. If you do so, the clock_isr_on(),
    77  * clock_isr_off(), and clock_isr_is_on() functions can be 
     77 * clock_isr_off(), and clock_isr_is_on() functions can be
    7878 * NOPs.
    7979 */
    80  
     80
    8181  /* set timer to generate interrupt every rtems_configuration_get_microseconds_per_tick()
    8282   * MR0/(LPC22xx_Fpclk/(PR0+1)) = 10/1000 = 0.01s
    83    */                   
    84        
     83   */
     84
    8585#define Clock_driver_support_initialize_hardware() \
    8686  do { \
     
    9696
    9797/**
    98  * Do whatever you need to shut the clock down and remove the 
     98 * Do whatever you need to shut the clock down and remove the
    9999 * interrupt handler. Since this normally only gets called on
    100100 * RTEMS shutdown, you may not need to do anything other than
     
    111111{
    112112        uint32_t clicks;
    113        
     113
    114114        clicks = T0TC;  /*T0TC is the 32bit time counter 0*/
    115        
     115
    116116        return (uint32_t) (rtems_configuration_get_microseconds_per_tick() - clicks) * 1000;
    117117}
    118        
     118
    119119#define Clock_driver_nanoseconds_since_last_tick bsp_clock_nanoseconds_since_last_tick
    120120
  • c/src/lib/libcpu/arm/lpc22xx/include/lpc22xx.h

    rac7af4a r359e537  
    33 *
    44 * Copyright (c) 2006 by Ray <rayx.cn@gmail.com>
    5  *     
     5 *
    66 *  The license and distribution terms for this file may be
    77 *  found in the file LICENSE in this distribution or at
     
    319319#define CAN5TDB3        (*((volatile unsigned long *) 0xE005405C))      /* lpc2119\lpc2129\lpc2292\lpc2294 only */
    320320
    321 #ifdef CONFIG_ARCH_LPC22xx 
     321#ifdef CONFIG_ARCH_LPC22xx
    322322#define CAN6MOD         (*((volatile unsigned long *) 0xE0058000))      /* lpc2292\lpc2294 only */
    323323#define CAN6CMR         (*((volatile unsigned long *) 0xE0058004))      /* lpc2292\lpc2294 only */
     
    456456/*
    457457        Register define for constant
    458 */     
     458*/
    459459#define REG_U0RBR                               0xE000C000
    460460#define REG_U1RBR                               0xE0010000
  • c/src/lib/libcpu/arm/lpc22xx/irq/bsp_irq_asm.S

    rac7af4a r359e537  
    1313 */
    1414#define __asm__
    15        
    16 /* 
     15
     16/*
    1717 * BSP specific interrupt handler for INT or FIQ. In here
    1818 * you do determine which interrupt happened and call its
     
    3131 * and load handler address into r0.
    3232 */
    33  
     33
    3434  ldr   r0, =0xFFFFF030  /* Read the vector number */
    3535    ldr r0, [r0]
  • c/src/lib/libcpu/arm/lpc22xx/irq/bsp_irq_init.c

    rac7af4a r359e537  
    11/*
    22 *  NXP/Philips LPC22XX/LPC21xx Interrupt handler
    3  *  Ray 2007 <rayx.cn@gmail.com> to support LPC ARM     
     3 *  Ray 2007 <rayx.cn@gmail.com> to support LPC ARM
    44 *  The license and distribution terms for this file may be
    55 *  found in the file LICENSE in this distribution or at
     
    1717extern void default_int_handler(void);
    1818
    19 /* 
    20  * Interrupt system initialization. Disable interrupts, clear 
     19/*
     20 * Interrupt system initialization. Disable interrupts, clear
    2121 * any that are pending.
    2222 */
     
    3434      *(vectorTable + i) = (long)(default_int_handler);
    3535  }
    36    
     36
    3737  /*
    3838   * Set IRQHandler
     
    5757   * enable the next lines and set a breakpoint
    5858   * in ABORTHandler.
    59    */ 
     59   */
    6060#if 1
    6161  DATA_ABORT_VECTOR_ADDR = 0xE59FF018;
    62 #endif 
     62#endif
    6363
    6464  /*
  • c/src/lib/libcpu/arm/lpc22xx/irq/irq.c

    rac7af4a r359e537  
    11/*
    22 * Philps LPC22XX Interrupt handler
    3  * 
    4  * Copyright (c)  2006 by Ray<rayx.cn@gmail.com>  to support LPC ARM     
     3 *
     4 * Copyright (c)  2006 by Ray<rayx.cn@gmail.com>  to support LPC ARM
    55 *  The license and distribution terms for this file may be
    66 *  found in the file LICENSE in this distribution or at
     
    3838    rtems_irq_hdl        *bsp_tbl;
    3939    int                  *vic_cntl;
    40    
     40
    4141    bsp_tbl = (rtems_irq_hdl *)VICVectAddrBase;
    4242
    4343    vic_cntl=(int *)VICVectCntlBase;
    44    
     44
    4545    if (!isValidInterrupt(irq->name)) {
    4646      return 0;
     
    6767    vic_cntl[irq->name] = 0x20 | irq->name;
    6868
    69     VICIntEnable |= 1 << irq->name; 
    70    
     69    VICIntEnable |= 1 << irq->name;
     70
    7171    if(irq->on)
    7272    {
     
    7676
    7777    rtems_interrupt_enable(level);
    78    
     78
    7979    return 1;
    8080}
    8181
    82 /* 
     82/*
    8383 * Remove and interrupt handler
    8484 *
     
    9292
    9393    bsp_tbl = (rtems_irq_hdl *)&VICVectAddr0;
    94  
     94
    9595    if (!isValidInterrupt(irq->name)) {
    9696      return 0;
     
    117117     */
    118118    bsp_tbl[irq->name] = default_int_handler;
    119    
     119
    120120    rtems_interrupt_enable(level);
    121121
  • c/src/lib/libcpu/arm/lpc22xx/irq/irq.h

    rac7af4a r359e537  
    22 * Interrupt handler Header file
    33 *
    4  * Copyright (c) 2006 by Ray <rayx.cn@gmail.com> to support LPC ARM 
    5  *     
     4 * Copyright (c) 2006 by Ray <rayx.cn@gmail.com> to support LPC ARM
     5 *
    66 *  The license and distribution terms for this file may be
    77 *  found in the file LICENSE in this distribution or at
     
    2626 * Include some preprocessor value also used by assember code
    2727 */
    28  
     28
    2929#include <rtems.h>
    3030#include <lpc22xx.h>
     
    6767#define BSP_MAX_INT              28
    6868
    69 #define UNDEFINED_INSTRUCTION_VECTOR_ADDR   (*(u_long *)0x00000004L)   
     69#define UNDEFINED_INSTRUCTION_VECTOR_ADDR   (*(u_long *)0x00000004L)
    7070#define SOFTWARE_INTERRUPT_VECTOR_ADDR      (*(u_long *)0x00000008L)
    7171#define PREFETCH_ABORT_VECTOR_ADDR          (*(u_long *)0x0000000CL)
     
    7878#define FIQ_ISR_ADDR                        (*(u_long *)0x0000003CL)
    7979
    80              
     80
    8181typedef unsigned char  rtems_irq_level;
    8282typedef unsigned char  rtems_irq_trigger;
     
    9292//extern rtems_irq_hdl bsp_vector_table[BSP_MAX_INT];
    9393#define VECTOR_TABLE VICVectAddrBase
    94                                                                                            
     94
    9595typedef struct __rtems_irq_connect_data__ {
    9696    /* IRQ line */
     
    128128
    129129/*
    130  * function to get the current RTEMS irq handler for ptr->name. 
     130 * function to get the current RTEMS irq handler for ptr->name.
    131131 */
    132132int BSP_get_current_rtems_irq_handler   (rtems_irq_connect_data* ptr);
  • c/src/lib/libcpu/arm/lpc22xx/timer/lpc_timer.h

    rac7af4a r359e537  
    1212#define TCR_RESET_BIT   1
    1313
    14 // The channel name which is used in matching, in fact they represent 
    15 // corresponding Match Register 
     14// The channel name which is used in matching, in fact they represent
     15// corresponding Match Register
    1616#define CH_MAXNUM       4
    1717#define CH0             0
     
    2020#define CH3             3
    2121
    22 // The channel name which is used in capturing, in fact they represent 
    23 // corresponding Capture Register 
     22// The channel name which is used in capturing, in fact they represent
     23// corresponding Capture Register
    2424#define CPCH_MAXNUM     4
    2525#define CPCH0           0
  • c/src/lib/libcpu/arm/lpc22xx/timer/timer.c

    rac7af4a r359e537  
    33 *
    44 * This uses Timer1 for timing measurments.
    5  * 
     5 *
    66 *  By Ray xu<rayx.cn@gmail.com>, modify form Mc9328mxl RTEMS DSP
    77 *
     
    1717 *  the number of microseconds since benchmark_timer_initialize() exitted.
    1818 *
    19  *  It is important that the timer start/stop overhead be determined 
     19 *  It is important that the timer start/stop overhead be determined
    2020 *  when porting or modifying this code.
    2121 *
     
    3232bool benchmark_timer_find_average_overhead;
    3333
    34    
     34
    3535/*
    3636 * Set up Timer 1
  • c/src/lib/libcpu/arm/mc9328mxl/clock/clockdrv.c

    rac7af4a r359e537  
    3838};
    3939
    40 /* If you follow the code, this is never used, so any value 
     40/* If you follow the code, this is never used, so any value
    4141 * should work
    4242 */
    4343#define CLOCK_VECTOR 0
    4444
    45    
     45
    4646/**
    4747 * When we get the clock interrupt
     
    7373 *   - clear any pending interrupts
    7474 *
    75  * Since you may want the clock always running, you can 
     75 * Since you may want the clock always running, you can
    7676 * enable interrupts here. If you do so, the clock_isr_on(),
    77  * clock_isr_off(), and clock_isr_is_on() functions can be 
     77 * clock_isr_off(), and clock_isr_is_on() functions can be
    7878 * NOPs.
    7979 */
     
    9696
    9797/**
    98  * Do whatever you need to shut the clock down and remove the 
     98 * Do whatever you need to shut the clock down and remove the
    9999 * interrupt handler. Since this normally only gets called on
    100100 * RTEMS shutdown, you may not need to do anything other than
  • c/src/lib/libcpu/arm/mc9328mxl/include/mc9328mxl.h

    rac7af4a r359e537  
    44 * Copyright (c) 2003 by Cogent Computer Systems
    55 * Written by Jay Monkman <jtm@lopingdog.com>
    6  *     
     6 *
    77 *  The license and distribution terms for this file may be
    88 *  found in the file LICENSE in this distribution or at
     
    7676#define MC9328MXL_TMR_TCTL_CAP_ANY            (3 << 6)
    7777#define MC9328MXL_TMR_TCTL_OM                 (bit(5))
    78 #define MC9328MXL_TMR_TCTL_IRQEN              (bit(4))               
     78#define MC9328MXL_TMR_TCTL_IRQEN              (bit(4))
    7979#define MC9328MXL_TMR_TCTL_CLKSRC_STOP        (0 << 1)
    8080#define MC9328MXL_TMR_TCTL_CLKSRC_PCLK1       (1 << 1)
    8181#define MC9328MXL_TMR_TCTL_CLKSRC_PCLK_DIV16  (2 << 1)
    8282#define MC9328MXL_TMR_TCTL_CLKSRC_TIN         (3 << 1)
    83 #define MC9328MXL_TMR_TCTL_CLKSRC_32KHX       (4 << 1) 
     83#define MC9328MXL_TMR_TCTL_CLKSRC_32KHX       (4 << 1)
    8484#define MC9328MXL_TMR_TCTL_TEN                (bit(0))
    8585
     
    222222#define MC9328MXL_UART_CR3_BPEN       (bit(0))
    223223
    224 #define MC9328MXL_UART_CR4_CTSTL(_x_) (((_x_) & 0x3f) << 10)     
     224#define MC9328MXL_UART_CR4_CTSTL(_x_) (((_x_) & 0x3f) << 10)
    225225#define MC9328MXL_UART_CR4_INVR       (bit(9))
    226226#define MC9328MXL_UART_CR4_ENIRI      (bit(8))
     
    314314#define MC9328MXL_PLL_SPCTL_MFN_MASK       (0x000003ff)
    315315#define MC9328MXL_PLL_SPCTL_MFN_SHIFT      (0)
    316    
     316
    317317
    318318#define MC9328MXL_GPIOA_DDIR    (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x00)))
  • c/src/lib/libcpu/arm/mc9328mxl/irq/bsp_irq_asm.S

    rac7af4a r359e537  
    1313 */
    1414#define __asm__
    15        
    16 /* 
     15
     16/*
    1717 * BSP specific interrupt handler for INT or FIQ. In here
    1818 * you do determine which interrupt happened and call its
     
    3030  mov   r1, r1, LSR #16         /* get the NIVECTOR into 16 LSbits */
    3131
    32   /* find the ISR's address based on the vector */     
     32  /* find the ISR's address based on the vector */
    3333  ldr   r0, =bsp_vector_table
    3434  mov   r1, r1, LSL #3          /* Shift vector to get offset into table */
  • c/src/lib/libcpu/arm/mc9328mxl/irq/bsp_irq_init.c

    rac7af4a r359e537  
    33 *
    44 * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
    5  *     
     5 *
    66 *  The license and distribution terms for this file may be
    77 *  found in the file LICENSE in this distribution or at
     
    1818extern void default_int_handler(void);
    1919
    20 /* 
    21  * Interrupt system initialization. Disable interrupts, clear 
     20/*
     21 * Interrupt system initialization. Disable interrupts, clear
    2222 * any that are pending.
    2323 */
  • c/src/lib/libcpu/arm/mc9328mxl/irq/irq.c

    rac7af4a r359e537  
    33 *
    44 * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
    5  *     
     5 *
    66 *  The license and distribution terms for this file may be
    77 *  found in the file LICENSE in this distribution or at
     
    3939{
    4040    rtems_interrupt_level level;
    41    
     41
    4242    if (!isValidInterrupt(irq->name)) {
    4343      return 0;
     
    6666        irq->on(irq);
    6767    }
    68    
     68
    6969    rtems_interrupt_enable(level);
    70    
     70
    7171    return 1;
    7272}
    7373
    74 /* 
     74/*
    7575 * Remove and interrupt handler
    7676 *
  • c/src/lib/libcpu/arm/mc9328mxl/irq/irq.h

    rac7af4a r359e537  
    33 *
    44 * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
    5  *     
     5 *
    66 *  The license and distribution terms for this file may be
    77 *  found in the file LICENSE in this distribution or at
     
    2828 * Include some preprocessor value also used by assember code
    2929 */
    30  
     30
    3131#include <rtems.h>
    3232#include <mc9328mxl.h>
     
    3838
    3939/* possible interrupt sources on the MC9328MXL */
    40 #define BSP_INT_UART3_PFERR       0 
    41 #define BSP_INT_UART3_RTS         1     
    42 #define BSP_INT_UART3_DTR         2     
    43 #define BSP_INT_UART3_UARTC       3       
    44 #define BSP_INT_UART3_TX          4   
    45 #define BSP_INT_PEN_UP            5 
     40#define BSP_INT_UART3_PFERR       0
     41#define BSP_INT_UART3_RTS         1
     42#define BSP_INT_UART3_DTR         2
     43#define BSP_INT_UART3_UARTC       3
     44#define BSP_INT_UART3_TX          4
     45#define BSP_INT_PEN_UP            5
    4646#define BSP_INT_CSI               6
    47 #define BSP_INT_MMA_MAC           7   
     47#define BSP_INT_MMA_MAC           7
    4848#define BSP_INT_MMA               8
    4949#define BSP_INT_COMP              9
    50 #define BSP_INT_MSIRQ            10 
    51 #define BSP_INT_GPIO_PORTA       11       
    52 #define BSP_INT_GPIO_PORTB       12       
    53 #define BSP_INT_GPIO_PORTC       13       
    54 #define BSP_INT_LCDC             14 
    55 #define BSP_INT_SIM_IRQ          15   
    56 #define BSP_INT_SIM_DATA         16     
     50#define BSP_INT_MSIRQ            10
     51#define BSP_INT_GPIO_PORTA       11
     52#define BSP_INT_GPIO_PORTB       12
     53#define BSP_INT_GPIO_PORTC       13
     54#define BSP_INT_LCDC             14
     55#define BSP_INT_SIM_IRQ          15
     56#define BSP_INT_SIM_DATA         16
    5757#define BSP_INT_RTC              17
    58 #define BSP_INT_RTC_SAM          18   
    59 #define BSP_INT_UART2_PFERR      19       
    60 #define BSP_INT_UART2_RTS        20     
    61 #define BSP_INT_UART2_DTR        21     
    62 #define BSP_INT_UART2_UARTC      22       
    63 #define BSP_INT_UART2_TX         23     
    64 #define BSP_INT_UART2_RX         24     
    65 #define BSP_INT_UART1_PFERR      25       
    66 #define BSP_INT_UART1_RTS        26     
    67 #define BSP_INT_UART1_DTR        27     
    68 #define BSP_INT_UART1_UARTC      28       
    69 #define BSP_INT_UART1_TX         29     
    70 #define BSP_INT_UART1_RX         30     
    71 #define BSP_INT_RES31            31 
    72 #define BSP_INT_RES32            32 
    73 #define BSP_INT_PEN_DATA         33   
     58#define BSP_INT_RTC_SAM          18
     59#define BSP_INT_UART2_PFERR      19
     60#define BSP_INT_UART2_RTS        20
     61#define BSP_INT_UART2_DTR        21
     62#define BSP_INT_UART2_UARTC      22
     63#define BSP_INT_UART2_TX         23
     64#define BSP_INT_UART2_RX         24
     65#define BSP_INT_UART1_PFERR      25
     66#define BSP_INT_UART1_RTS        26
     67#define BSP_INT_UART1_DTR        27
     68#define BSP_INT_UART1_UARTC      28
     69#define BSP_INT_UART1_TX         29
     70#define BSP_INT_UART1_RX         30
     71#define BSP_INT_RES31            31
     72#define BSP_INT_RES32            32
     73#define BSP_INT_PEN_DATA         33
    7474#define BSP_INT_PWM              34
    75 #define BSP_INT_MMC_IRQ          35   
    76 #define BSP_INT_SSI2_TX          36   
    77 #define BSP_INT_SSI2_RX          37   
    78 #define BSP_INT_SSI2_ERR         38   
     75#define BSP_INT_MMC_IRQ          35
     76#define BSP_INT_SSI2_TX          36
     77#define BSP_INT_SSI2_RX          37
     78#define BSP_INT_SSI2_ERR         38
    7979#define BSP_INT_I2C              39
    8080#define BSP_INT_SPI2             40
    8181#define BSP_INT_SPI1             41
    82 #define BSP_INT_SSI_TX           42 
    83 #define BSP_INT_SSI_TX_ERR       43     
    84 #define BSP_INT_SSI_RX           44   
    85 #define BSP_INT_SSI_RX_ERR       45     
    86 #define BSP_INT_TOUCH            46 
    87 #define BSP_INT_USBD0            47 
    88 #define BSP_INT_USBD1            48 
    89 #define BSP_INT_USBD2            49 
    90 #define BSP_INT_USBD3            50 
    91 #define BSP_INT_USBD4            51 
    92 #define BSP_INT_USBD5            52 
    93 #define BSP_INT_USBD6            53 
    94 #define BSP_INT_UART3_RX         54   
    95 #define BSP_INT_BTSYS            55 
    96 #define BSP_INT_BTTIM            56 
    97 #define BSP_INT_BTWUI            57 
    98 #define BSP_INT_TIMER2           58 
    99 #define BSP_INT_TIMER1           59   
    100 #define BSP_INT_DMA_ERR          60   
     82#define BSP_INT_SSI_TX           42
     83#define BSP_INT_SSI_TX_ERR       43
     84#define BSP_INT_SSI_RX           44
     85#define BSP_INT_SSI_RX_ERR       45
     86#define BSP_INT_TOUCH            46
     87#define BSP_INT_USBD0            47
     88#define BSP_INT_USBD1            48
     89#define BSP_INT_USBD2            49
     90#define BSP_INT_USBD3            50
     91#define BSP_INT_USBD4            51
     92#define BSP_INT_USBD5            52
     93#define BSP_INT_USBD6            53
     94#define BSP_INT_UART3_RX         54
     95#define BSP_INT_BTSYS            55
     96#define BSP_INT_BTTIM            56
     97#define BSP_INT_BTWUI            57
     98#define BSP_INT_TIMER2           58
     99#define BSP_INT_TIMER1           59
     100#define BSP_INT_DMA_ERR          60
    101101#define BSP_INT_DMA              61
    102 #define BSP_INT_GPIO_PORTD       62     
     102#define BSP_INT_GPIO_PORTD       62
    103103#define BSP_INT_WDT              63
    104104#define BSP_MAX_INT              64
    105              
     105
    106106typedef struct {
    107107    rtems_irq_hdl       vector;
  • c/src/lib/libcpu/arm/mc9328mxl/timer/timer.c

    rac7af4a r359e537  
    66 * Copyright (c) 2004 Cogent Computer Systems
    77 *        Written by Jay Monkman <jtm@lopingdog.com>
    8  *     
     8 *
    99 *  The license and distribution terms for this file may be
    1010 *  found in the file LICENSE in this distribution or at
     
    1818 *  the number of microseconds since benchmark_timer_initialize() exitted.
    1919 *
    20  *  It is important that the timer start/stop overhead be determined 
     20 *  It is important that the timer start/stop overhead be determined
    2121 *  when porting or modifying this code.
    2222 *
     
    3333bool benchmark_timer_find_average_overhead;
    3434
    35    
     35
    3636/*
    3737 * Set up Timer 1
     
    3939void benchmark_timer_initialize( void )
    4040{
    41     MC9328MXL_TMR2_TCTL = (MC9328MXL_TMR_TCTL_CLKSRC_PCLK1 | 
     41    MC9328MXL_TMR2_TCTL = (MC9328MXL_TMR_TCTL_CLKSRC_PCLK1 |
    4242                            MC9328MXL_TMR_TCTL_FRR |
    4343                            MC9328MXL_TMR_TCTL_TEN);
     
    8181
    8282  /* convert to nanoseconds */
    83   total = (total * 1000)/ g_freq; 
     83  total = (total * 1000)/ g_freq;
    8484
    8585  if ( benchmark_timer_find_average_overhead == 1 ) {
    86     return (int) total; 
     86    return (int) total;
    8787  } else if ( total < LEAST_VALID ) {
    88       return 0;       
     88      return 0;
    8989  }
    9090  /*
  • c/src/lib/libcpu/arm/pxa255/ffuart/ffuart.c

    rac7af4a r359e537  
    3232
    3333/* Pointers to functions for handling the UART. */
    34 console_fns ffuart_fns = 
    35 { 
     34console_fns ffuart_fns =
     35{
    3636    libchip_serial_default_probe,
    3737    ffuart_first_open,
     
    4646
    4747
    48 /* 
     48/*
    4949 * This is called the first time each device is opened. Since
    50  * the driver is polled, we don't have to do anything. If the driver 
    51  * were interrupt driven, we'd enable interrupts here. 
    52  */
    53 static int ffuart_first_open(int major, int minor, void *arg) 
     50 * the driver is polled, we don't have to do anything. If the driver
     51 * were interrupt driven, we'd enable interrupts here.
     52 */
     53static int ffuart_first_open(int major, int minor, void *arg)
    5454{
    5555    return 0;
     
    5757
    5858
    59 /* 
     59/*
    6060 * This is called the last time each device is closed.  Since
    61  * the driver is polled, we don't have to do anything. If the driver 
    62  * were interrupt driven, we'd disable interrupts here. 
    63  */
    64 static int ffuart_last_close(int major, int minor, void *arg) 
     61 * the driver is polled, we don't have to do anything. If the driver
     62 * were interrupt driven, we'd disable interrupts here.
     63 */
     64static int ffuart_last_close(int major, int minor, void *arg)
    6565{
    6666    return 0;
     
    7474 * the character in lowest 8 bits of returned int.
    7575 */
    76 static int ffuart_read(int minor) 
     76static int ffuart_read(int minor)
    7777{
    7878    char c;
     
    9191        return -1;
    9292    }
    93    
    94     c  = ffuart->rbr & 0xff; 
    95    
     93
     94    c  = ffuart->rbr & 0xff;
     95
    9696    return c;
    9797}
    9898
    9999
    100 /* 
    101  * Write buffer to UART 
     100/*
     101 * Write buffer to UART
    102102 *
    103103 * return 1 on success, -1 on error
     
    125125            }
    126126        }
    127        
     127
    128128        c = (char) buf[i];
    129129#if ON_SKYEYE != 1
     
    141141#endif
    142142        ffuart->rbr = c;
    143        
     143
    144144        /* the TXRDY flag does not seem to update right away (is this true?) */
    145145        /* so we wait a bit before continuing */
     
    148148        }
    149149    }
    150    
     150
    151151    return 1;
    152152}
     
    156156{
    157157
    158  
     158
    159159    console_tbl *console_entry;
    160160    ffuart_reg_t  *ffuart;
     
    164164
    165165
    166    
     166
    167167    if (console_entry == NULL) {
    168168        return;
    169169    }
    170    
     170
    171171    ffuart = (ffuart_reg_t *)console_entry->ulCtrlPort1;
    172172    ffuart->lcr |= DLAB;
     
    192192
    193193/* This is for setting baud rate, bits, etc. */
    194 static int ffuart_set_attributes(int minor, const struct termios *t) 
     194static int ffuart_set_attributes(int minor, const struct termios *t)
    195195{
    196196    return 0;
     
    203203 */
    204204/***********************************************************************/
    205 /* 
     205/*
    206206 * Read from UART. This is used in the exit code, and can't
    207207 * rely on interrupts.
     
    214214
    215215/*
    216  * Write a character to the console. This is used by printk() and 
     216 * Write a character to the console. This is used by printk() and
    217217 * maybe other low level functions. It should not use interrupts or any
    218218 * RTEMS system calls. It needs to be very simple
  • c/src/lib/libcpu/arm/pxa255/include/ffuart.h

    rac7af4a r359e537  
    4848
    4949#endif
    50  
     50
  • c/src/lib/libcpu/arm/pxa255/irq/bsp_irq_asm.S

    rac7af4a r359e537  
    22 * PXA255 Interrupt handler by Yang Xi <hiyangxi@gmail.com>
    33 * Copyright (c) 2004 by Jay Monkman <jtm@lopgindog.com>
    4  *     
     4 *
    55 *  The license and distribution terms for this file may be
    66 *  found in the file LICENSE in this distribution or at
     
    1111
    1212#define __asm__
    13        
     13
    1414        .globl bsp_interrupt_dispatch
    1515bsp_interrupt_dispatch :
  • c/src/lib/libcpu/arm/pxa255/irq/bsp_irq_init.c

    rac7af4a r359e537  
    22 * PXA255 interrupt controller by Yang Xi <hiyangxi@gmail.com>
    33 * Copyright (c) 2004 by Jay Monkman <jtm@lopgindog.com>
    4  * 
     4 *
    55 *  The license and distribution terms for this file may be
    66 *  found in the file LICENSE in this distribution or at
     
    2121void (*IRQ_table[PRIMARY_IRQS])(uint32_t vector);
    2222
    23 /* 
    24  * Interrupt system initialization. Disable interrupts, clear 
     23/*
     24 * Interrupt system initialization. Disable interrupts, clear
    2525 * any that are pending.
    2626 */
  • c/src/lib/libcpu/arm/pxa255/irq/irq.c

    rac7af4a r359e537  
    22 * PXA255 Interrupt handler by Yang Xi <hiyangxi@gmail.com>
    33 * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
    4  *     
     4 *
    55 *  The license and distribution terms for this file may be
    66 *  found in the file LICENSE in this distribution or at
     
    3333{
    3434    rtems_interrupt_level level;
    35    
     35
    3636    if (!isValidInterrupt(irq->name)) {
    3737        return 0;
    3838    }
    39    
     39
    4040    /*
    41      * Check if default handler is actually connected. If not, issue 
    42      * an error. Note: irq->name is a number corresponding to the 
    43      * interrupt number .  We 
    44      * convert it to a long word offset to get source's vector register 
     41     * Check if default handler is actually connected. If not, issue
     42     * an error. Note: irq->name is a number corresponding to the
     43     * interrupt number .  We
     44     * convert it to a long word offset to get source's vector register
    4545     */
    4646        if (IRQ_table[irq->name] != dummy_handler) {
    4747        return 0;
    4848        }
    49    
     49
    5050    _CPU_ISR_Disable(level);
    51    
     51
    5252    /*
    5353     * store the new handler
    5454     */
    5555    IRQ_table[irq->name] = irq->hdl;
    56    
     56
    5757    /*
    5858     * unmask interrupt
     
    6161
    6262
    63    
     63
    6464    /*
    6565     * Enable interrupt on device
     
    6868        irq->on(irq);
    6969    }
    70    
     70
    7171    _CPU_ISR_Enable(level);
    72    
     72
    7373    return 1;
    7474}
    7575
    76 /* 
     76/*
    7777 * Remove and interrupt handler
    7878 */
     
    8080{
    8181    rtems_interrupt_level level;
    82  
     82
    8383    if (!isValidInterrupt(irq->name)) {
    8484        return 0;
     
    9797     */
    9898    XSCALE_INT_ICMR  =  XSCALE_INT_ICMR  & (~(1 << irq->name));
    99    
     99
    100100    /*
    101101     * Disable interrupt on device
     
    109109     */
    110110    IRQ_table[irq->name] = dummy_handler;
    111    
     111
    112112    _CPU_ISR_Enable(level);
    113113
  • c/src/lib/libcpu/arm/pxa255/irq/irq.h

    rac7af4a r359e537  
    22 * Interrupt handler Header file for PXA By Yang Xi <hiyangxi@gmail.com>
    33 * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
    4  *     
     4 *
    55 *  The license and distribution terms for this file may be
    66 *  found in the file LICENSE in this distribution or at
     
    2222 * Include some preprocessor value also used by assember code
    2323 */
    24  
     24
    2525#include <rtems.h>
    2626#include <pxa255.h>
     
    7878
    7979/*
    80  * function to get the current RTEMS irq handler for ptr->name. 
     80 * function to get the current RTEMS irq handler for ptr->name.
    8181 */
    8282int BSP_get_current_rtems_irq_handler   (rtems_irq_connect_data* ptr);
  • c/src/lib/libcpu/arm/pxa255/timer/timer.c

    rac7af4a r359e537  
    99 *  the number of microseconds since Timer_initialize() exitted.
    1010 *
    11  *  It is important that the timer start/stop overhead be determined 
     11 *  It is important that the timer start/stop overhead be determined
    1212 *  when porting or modifying this code.
    1313 *
     
    3030
    3131/*
    32  * Use the timer count register to measure. 
     32 * Use the timer count register to measure.
    3333 * The frequency of it is 3.4864MHZ
    3434 * The longest period we are able to capture is 4G/3.4864MHZ
     
    6363  else
    6464    total += 0xffffffff - tick_time; /*Round up but not overflow*/
    65      
     65
    6666  if ( benchmark_timer_find_average_overhead == true )
    6767    return total;          /*Counter cycles*/
  • c/src/lib/libcpu/arm/s3c2400/clock/support.c

    rac7af4a r359e537  
    4242uint32_t get_HCLK(void)
    4343{
    44     if (rCLKDIVN & 0x2) 
     44    if (rCLKDIVN & 0x2)
    4545        return get_FCLK()/2;
    4646    else
    47         return get_FCLK();   
     47        return get_FCLK();
    4848}
    4949
  • c/src/lib/libcpu/arm/s3c2400/include/s3c2400.h

    rac7af4a r359e537  
    473473} LCDCON1;
    474474
    475 typedef union { 
     475typedef union {
    476476  struct {
    477477    unsigned VSPW:6;    /* TFT: Vertical sync pulse width determines the */
  • c/src/lib/libcpu/arm/s3c2400/irq/bsp_irq_asm.S

    rac7af4a r359e537  
    1515
    1616#define __asm__
    17                
    18 /* 
    19  * Function to obtain, execute an IT handler and acknowledge the IT 
     17
     18/*
     19 * Function to obtain, execute an IT handler and acknowledge the IT
    2020 */
    2121
    2222        .globl bsp_interrupt_dispatch
    23        
    24 bsp_interrupt_dispatch :     
     23
     24bsp_interrupt_dispatch :
    2525
    2626        ldr     r0, =0x14400014  /* Read rINTOFFSET */
     
    2929        ldr     r0, =bsp_vector_table
    3030        ldr     r0, [r0, r1, LSL #2]    /* Read the address */
    31        
     31
    3232        stmdb     sp!,{lr}
    3333        ldr     lr, =IRQ_return         /* prepare the return from handler  */
    34        
     34
    3535        mov pc, r0
    3636
  • c/src/lib/libcpu/arm/s3c2400/irq/bsp_irq_init.c

    rac7af4a r359e537  
    1919extern void default_int_handler();
    2020
    21 void BSP_rtems_irq_mngt_init() 
     21void BSP_rtems_irq_mngt_init()
    2222{
    2323    long *vectorTable;
  • c/src/lib/libcpu/arm/s3c2400/irq/irq.c

    rac7af4a r359e537  
    4242    rtems_irq_hdl         *HdlTable;
    4343    rtems_interrupt_level  level;
    44    
     44
    4545    if (!isValidInterrupt(irq->name)) {
    4646        return 0;
     
    5454        return 0;
    5555    }
    56    
     56
    5757    rtems_interrupt_disable(level);
    5858
     
    7979    rtems_irq_hdl         *HdlTable;
    8080    rtems_interrupt_level  level;
    81  
     81
    8282    if (!isValidInterrupt(irq->name)) {
    8383        return 0;
     
    104104     */
    105105    *(HdlTable + irq->name) = default_int_handler;
    106          
     106
    107107    rtems_interrupt_enable(level);
    108108
  • c/src/lib/libcpu/arm/s3c2400/irq/irq.h

    rac7af4a r359e537  
    2424 * Include some preprocessor value also used by assember code
    2525 */
    26  
     26
    2727#include <rtems.h>
    2828#include <s3c2400.h>
     
    4242#define BSP_EINT6             6
    4343#define BSP_EINT7             7
    44 #define BSP_INT_TICK          8 
    45 #define BSP_INT_WDT           9 
    46 #define BSP_INT_TIMER0       10   
    47 #define BSP_INT_TIMER1       11   
    48 #define BSP_INT_TIMER2       12   
    49 #define BSP_INT_TIMER3       13   
    50 #define BSP_INT_TIMER4       14   
    51 #define BSP_INT_UERR01       15   
    52 #define _res0                16       
    53 #define BSP_INT_DMA0         17 
    54 #define BSP_INT_DMA1         18 
    55 #define BSP_INT_DMA2         19 
    56 #define BSP_INT_DMA3         20 
    57 #define BSP_INT_MMC          21 
    58 #define BSP_INT_SPI          22 
    59 #define BSP_INT_URXD0        23   
    60 #define BSP_INT_URXD1        24   
    61 #define BSP_INT_USBD         25 
    62 #define BSP_INT_USBH         26 
    63 #define BSP_INT_IIC          27 
    64 #define BSP_INT_UTXD0        28   
    65 #define BSP_INT_UTXD1        29   
    66 #define BSP_INT_RTC          30 
    67 #define BSP_INT_ADC          31 
    68 #define BSP_MAX_INT          32 
     44#define BSP_INT_TICK          8
     45#define BSP_INT_WDT           9
     46#define BSP_INT_TIMER0       10
     47#define BSP_INT_TIMER1       11
     48#define BSP_INT_TIMER2       12
     49#define BSP_INT_TIMER3       13
     50#define BSP_INT_TIMER4       14
     51#define BSP_INT_UERR01       15
     52#define _res0                16
     53#define BSP_INT_DMA0         17
     54#define BSP_INT_DMA1         18
     55#define BSP_INT_DMA2         19
     56#define BSP_INT_DMA3         20
     57#define BSP_INT_MMC          21
     58#define BSP_INT_SPI          22
     59#define BSP_INT_URXD0        23
     60#define BSP_INT_URXD1        24
     61#define BSP_INT_USBD         25
     62#define BSP_INT_USBH         26
     63#define BSP_INT_IIC          27
     64#define BSP_INT_UTXD0        28
     65#define BSP_INT_UTXD1        29
     66#define BSP_INT_RTC          30
     67#define BSP_INT_ADC          31
     68#define BSP_MAX_INT          32
    6969
    7070extern void *bsp_vector_table;
    7171#define VECTOR_TABLE &bsp_vector_table
    72  
     72
    7373/*
    7474 * Type definition for RTEMS managed interrupts
     
    102102     * RTEMS may well need such a function when restoring normal interrupt
    103103     * processing after a debug session.
    104      * 
    105      */
    106     rtems_irq_enable            on;     
     104     *
     105     */
     106    rtems_irq_enable            on;
    107107
    108108    /*
     
    179179 *      5) restore the C scratch registers...
    180180 *      6) restore initial execution flow
    181  * 
     181 *
    182182 */
    183183int BSP_install_rtems_irq_handler       (const rtems_irq_connect_data*);
  • c/src/lib/libcpu/arm/s3c2400/timer/timer.c

    rac7af4a r359e537  
    1515 *  the number of microseconds since benchmark_timer_initialize() exitted.
    1616 *
    17  *  It is important that the timer start/stop overhead be determined 
     17 *  It is important that the timer start/stop overhead be determined
    1818 *  when porting or modifying this code.
    1919 *
     
    3030bool benchmark_timer_find_average_overhead;
    3131
    32    
     32
    3333/*
    3434 * Set up Timer 1
     
    3838    uint32_t cr;
    3939
    40     /* stop TIMER1*/ 
     40    /* stop TIMER1*/
    4141    cr=rTCON & 0xFFFFF0FF;
    4242    rTCON=(cr | (0x0 << 8));
     
    4646    rTCFG1=(cr | (0<<4));
    4747
    48     /* input freq=PLCK/2 Mhz*/ 
    49     g_freq = get_PCLK() / 2000; 
     48    /* input freq=PLCK/2 Mhz*/
     49    g_freq = get_PCLK() / 2000;
    5050    rTCNTB1 = 0xFFFF;
    5151
    52     /* start TIMER1 with manual reload */ 
     52    /* start TIMER1 with manual reload */
    5353    cr=rTCON & 0xFFFFF0FF;
    5454    rTCON=(cr | (0x1 << 9));
    5555    rTCON=(cr | (0x1 << 8));
    56  
     56
    5757    g_start =  rTCNTO1;
    5858}
     
    8484     *  interrupts.
    8585     */
    86    
     86
    8787    total = (g_start - t);
    8888
    8989    /* convert to microseconds */
    90     total = (total*1000) / g_freq; 
     90    total = (total*1000) / g_freq;
    9191
    9292    if ( benchmark_timer_find_average_overhead == 1 ) {
    93         return (int) total; 
     93        return (int) total;
    9494    } else if ( total < LEAST_VALID ) {
    95         return 0;       
     95        return 0;
    9696    }
    9797
  • c/src/lib/libcpu/arm/s3c2410/irq/irq.h

    rac7af4a r359e537  
    2424 * Include some preprocessor value also used by assember code
    2525 */
    26  
     26
    2727#include <rtems.h>
    2828#include <s3c2410.h>
     
    4141#define BSP_EINT8_23          5
    4242#define BSP_nBATT_FLT         7
    43 #define BSP_INT_TICK          8 
    44 #define BSP_INT_WDT           9 
    45 #define BSP_INT_TIMER0       10   
    46 #define BSP_INT_TIMER1       11   
    47 #define BSP_INT_TIMER2       12   
    48 #define BSP_INT_TIMER3       13   
    49 #define BSP_INT_TIMER4       14   
    50 #define BSP_INT_UART2        15   
    51 #define BSP_INT_LCD          16       
    52 #define BSP_INT_DMA0         17 
    53 #define BSP_INT_DMA1         18 
    54 #define BSP_INT_DMA2         19 
    55 #define BSP_INT_DMA3         20 
    56 #define BSP_INT_SDI          21 
    57 #define BSP_INT_SPI0         22 
    58 #define BSP_INT_UART1        23   
    59 #define BSP_INT_USBD         25 
    60 #define BSP_INT_USBH         26 
    61 #define BSP_INT_IIC          27 
    62 #define BSP_INT_UART0        28   
    63 #define BSP_INT_SPI1         29   
    64 #define BSP_INT_RTC          30 
    65 #define BSP_INT_ADC          31 
    66 #define BSP_MAX_INT          32 
     43#define BSP_INT_TICK          8
     44#define BSP_INT_WDT           9
     45#define BSP_INT_TIMER0       10
     46#define BSP_INT_TIMER1       11
     47#define BSP_INT_TIMER2       12
     48#define BSP_INT_TIMER3       13
     49#define BSP_INT_TIMER4       14
     50#define BSP_INT_UART2        15
     51#define BSP_INT_LCD          16
     52#define BSP_INT_DMA0         17
     53#define BSP_INT_DMA1         18
     54#define BSP_INT_DMA2         19
     55#define BSP_INT_DMA3         20
     56#define BSP_INT_SDI          21
     57#define BSP_INT_SPI0         22
     58#define BSP_INT_UART1        23
     59#define BSP_INT_USBD         25
     60#define BSP_INT_USBH         26
     61#define BSP_INT_IIC          27
     62#define BSP_INT_UART0        28
     63#define BSP_INT_SPI1         29
     64#define BSP_INT_RTC          30
     65#define BSP_INT_ADC          31
     66#define BSP_MAX_INT          32
    6767
    6868extern void *bsp_vector_table;
    6969#define VECTOR_TABLE &bsp_vector_table
    70  
     70
    7171/*
    7272 * Type definition for RTEMS managed interrupts
     
    100100     * RTEMS may well need such a function when restoring normal interrupt
    101101     * processing after a debug session.
    102      * 
    103      */
    104     rtems_irq_enable            on;     
     102     *
     103     */
     104    rtems_irq_enable            on;
    105105
    106106    /*
     
    177177 *      5) restore the C scratch registers...
    178178 *      6) restore initial execution flow
    179  * 
     179 *
    180180 */
    181181int BSP_install_rtems_irq_handler       (const rtems_irq_connect_data*);
  • c/src/lib/libcpu/arm/shared/arm920/mmu.c

    rac7af4a r359e537  
    109109        while (sects > 0) {
    110110            lvl1_base[vbase] = MMU_SET_LVL1_SECT(pbase << 20,
    111                                                  MMU_SECT_AP_ALL, 
    112                                                  0, 
    113                                                  c, 
     111                                                 MMU_SECT_AP_ALL,
     112                                                 0,
     113                                                 c,
    114114                                                 b);
    115115            pbase++;
     
    250250    mmu_set_ctrl(reg);
    251251}
    252    
     252
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