Changeset 359e537 in rtems


Ignore:
Timestamp:
11/30/09 05:09:41 (12 years ago)
Author:
Ralf Corsepius <ralf.corsepius@…>
Branches:
4.10, 4.11, 5, master
Children:
023f1dd9
Parents:
ac7af4a
Message:

Whitespace removal.

Location:
c/src/lib
Files:
199 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/i386/i386ex/timer/timer.c

    rac7af4a r359e537  
    1 /* 
     1/*
    22 *  COPYRIGHT (c) 1989-1999.
    33 *  On-Line Applications Research Corporation (OAR).
  • c/src/lib/libbsp/i386/pc386/clock/ckinit.c

    rac7af4a r359e537  
    8585   * Get nanoseconds using Pentium-compatible TSC register
    8686   ******/
    87  
     87
    8888  uint64_t                 diff_nsec;
    8989
     
    107107  return (uint32_t)diff_nsec;
    108108}
    109  
     109
    110110uint32_t bsp_clock_nanoseconds_since_last_tick_i8254(void)
    111111{
     
    180180
    181181  for (i = rtems_clock_get_ticks_per_second() * pc386_isrs_per_tick;
    182        i != 0; --i ) {   
     182       i != 0; --i ) {
    183183    /* We know we've just completed a tick when timer goes from low to high */
    184184    then_lsb = then_msb = 0xff;
     
    201201  printk( "CPU clock at %u MHz\n", (uint32_t)(pc586_tsc_per_tick / 1000000));
    202202#endif
    203  
     203
    204204  pc586_tsc_per_tick /= rtems_clock_get_ticks_per_second();
    205205}
     
    219219
    220220  #if 0
    221     printk( "configured usecs per tick=%d \n", 
     221    printk( "configured usecs per tick=%d \n",
    222222      rtems_configuration_get_microseconds_per_tick() );
    223223    printk( "Microseconds per ISR =%d\n", pc386_microseconds_per_isr );
     
    268268  bool use_tsc = false;
    269269  bool use_8254 = false;
    270  
     270
    271271  #if (CLOCK_DRIVER_USE_TSC == 1)
    272272    use_tsc = true;
     
    276276    use_8254 = true;
    277277  #endif
    278  
     278
    279279  if ( !use_tsc && !use_8254 ) {
    280280    if ( x86_has_tsc() ) use_tsc  = true;
     
    285285    /* printk( "Use 8254\n" ); */
    286286    Clock_driver_support_at_tick = Clock_driver_support_at_tick_empty;
    287     Clock_driver_nanoseconds_since_last_tick = 
     287    Clock_driver_nanoseconds_since_last_tick =
    288288      bsp_clock_nanoseconds_since_last_tick_i8254;
    289289  } else {
    290290    /* printk( "Use TSC\n" ); */
    291291    Clock_driver_support_at_tick = Clock_driver_support_at_tick_tsc;
    292     Clock_driver_nanoseconds_since_last_tick = 
     292    Clock_driver_nanoseconds_since_last_tick =
    293293      bsp_clock_nanoseconds_since_last_tick_tsc;
    294294  }
  • c/src/lib/libbsp/i386/pc386/console/console.c

    rac7af4a r359e537  
    229229{
    230230  rtems_status_code status;
    231  
    232  
     231
     232
    233233  /* Initialize the KBD interface */
    234234  kbd_init();
  • c/src/lib/libbsp/i386/pc386/console/fb_vga.c

    rac7af4a r359e537  
    8787    rtems_fatal_error_occurred( status );
    8888  }
    89  
     89
    9090  return RTEMS_SUCCESSFUL;
    9191}
     
    103103      /* restore previous state.  for VGA this means return to text mode.
    104104       * leave out if graphics hardware has been initialized in
    105        * frame_buffer_initialize() 
     105       * frame_buffer_initialize()
    106106       */
    107107      ega_hwinit();
    108       printk( "FBVGA open called.\n" );     
     108      printk( "FBVGA open called.\n" );
    109109      return RTEMS_SUCCESSFUL;
    110110  }
    111  
     111
    112112  return RTEMS_UNSATISFIED;
    113113}
     
    146146  rw_args->bytes_moved = ((rw_args->offset + rw_args->count) > fb_fix.smem_len ) ? (fb_fix.smem_len - rw_args->offset) : rw_args->count;
    147147  memcpy(rw_args->buffer, (const void *) (fb_fix.smem_start + rw_args->offset), rw_args->bytes_moved);
    148   return RTEMS_SUCCESSFUL;   
     148  return RTEMS_SUCCESSFUL;
    149149}
    150150
     
    161161  rw_args->bytes_moved = ((rw_args->offset + rw_args->count) > fb_fix.smem_len ) ? (fb_fix.smem_len - rw_args->offset) : rw_args->count;
    162162  memcpy( (void *) (fb_fix.smem_start + rw_args->offset), rw_args->buffer, rw_args->bytes_moved);
    163   return RTEMS_SUCCESSFUL;       
     163  return RTEMS_SUCCESSFUL;
    164164}
    165165
  • c/src/lib/libbsp/i386/pc386/console/ps2_mouse.c

    rac7af4a r359e537  
    9797
    9898static rtems_irq_connect_data ps2_isr_data = { AUX_IRQ,
    99                                                ps2_mouse_interrupt, 
     99                                               ps2_mouse_interrupt,
    100100                                               0,
    101                                                isr_on, 
    102                                                isr_off, 
     101                                               isr_on,
     102                                               isr_off,
    103103                                               isr_is_on };
    104104
  • c/src/lib/libbsp/i386/pc386/ide/ide.c

    rac7af4a r359e537  
    8888  volatile uint8_t status;
    8989  int              polls;
    90  
     90
    9191  do
    9292  {
     
    122122  volatile uint8_t status;
    123123  int              polls;
    124  
     124
    125125  do
    126126  {
     
    129129    {
    130130      inport_byte (port + IDE_REGISTER_STATUS, status);
    131    
     131
    132132      if (((status & IDE_REGISTER_STATUS_BSY) == 0) &&
    133133          (status & IDE_REGISTER_STATUS_DRQ))
     
    230230    char*       p = &model_number[0];
    231231    bool        data_ready;
    232    
     232
    233233    memset(model_number, 0, sizeof(model_number));
    234234
     
    241241
    242242    outport_byte(port+IDE_REGISTER_COMMAND, 0x00);
    243    
     243
    244244    if (!pc386_ide_status_busy (port, PC386_IDE_PROBE_TIMEOUT,
    245245                                &status, pc386_ide_prestart_sleep))
    246246      continue;
    247    
     247
    248248    inport_byte(port+IDE_REGISTER_STATUS,        status);
    249249    inport_byte(port+IDE_REGISTER_ERROR,         error);
     
    295295    if (!data_ready)
    296296      continue;
    297    
     297
    298298    byte = 0;
    299299    while (byte < 512)
    300300    {
    301301      uint16_t word;
    302      
     302
    303303      if (pc386_ide_show && ((byte % 16) == 0))
    304304        printk("\n %04x : ", byte);
    305      
     305
    306306      inport_word(port+IDE_REGISTER_DATA, word);
    307307
     
    315315      if (byte == 12)
    316316        sectors = word;
    317      
     317
    318318      if (byte >= 54 && byte < (54 + 40))
    319319      {
     
    326326      if (byte == (47 * 2))
    327327        max_multiple_sectors = word & 0xff;
    328      
     328
    329329      if (byte == (49 * 2))
    330330        capabilities = word;
    331      
     331
    332332      if (byte == (59 * 2))
    333333      {
     
    340340      if (byte == (61 * 2))
    341341        lba_sectors |= word << 16;
    342      
     342
    343343      byte += 2;
    344344    }
    345    
     345
    346346    if (pc386_ide_show)
    347347      printk("\nbytes read = %d\n", byte);
     
    360360
    361361      size /= 2;
    362      
     362
    363363      if (size > (1024 * 1024))
    364364      {
     
    379379      left = size / 10;
    380380      right = size % 10;
    381      
     381
    382382      p--;
    383383      while (*p == ' ')
     
    391391             heads, cylinders, sectors, max_multiple_sectors * 512);
    392392    }
    393    
     393
    394394#if IDE_CLEAR_MULTI_SECTOR_COUNT
    395395    if (max_multiple_sectors)
     
    418418    }
    419419#endif
    420    
     420
    421421    outport_byte(port+IDE_REGISTER_DEVICE_CONTROL,
    422422                 IDE_REGISTER_DEVICE_CONTROL_nIEN);
     
    425425
    426426  pc386_ide_timeout = PC386_IDE_TASKING_TIMEOUT;
    427  
     427
    428428  /*
    429429   * FIXME: enable interrupts, if needed
     
    536536    uint8_t  status_val;
    537537    int      b;
    538    
     538
    539539    if (!pc386_ide_status_data_ready (port, pc386_ide_timeout,
    540540                                      &status_val, pc386_ide_tasking_sleep))
     
    545545      return;
    546546    }
    547    
     547
    548548    if (status_val & IDE_REGISTER_STATUS_ERR)
    549549    {
     
    554554
    555555    lbuf = (uint16_t*)((uint8_t*)(bufs[(*cbuf)].buffer) + (*pos));
    556  
     556
    557557    for (b = 0; b < (ATA_SECTOR_SIZE / 2); b++)
    558558    {
     
    615615    uint8_t  status_val;
    616616    int      b;
    617    
     617
    618618    if (!pc386_ide_status_data_ready (port, pc386_ide_timeout,
    619619                                      &status_val, pc386_ide_tasking_sleep))
     
    624624      return;
    625625    }
    626    
     626
    627627    if (status_val & IDE_REGISTER_STATUS_ERR)
    628628    {
     
    631631      return;
    632632    }
    633    
     633
    634634    lbuf = (uint16_t*)(((uint8_t*)bufs[*cbuf].buffer) + (*pos));
    635  
     635
    636636    for (b = 0; b < (ATA_SECTOR_SIZE / 2); b++)
    637637    {
  • c/src/lib/libbsp/i386/pc386/ide/idecfg.c

    rac7af4a r359e537  
    7878  bool ide2 = IDE2_DEFAULT;
    7979  const char* ide;
    80  
     80
    8181  /*
    8282   * Can have:
     
    8484   */
    8585  ide = bsp_cmdline_arg ("--ide=");
    86  
     86
    8787  if (ide)
    8888  {
     
    9292     */
    9393    ide1 = ide2 = false;
    94    
     94
    9595    ide += sizeof ("--ide=") - 1;
    96    
     96
    9797    for (i = 0; i < 3; i++)
    9898    {
     
    134134   */
    135135  ide = bsp_cmdline_arg ("--ide-show");
    136  
     136
    137137  if (ide)
    138138    pc386_ide_show = true;
  • c/src/lib/libbsp/i386/pc386/start/start.S

    rac7af4a r359e537  
    105105        cmp     $0x2badb002,eax
    106106        jne     2f
    107        
     107
    108108        /* We have multiboot info; let's hope DS and ES are OK... */
    109109        movl    ebx, SYM(_boot_multiboot_info_p)
     
    232232        movl    $SYM (no_sse_msg), 0(esp)
    233233        jmp     SYM(_sse_panic)
    234 1:     
     2341:
    235235#ifdef __SSE2__
    236236        testl   $0x04000000, eax
     
    302302        .byte 0
    303303        .endr
    304        
     304
    305305        PUBLIC(_stack_size)
    306306SYM(_stack_size):
  • c/src/lib/libbsp/i386/pc386/startup/bspgetworkarea.c

    rac7af4a r359e537  
    9595      }
    9696    }
    97      
     97
    9898    topAddr = (i-1)*1024*1024 - 4;
    9999  } else {
  • c/src/lib/libbsp/i386/pc386/startup/ldsegs.S

    rac7af4a r359e537  
    223223        .word 0,0,0,0
    224224        .endr
    225                
     225
    226226/*---------------------------------------------------------------------------+
    227227| Descriptor of IDT
     
    232232        .word  (256*8 - 1)
    233233        .long  SYM (Interrupt_descriptor_table)
    234        
     234
    235235END_DATA
    236236
  • c/src/lib/libbsp/m32c/m32cbsp/start/start.S

    rac7af4a r359e537  
    44All rights reserved.
    55
    6 Redistribution and use in source and binary forms, with or without 
    7 modification, are permitted provided that the following conditions are met: 
     6Redistribution and use in source and binary forms, with or without
     7modification, are permitted provided that the following conditions are met:
    88
    9     Redistributions of source code must retain the above copyright 
     9    Redistributions of source code must retain the above copyright
    1010    notice, this list of conditions and the following disclaimer.
    1111
     
    1414    documentation and/or other materials provided with the distribution.
    1515
    16     The name of Red Hat Incorporated may not be used to endorse 
    17     or promote products derived from this software without specific 
     16    The name of Red Hat Incorporated may not be used to endorse
     17    or promote products derived from this software without specific
    1818    prior written permission.
    1919
    20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
    21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
     20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
     21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
    2222IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
    2323DISCLAIMED.  IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
    2424DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
    2525(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
    26 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 
     26LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
    2727ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
    2828(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
    29 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
     29SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    3030
    3131*/
     
    3535#warning You need to pass a NULL.
    3636#warning Please check and remove these errors.
    37        
     37
    3838#if defined(__r8c_cpu__) || defined(__m16c_cpu__)
    3939#define A16
  • c/src/lib/libbsp/m32c/m32cbsp/startup/crtn.S

    rac7af4a r359e537  
    44All rights reserved.
    55
    6 Redistribution and use in source and binary forms, with or without 
    7 modification, are permitted provided that the following conditions are met: 
     6Redistribution and use in source and binary forms, with or without
     7modification, are permitted provided that the following conditions are met:
    88
    9     Redistributions of source code must retain the above copyright 
     9    Redistributions of source code must retain the above copyright
    1010    notice, this list of conditions and the following disclaimer.
    1111
     
    1414    documentation and/or other materials provided with the distribution.
    1515
    16     The name of Red Hat Incorporated may not be used to endorse 
    17     or promote products derived from this software without specific 
     16    The name of Red Hat Incorporated may not be used to endorse
     17    or promote products derived from this software without specific
    1818    prior written permission.
    1919
    20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
    21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
     20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
     21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
    2222IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
    2323DISCLAIMED.  IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
    2424DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
    2525(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
    26 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 
     26LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
    2727ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
    2828(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
    29 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
     29SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    3030
    3131*/
  • c/src/lib/libbsp/m32c/m32cbsp/timer/timer.c

    rac7af4a r359e537  
    3838  benchmark_timer_interrupts = 0;
    3939  _set_var_vect (timer_ra_interrupt, ivec_timer_a0);
    40   TA0MR = 0x00; 
    41   TA0   = 0xffff; 
    42   TA0IC = 0x05; 
    43   TABSR = 0x55; 
     40  TA0MR = 0x00;
     41  TA0   = 0xffff;
     42  TA0IC = 0x05;
     43  TABSR = 0x55;
    4444}
    4545
     
    5050  count = 0xFFFF - TA0;
    5151  count += benchmark_timer_interrupts * 0xFFFFL;
    52  
     52
    5353  if (!benchmark_timer_find_average_overhead) {
    5454    if ( count > benchmark_timer_overhead )
  • c/src/lib/libbsp/m32r/m32rsim/start/start.S

    rac7af4a r359e537  
    2626        seth    r3, #shigh(_end)
    2727        add3    r3, r3, #low(_end)      ; R3 = end of BSS + 1
    28        
     28
    2929        sub     r3, r2          ; R3 = BSS size in bytes
    3030        mv      r4, r3
  • c/src/lib/libbsp/nios2/nios2_iss/console/console.c

    rac7af4a r359e537  
    11/*
    22 *  This file implements simple console IO via JTAG UART.
    3  * 
     3 *
    44 *  Based on no_cpu/console.c
    55 *  COPYRIGHT (c) 1989-1999.
     
    2626 *
    2727 *  If a character is available, this routine reads it and stores
    28  *  it in 
     28 *  it in
    2929 *  reads the character and stores
    3030 *
     
    9393
    9494void console_outbyte_polled(
    95   int  port, 
     95  int  port,
    9696  char ch
    9797)
  • c/src/lib/libbsp/nios2/nios2_iss/timer/timer.c

    rac7af4a r359e537  
    7575
    7676  /* This is the most safe place for resetting the overflow
    77      counter - just _after_ we reset the timer. Depending 
    78      on the SOPC configuration, the counter may not be 
     77     counter - just _after_ we reset the timer. Depending
     78     on the SOPC configuration, the counter may not be
    7979     stoppable and it doesn't make sense to assume that
    8080     there is any "safe" period before resetting. */
     
    130130
    131131  if(benchmark_timer_find_average_overhead != TRUE) total-= AVG_OVERHEAD;
    132  
     132
    133133  return total;
    134134}
  • c/src/lib/libbsp/sh/gensh1/start/start.S

    rac7af4a r359e537  
    2525#warning The call is "void boot_card(const char* cmdline);"
    2626#warning Please check and remove these warnings.
    27        
     27
    2828        BEGIN_CODE
    2929        PUBLIC(start)
  • c/src/lib/libbsp/sh/gensh2/start/start.S

    rac7af4a r359e537  
    3636#warning The call is "void boot_card(const char* cmdline);"
    3737#warning Please check and remove these warnings.
    38        
     38
    3939        BEGIN_CODE
    4040        PUBLIC(start)
  • c/src/lib/libbsp/sh/gensh4/start/start.S

    rac7af4a r359e537  
    4444#warning The call is "void boot_card(const char* cmdline);"
    4545#warning Please check and remove these warnings.
    46        
     46
    4747        BEGIN_CODE
    4848        PUBLIC(start)
  • c/src/lib/libbsp/sh/shsim/start/start.S

    rac7af4a r359e537  
    2626#warning You need to pass a NULL.
    2727#warning Please check and remove these warnings.
    28        
     28
    2929        BEGIN_CODE
    3030        PUBLIC(start)
     
    6363        mov.l main_k,r0
    6464        jsr @r0
    65        
     65
    6666
    6767        ! call exit
  • c/src/lib/libbsp/shared/bspclean.c

    rac7af4a r359e537  
    3838  #if (BSP_PRESS_KEY_FOR_RESET) || (BSP_RESET_BOARD_AT_EXIT)
    3939    bsp_reset();
    40   #endif 
     40  #endif
    4141}
  • c/src/lib/libbsp/shared/bspgetworkarea.c

    rac7af4a r359e537  
    6969   */
    7070  #ifdef BSP_GET_WORK_AREA_DEBUG
    71     { 
     71    {
    7272      void *sp = __builtin_frame_address(0);
    7373      void *end = *work_area_start + *work_area_size;
  • c/src/lib/libbsp/shared/bspinit.c

    rac7af4a r359e537  
    3939  {
    4040    cmdline = malloc (strlen (boot_cmdline) + 1);
    41  
     41
    4242    if (cmdline)
    4343    {
     
    6363      {
    6464        int a;
    65        
     65
    6666        command = cmdline;
    6767        argv[0] = command;
     
    7777    }
    7878  }
    79  
     79
    8080#ifdef RTEMS_NETWORKING
    8181  rtems_bsdnet_initialize_network ();
     
    8383
    8484  result = main (argc, argv);
    85  
     85
    8686  free (argv);
    8787  free (cmdline);
  • c/src/lib/libbsp/shared/include/irq-config.h

    rac7af4a r359e537  
    88
    99/*
    10  * Based on concepts of Pavel Pisa, Till Straumann and Eric Valette. 
     10 * Based on concepts of Pavel Pisa, Till Straumann and Eric Valette.
    1111 *
    1212 * Copyright (c) 2008, 2009
  • c/src/lib/libbsp/shared/include/irq-generic.h

    rac7af4a r359e537  
    88
    99/*
    10  * Based on concepts of Pavel Pisa, Till Straumann and Eric Valette. 
     10 * Based on concepts of Pavel Pisa, Till Straumann and Eric Valette.
    1111 *
    1212 * Copyright (c) 2008, 2009
  • c/src/lib/libbsp/shared/include/stackalloc.h

    rac7af4a r359e537  
    4242 * @code
    4343 * #include <bsp/stackalloc.h>
    44  * 
     44 *
    4545 * #define CONFIGURE_INIT
    4646 *
  • c/src/lib/libbsp/shared/src/irq-generic.c

    rac7af4a r359e537  
    88
    99/*
    10  * Based on concepts of Pavel Pisa, Till Straumann and Eric Valette. 
     10 * Based on concepts of Pavel Pisa, Till Straumann and Eric Valette.
    1111 *
    1212 * Copyright (c) 2008, 2009
  • c/src/lib/libcpu/arm/at91rm9200/clock/clock.c

    rac7af4a r359e537  
    3535{
    3636    /* enable timer interrupt */
    37     ST_REG(ST_IER) = ST_SR_PITS; 
     37    ST_REG(ST_IER) = ST_SR_PITS;
    3838}
    3939
     
    5959{
    6060    /* check timer interrupt */
    61     return ST_REG(ST_IMR) & ST_SR_PITS; 
     61    return ST_REG(ST_IMR) & ST_SR_PITS;
    6262}
    6363
     
    6565
    6666/* Replace the first value with the clock's interrupt name. */
    67 rtems_irq_connect_data clock_isr_data = {AT91RM9200_INT_SYSIRQ,   
     67rtems_irq_connect_data clock_isr_data = {AT91RM9200_INT_SYSIRQ,
    6868                                         (rtems_irq_hdl)Clock_isr,
    6969                                         clock_isr_on,
     
    8989  st_pimr_reload = st_pimr_value;
    9090
    91   /* read the status to clear the int */ 
     91  /* read the status to clear the int */
    9292  st_str = ST_REG(ST_SR);
    93    
     93
    9494  /* set priority */
    95   AIC_SMR_REG(AIC_SMR_SYSIRQ) = AIC_SMR_PRIOR(0x7); 
     95  AIC_SMR_REG(AIC_SMR_SYSIRQ) = AIC_SMR_PRIOR(0x7);
    9696
    9797  /* set the timer value */
  • c/src/lib/libcpu/arm/at91rm9200/dbgu/dbgu.c

    rac7af4a r359e537  
    22 *  Console driver for AT91RM9200 DBGU port
    33 *
    4  *  This driver uses the shared console driver in 
     4 *  This driver uses the shared console driver in
    55 *  ...../libbsp/shared/console.c
    66 *
     
    3939
    4040/* Pointers to functions for handling the UART. */
    41 console_fns dbgu_fns = 
    42 { 
     41console_fns dbgu_fns =
     42{
    4343    libchip_serial_default_probe,
    4444    dbgu_first_open,
     
    5555/*********************************************************************/
    5656
    57 /* 
     57/*
    5858 * This is called the first time each device is opened. Since
    59  * the driver is polled, we don't have to do anything. If the driver 
    60  * were interrupt driven, we'd enable interrupts here. 
    61  */
    62 static int dbgu_first_open(int major, int minor, void *arg) 
     59 * the driver is polled, we don't have to do anything. If the driver
     60 * were interrupt driven, we'd enable interrupts here.
     61 */
     62static int dbgu_first_open(int major, int minor, void *arg)
    6363{
    6464    return 0;
     
    6666
    6767
    68 /* 
     68/*
    6969 * This is called the last time each device is closed.  Since
    70  * the driver is polled, we don't have to do anything. If the driver 
    71  * were interrupt driven, we'd disable interrupts here. 
    72  */
    73 static int dbgu_last_close(int major, int minor, void *arg) 
     70 * the driver is polled, we don't have to do anything. If the driver
     71 * were interrupt driven, we'd disable interrupts here.
     72 */
     73static int dbgu_last_close(int major, int minor, void *arg)
    7474{
    7575    return 0;
     
    8383 * the character in lowest 8 bits of returned int.
    8484 */
    85 static int dbgu_read(int minor) 
     85static int dbgu_read(int minor)
    8686{
    8787    char c;
     
    100100        return -1;
    101101    }
    102    
    103     c  = dbgu->rhr & 0xff; 
    104    
     102
     103    c  = dbgu->rhr & 0xff;
     104
    105105    return c;
    106106}
    107107
    108108
    109 /* 
    110  * Write buffer to UART 
     109/*
     110 * Write buffer to UART
    111111 *
    112112 * return 1 on success, -1 on error
     
    134134            }
    135135        }
    136        
     136
    137137        c = (char) buf[i];
    138138        dbgu->thr = c;
    139        
     139
    140140        /* the TXRDY flag does not seem to update right away (is this true?) */
    141141        /* so we wait a bit before continuing */
     
    144144        }
    145145    }
    146    
     146
    147147    return 1;
    148148}
     
    187187
    188188/* This is for setting baud rate, bits, etc. */
    189 static int dbgu_set_attributes(int minor, const struct termios *t) 
     189static int dbgu_set_attributes(int minor, const struct termios *t)
    190190{
    191191    return 0;
     
    198198 */
    199199/***********************************************************************/
    200 /* 
     200/*
    201201 * Read from UART. This is used in the exit code, and can't
    202202 * rely on interrupts.
     
    209209
    210210/*
    211  * Write a character to the console. This is used by printk() and 
     211 * Write a character to the console. This is used by printk() and
    212212 * maybe other low level functions. It should not use interrupts or any
    213213 * RTEMS system calls. It needs to be very simple
  • c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200.h

    rac7af4a r359e537  
    3333
    3434/* Control Register - 32 of them */
    35 #define AIC_CTL_BASE            0xFFFFF100     
     35#define AIC_CTL_BASE            0xFFFFF100
    3636#define AIC_CTL_REG(_x_)        *(vulong *)(AIC_CTL_BASE + (_x_ & 0x7f))
    3737
     
    104104#define AIC_SMR_PRIOR(_x_)      ((_x_ & 0x07) << 0)
    105105#define AIC_SMR_SRC_LVL_LOW     (0 << 5)        /* Are these right? docs don't say which is high/low     */
    106 #define AIC_SMR_SRC_EDGE_LOW    (1 << 5)       
    107 #define AIC_SMR_SRC_LVL_HI      (2 << 5)       
    108 #define AIC_SMR_SRC_EDGE_HI     (3 << 5)       
     106#define AIC_SMR_SRC_EDGE_LOW    (1 << 5)
     107#define AIC_SMR_SRC_LVL_HI      (2 << 5)
     108#define AIC_SMR_SRC_EDGE_HI     (3 << 5)
    109109
    110110/**************************************************************************/
     
    193193 * set of these registers starting at offset 0x100 from it's
    194194 * base address: DBGU, SPI, USART and SSC
    195  * To access the DMA for a peripheral, use the macro for that 
     195 * To access the DMA for a peripheral, use the macro for that
    196196 * peripheral but with these register offsets
    197197 **************************************************************************/
  • c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_dbgu.h

    rac7af4a r359e537  
    44 * Copyright (c) 2003 by Cogent Computer Systems
    55 * Written by Mike Kelly <mike@cogcomp.com>
    6  *     
     6 *
    77 *  The license and distribution terms for this file may be
    88 *  found in the file LICENSE in this distribution or at
  • c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_emac.h

    rac7af4a r359e537  
    44 * Copyright (c) 2003 by Cogent Computer Systems
    55 * Written by Mike Kelly <mike@cogcomp.com>
    6  *     
     6 *
    77 *  The license and distribution terms for this file may be
    88 *  found in the file LICENSE in this distribution or at
     
    105105#define EMAC_TSR_COMP   BIT5          /* 1 = Transmit complete */
    106106#define EMAC_TSR_UND    BIT6          /* 1 = Transmit underrun */
    107  
     107
    108108/* Receive Status Register, EMAC_RSR, Offset 0x20 */
    109109#define EMAC_RSR_BNA    BIT0          /* 1 = Buffer not available */
     
    138138#define EMAC_MAN_READ           (0x2 << 28)           /* Transfer is a read */
    139139#define EMAC_MAN_HIGH           BIT30                 /* Must be set */
    140 #define EMAC_MAN_LOW            BIT31 
     140#define EMAC_MAN_LOW            BIT31
    141141
    142142/*
  • c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_gpio.h

    rac7af4a r359e537  
    44 * Copyright (c) 2002 by Cogent Computer Systems
    55 * Written by Mike Kelly <mike@cogcomp.com>
    6  *     
     6 *
    77 *  The license and distribution terms for this file may be
    88 *  found in the file LICENSE in this distribution or at
     
    6060 * PORT A
    6161 */
    62 #define GPIO_0          BIT0   
    63 #define GPIO_1          BIT1   
    64 #define GPIO_2          BIT2   
    65 #define GPIO_3          BIT3   
    66 #define GPIO_4          BIT4   
    67 #define GPIO_5          BIT5   
    68 #define GPIO_6          BIT6   
    69 #define GPIO_7          BIT7   
    70 #define GPIO_8          BIT8   
    71 #define GPIO_9          BIT9   
     62#define GPIO_0          BIT0
     63#define GPIO_1          BIT1
     64#define GPIO_2          BIT2
     65#define GPIO_3          BIT3
     66#define GPIO_4          BIT4
     67#define GPIO_5          BIT5
     68#define GPIO_6          BIT6
     69#define GPIO_7          BIT7
     70#define GPIO_8          BIT8
     71#define GPIO_9          BIT9
    7272#define GPIO_10         BIT10
    7373#define GPIO_11         BIT11
     
    9393#define GPIO_31         BIT31
    9494/* PORT B */
    95 #define GPIO_32         BIT0   
    96 #define GPIO_33         BIT1   
    97 #define GPIO_34         BIT2   
    98 #define GPIO_35         BIT3   
    99 #define GPIO_36         BIT4   
    100 #define GPIO_37         BIT5   
    101 #define GPIO_38         BIT6   
    102 #define GPIO_39         BIT7   
    103 #define GPIO_40         BIT8   
    104 #define GPIO_41         BIT9   
     95#define GPIO_32         BIT0
     96#define GPIO_33         BIT1
     97#define GPIO_34         BIT2
     98#define GPIO_35         BIT3
     99#define GPIO_36         BIT4
     100#define GPIO_37         BIT5
     101#define GPIO_38         BIT6
     102#define GPIO_39         BIT7
     103#define GPIO_40         BIT8
     104#define GPIO_41         BIT9
    105105#define GPIO_42         BIT10
    106106#define GPIO_43         BIT11
     
    126126#define GPIO_63         BIT31
    127127/* PORT C */
    128 #define GPIO_64         BIT0   
    129 #define GPIO_65         BIT1   
    130 #define GPIO_66         BIT2   
    131 #define GPIO_67         BIT3   
    132 #define GPIO_68         BIT4   
    133 #define GPIO_69         BIT5   
    134 #define GPIO_70         BIT6   
    135 #define GPIO_71         BIT7   
    136 #define GPIO_72         BIT8   
    137 #define GPIO_73         BIT9   
     128#define GPIO_64         BIT0
     129#define GPIO_65         BIT1
     130#define GPIO_66         BIT2
     131#define GPIO_67         BIT3
     132#define GPIO_68         BIT4
     133#define GPIO_69         BIT5
     134#define GPIO_70         BIT6
     135#define GPIO_71         BIT7
     136#define GPIO_72         BIT8
     137#define GPIO_73         BIT9
    138138#define GPIO_74         BIT10
    139139#define GPIO_75         BIT11
     
    159159#define GPIO_95         BIT31
    160160/* PORT D */
    161 #define GPIO_96         BIT0   
    162 #define GPIO_97         BIT1   
    163 #define GPIO_98         BIT2   
    164 #define GPIO_99         BIT3   
    165 #define GPIO_100        BIT4   
    166 #define GPIO_101        BIT5   
    167 #define GPIO_102        BIT6   
    168 #define GPIO_103        BIT7   
    169 #define GPIO_104        BIT8   
    170 #define GPIO_105        BIT9   
     161#define GPIO_96         BIT0
     162#define GPIO_97         BIT1
     163#define GPIO_98         BIT2
     164#define GPIO_99         BIT3
     165#define GPIO_100        BIT4
     166#define GPIO_101        BIT5
     167#define GPIO_102        BIT6
     168#define GPIO_103        BIT7
     169#define GPIO_104        BIT8
     170#define GPIO_105        BIT9
    171171#define GPIO_106        BIT10
    172172#define GPIO_107        BIT11
     
    377377#define PIOD_ASR_RTS3   BIT24   /* USART 3 RTS */
    378378#define PIOD_ASR_DTR1   BIT25   /* USART 1 DTR */
    379                    
     379
    380380/* Port D, Alternate Function B */
    381                
     381
    382382#define PIOC_ASR_TSYNC  BIT7    /* ETM Sync      */
    383383#define PIOC_ASR_TCLK   BIT8    /* ETM Clock */
  • c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_mem.h

    rac7af4a r359e537  
    44 * Copyright (c) 2002 by Cogent Computer Systems
    55 * Written by Mike Kelly <mike@cogcomp.com>
    6  *     
     6 *
    77 *  The license and distribution terms for this file may be
    88 *  found in the file LICENSE in this distribution or at
  • c/src/lib/libcpu/arm/at91rm9200/include/at91rm9200_pmc.h

    rac7af4a r359e537  
    44 * Copyright (c) 2002 by Cogent Computer Systems
    55 * Written by Mike Kelly <mike@cogcomp.com>
    6  *     
     6 *
    77 *  The license and distribution terms for this file may be
    88 *  found in the file LICENSE in this distribution or at
  • c/src/lib/libcpu/arm/at91rm9200/include/bits.h

    rac7af4a r359e537  
    44 * Copyright (c) 2002 by Cogent Computer Systems
    55 * Written by Mike Kelly <mike@cogcomp.com>
    6  *     
     6 *
    77 *  The license and distribution terms for this file may be
    88 *  found in the file LICENSE in this distribution or at
  • c/src/lib/libcpu/arm/at91rm9200/irq/bsp_irq_asm.S

    rac7af4a r359e537  
    33 *
    44 * Copyright (c) 2004 by Jay Monkman <jtm@lopgindog.com>
    5  *     
     5 *
    66 *  The license and distribution terms for this file may be
    77 *  found in the file LICENSE in this distribution or at
     
    1313 */
    1414#define __asm__
    15        
     15
    1616        .globl bsp_interrupt_dispatch
    1717bsp_interrupt_dispatch :
     
    2222 */
    2323        ldr     r0, =0xFFFFF100   /* AIC_CTL_BASE + AIC_IVR */
    24         ldr     r1, [r0]               
     24        ldr     r1, [r0]
    2525        str     r1, [r0]          /* write back in case we are using protect */
    2626
     
    3636        ldr   r2, =0xFFFFF130     /* AIC_CTL_BASE + AIC_EIOCR */
    3737        str   r1, [r2]
    38        
     38
    3939        ldmia sp!,{lr}
    4040
  • c/src/lib/libcpu/arm/at91rm9200/irq/bsp_irq_init.c

    rac7af4a r359e537  
    33 *
    44 * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
    5  *     
     5 *
    66 *  The license and distribution terms for this file may be
    77 *  found in the file LICENSE in this distribution or at
     
    1818extern void default_int_handler(void);
    1919
    20 /* 
    21  * Interrupt system initialization. Disable interrupts, clear 
     20/*
     21 * Interrupt system initialization. Disable interrupts, clear
    2222 * any that are pending.
    2323 */
  • c/src/lib/libcpu/arm/at91rm9200/irq/irq.c

    rac7af4a r359e537  
    33 *
    44 * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
    5  *     
     5 *
    66 *  The license and distribution terms for this file may be
    77 *  found in the file LICENSE in this distribution or at
     
    3535{
    3636    rtems_interrupt_level level;
    37    
     37
    3838    if (!isValidInterrupt(irq->name)) {
    3939        return 0;
    4040    }
    41    
     41
    4242    /*
    43      * Check if default handler is actually connected. If not, issue 
    44      * an error. Note: irq->name is a number corresponding to the 
    45      * sources PID (see the at91rm9200_pid for this mapping).  We 
    46      * convert it to a long word offset to get source's vector register 
     43     * Check if default handler is actually connected. If not, issue
     44     * an error. Note: irq->name is a number corresponding to the
     45     * sources PID (see the at91rm9200_pid for this mapping).  We
     46     * convert it to a long word offset to get source's vector register
    4747     */
    4848    if (AIC_SVR_REG(irq->name * 4) != (uint32_t) default_int_handler) {
    4949        return 0;
    5050    }
    51    
     51
    5252    rtems_interrupt_disable(level);
    53    
     53
    5454    /*
    5555     * store the new handler
    5656     */
    5757    AIC_SVR_REG(irq->name * 4) = (uint32_t) irq->hdl;
    58    
     58
    5959    /*
    6060     * unmask interrupt
    6161     */
    6262    AIC_CTL_REG(AIC_IECR) = 1 << irq->name;
    63    
     63
    6464    /*
    6565     * Enable interrupt on device
     
    6868        irq->on(irq);
    6969    }
    70    
     70
    7171    rtems_interrupt_enable(level);
    72    
     72
    7373    return 1;
    7474}
    7575
    76 /* 
     76/*
    7777 * Remove and interrupt handler
    7878 */
     
    8080{
    8181    rtems_interrupt_level level;
    82  
     82
    8383    if (!isValidInterrupt(irq->name)) {
    8484        return 0;
     
    9797     */
    9898    AIC_CTL_REG(AIC_IDCR) = 1 << irq->name;
    99    
     99
    100100    /*
    101101     * Disable interrupt on device
     
    109109     */
    110110    AIC_SVR_REG(irq->name * 4) = (uint32_t) default_int_handler;
    111    
     111
    112112    rtems_interrupt_enable(level);
    113113
  • c/src/lib/libcpu/arm/at91rm9200/irq/irq.h

    rac7af4a r359e537  
    33 *
    44 * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
    5  *     
     5 *
    66 *  The license and distribution terms for this file may be
    77 *  found in the file LICENSE in this distribution or at
     
    2525 * Include some preprocessor value also used by assember code
    2626 */
    27  
     27
    2828#include <rtems.h>
    2929#include <at91rm9200.h>
     
    3636#define AT91RM9200_INT_FIQ        0
    3737#define AT91RM9200_INT_SYSIRQ     1
    38 #define AT91RM9200_INT_PIOA       2 
     38#define AT91RM9200_INT_PIOA       2
    3939#define AT91RM9200_INT_PIOB       3
    4040#define AT91RM9200_INT_PIOC       4
     
    7272/* a vector table */
    7373#define VECTOR_TABLE AIC_SVR_BASE
    74                                                                                            
     74
    7575typedef unsigned char  rtems_irq_level;
    7676typedef unsigned char  rtems_irq_trigger;
     
    118118
    119119/*
    120  * function to get the current RTEMS irq handler for ptr->name. 
     120 * function to get the current RTEMS irq handler for ptr->name.
    121121 */
    122122int BSP_get_current_rtems_irq_handler   (rtems_irq_connect_data* ptr);
  • c/src/lib/libcpu/arm/at91rm9200/pmc/pmc.c

    rac7af4a r359e537  
    33 *
    44 * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
    5  *     
     5 *
    66 *  The license and distribution terms for this file may be
    77 *  found in the file LICENSE in this distribution or at
  • c/src/lib/libcpu/arm/at91rm9200/timer/timer.c

    rac7af4a r359e537  
    55 *
    66 * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
    7  *     
     7 *
    88 *  The license and distribution terms for this file may be
    99 *  found in the file LICENSE in this distribution or at
     
    1717 *  the number of microseconds since benchmark_timer_initialize() exitted.
    1818 *
    19  *  It is important that the timer start/stop overhead be determined 
     19 *  It is important that the timer start/stop overhead be determined
    2020 *  when porting or modifying this code.
    2121 *
     
    3232uint32_t tick_time;
    3333/*
    34  * Set up TC0 - 
     34 * Set up TC0 -
    3535 *   timer_clock2 (MCK/8)
    3636 *   capture mode - this shouldn't matter
  • c/src/lib/libcpu/arm/at91rm9200/usart/usart.c

    rac7af4a r359e537  
    22 *  Driver for AT91RM9200 USART ports
    33 *
    4  * COPYRIGHT (c) 2006-2009. 
     4 * COPYRIGHT (c) 2006-2009.
    55 * NCB - Sistemas Embarcados Ltda. (Brazil)
    66 * Fernando Nicodemos <fgnicodemos@terra.com.br>
    7  * 
     7 *
    88 * and
    99 *
     
    6161  if (console_entry == NULL)
    6262    return 0;
    63  
     63
    6464  port = (at91rm9200_usart_regs_t *) console_entry->ulCtrlPort1;
    6565  //printk( "minor=%d entry=%p port=%p\n", minor, console_entry, port );
     
    242242
    243243  baud_requested = t->c_cflag & CBAUD;
    244  
     244
    245245  /* If not, set the dbgu console baud as USART baud default */
    246246  if (!baud_requested)
    247     baud_requested = BSP_get_baud(); 
    248  
     247    baud_requested = BSP_get_baud();
     248
    249249  baud = rtems_termios_baud_to_number(baud_requested);
    250250
  • c/src/lib/libcpu/arm/lpc22xx/clock/clockdrv.c

    rac7af4a r359e537  
    3636                                         0 };   /* unused for ARM cpus */
    3737
    38 /* If you follow the code, this is never used, so any value 
     38/* If you follow the code, this is never used, so any value
    3939 * should work
    4040 */
     
    7373 *   - clear any pending interrupts
    7474 *
    75  * Since you may want the clock always running, you can 
     75 * Since you may want the clock always running, you can
    7676 * enable interrupts here. If you do so, the clock_isr_on(),
    77  * clock_isr_off(), and clock_isr_is_on() functions can be 
     77 * clock_isr_off(), and clock_isr_is_on() functions can be
    7878 * NOPs.
    7979 */
    80  
     80
    8181  /* set timer to generate interrupt every rtems_configuration_get_microseconds_per_tick()
    8282   * MR0/(LPC22xx_Fpclk/(PR0+1)) = 10/1000 = 0.01s
    83    */                   
    84        
     83   */
     84
    8585#define Clock_driver_support_initialize_hardware() \
    8686  do { \
     
    9696
    9797/**
    98  * Do whatever you need to shut the clock down and remove the 
     98 * Do whatever you need to shut the clock down and remove the
    9999 * interrupt handler. Since this normally only gets called on
    100100 * RTEMS shutdown, you may not need to do anything other than
     
    111111{
    112112        uint32_t clicks;
    113        
     113
    114114        clicks = T0TC;  /*T0TC is the 32bit time counter 0*/
    115        
     115
    116116        return (uint32_t) (rtems_configuration_get_microseconds_per_tick() - clicks) * 1000;
    117117}
    118        
     118
    119119#define Clock_driver_nanoseconds_since_last_tick bsp_clock_nanoseconds_since_last_tick
    120120
  • c/src/lib/libcpu/arm/lpc22xx/include/lpc22xx.h

    rac7af4a r359e537  
    33 *
    44 * Copyright (c) 2006 by Ray <rayx.cn@gmail.com>
    5  *     
     5 *
    66 *  The license and distribution terms for this file may be
    77 *  found in the file LICENSE in this distribution or at
     
    319319#define CAN5TDB3        (*((volatile unsigned long *) 0xE005405C))      /* lpc2119\lpc2129\lpc2292\lpc2294 only */
    320320
    321 #ifdef CONFIG_ARCH_LPC22xx 
     321#ifdef CONFIG_ARCH_LPC22xx
    322322#define CAN6MOD         (*((volatile unsigned long *) 0xE0058000))      /* lpc2292\lpc2294 only */
    323323#define CAN6CMR         (*((volatile unsigned long *) 0xE0058004))      /* lpc2292\lpc2294 only */
     
    456456/*
    457457        Register define for constant
    458 */     
     458*/
    459459#define REG_U0RBR                               0xE000C000
    460460#define REG_U1RBR                               0xE0010000
  • c/src/lib/libcpu/arm/lpc22xx/irq/bsp_irq_asm.S

    rac7af4a r359e537  
    1313 */
    1414#define __asm__
    15        
    16 /* 
     15
     16/*
    1717 * BSP specific interrupt handler for INT or FIQ. In here
    1818 * you do determine which interrupt happened and call its
     
    3131 * and load handler address into r0.
    3232 */
    33  
     33
    3434  ldr   r0, =0xFFFFF030  /* Read the vector number */
    3535    ldr r0, [r0]
  • c/src/lib/libcpu/arm/lpc22xx/irq/bsp_irq_init.c

    rac7af4a r359e537  
    11/*
    22 *  NXP/Philips LPC22XX/LPC21xx Interrupt handler
    3  *  Ray 2007 <rayx.cn@gmail.com> to support LPC ARM     
     3 *  Ray 2007 <rayx.cn@gmail.com> to support LPC ARM
    44 *  The license and distribution terms for this file may be
    55 *  found in the file LICENSE in this distribution or at
     
    1717extern void default_int_handler(void);
    1818
    19 /* 
    20  * Interrupt system initialization. Disable interrupts, clear 
     19/*
     20 * Interrupt system initialization. Disable interrupts, clear
    2121 * any that are pending.
    2222 */
     
    3434      *(vectorTable + i) = (long)(default_int_handler);
    3535  }
    36    
     36
    3737  /*
    3838   * Set IRQHandler
     
    5757   * enable the next lines and set a breakpoint
    5858   * in ABORTHandler.
    59    */ 
     59   */
    6060#if 1
    6161  DATA_ABORT_VECTOR_ADDR = 0xE59FF018;
    62 #endif 
     62#endif
    6363
    6464  /*
  • c/src/lib/libcpu/arm/lpc22xx/irq/irq.c

    rac7af4a r359e537  
    11/*
    22 * Philps LPC22XX Interrupt handler
    3  * 
    4  * Copyright (c)  2006 by Ray<rayx.cn@gmail.com>  to support LPC ARM     
     3 *
     4 * Copyright (c)  2006 by Ray<rayx.cn@gmail.com>  to support LPC ARM
    55 *  The license and distribution terms for this file may be
    66 *  found in the file LICENSE in this distribution or at
     
    3838    rtems_irq_hdl        *bsp_tbl;
    3939    int                  *vic_cntl;
    40    
     40
    4141    bsp_tbl = (rtems_irq_hdl *)VICVectAddrBase;
    4242
    4343    vic_cntl=(int *)VICVectCntlBase;
    44    
     44
    4545    if (!isValidInterrupt(irq->name)) {
    4646      return 0;
     
    6767    vic_cntl[irq->name] = 0x20 | irq->name;
    6868
    69     VICIntEnable |= 1 << irq->name; 
    70    
     69    VICIntEnable |= 1 << irq->name;
     70
    7171    if(irq->on)
    7272    {
     
    7676
    7777    rtems_interrupt_enable(level);
    78    
     78
    7979    return 1;
    8080}
    8181
    82 /* 
     82/*
    8383 * Remove and interrupt handler
    8484 *
     
    9292
    9393    bsp_tbl = (rtems_irq_hdl *)&VICVectAddr0;
    94  
     94
    9595    if (!isValidInterrupt(irq->name)) {
    9696      return 0;
     
    117117     */
    118118    bsp_tbl[irq->name] = default_int_handler;
    119    
     119
    120120    rtems_interrupt_enable(level);
    121121
  • c/src/lib/libcpu/arm/lpc22xx/irq/irq.h

    rac7af4a r359e537  
    22 * Interrupt handler Header file
    33 *
    4  * Copyright (c) 2006 by Ray <rayx.cn@gmail.com> to support LPC ARM 
    5  *     
     4 * Copyright (c) 2006 by Ray <rayx.cn@gmail.com> to support LPC ARM
     5 *
    66 *  The license and distribution terms for this file may be
    77 *  found in the file LICENSE in this distribution or at
     
    2626 * Include some preprocessor value also used by assember code
    2727 */
    28  
     28
    2929#include <rtems.h>
    3030#include <lpc22xx.h>
     
    6767#define BSP_MAX_INT              28
    6868
    69 #define UNDEFINED_INSTRUCTION_VECTOR_ADDR   (*(u_long *)0x00000004L)   
     69#define UNDEFINED_INSTRUCTION_VECTOR_ADDR   (*(u_long *)0x00000004L)
    7070#define SOFTWARE_INTERRUPT_VECTOR_ADDR      (*(u_long *)0x00000008L)
    7171#define PREFETCH_ABORT_VECTOR_ADDR          (*(u_long *)0x0000000CL)
     
    7878#define FIQ_ISR_ADDR                        (*(u_long *)0x0000003CL)
    7979
    80              
     80
    8181typedef unsigned char  rtems_irq_level;
    8282typedef unsigned char  rtems_irq_trigger;
     
    9292//extern rtems_irq_hdl bsp_vector_table[BSP_MAX_INT];
    9393#define VECTOR_TABLE VICVectAddrBase
    94                                                                                            
     94
    9595typedef struct __rtems_irq_connect_data__ {
    9696    /* IRQ line */
     
    128128
    129129/*
    130  * function to get the current RTEMS irq handler for ptr->name. 
     130 * function to get the current RTEMS irq handler for ptr->name.
    131131 */
    132132int BSP_get_current_rtems_irq_handler   (rtems_irq_connect_data* ptr);
  • c/src/lib/libcpu/arm/lpc22xx/timer/lpc_timer.h

    rac7af4a r359e537  
    1212#define TCR_RESET_BIT   1
    1313
    14 // The channel name which is used in matching, in fact they represent 
    15 // corresponding Match Register 
     14// The channel name which is used in matching, in fact they represent
     15// corresponding Match Register
    1616#define CH_MAXNUM       4
    1717#define CH0             0
     
    2020#define CH3             3
    2121
    22 // The channel name which is used in capturing, in fact they represent 
    23 // corresponding Capture Register 
     22// The channel name which is used in capturing, in fact they represent
     23// corresponding Capture Register
    2424#define CPCH_MAXNUM     4
    2525#define CPCH0           0
  • c/src/lib/libcpu/arm/lpc22xx/timer/timer.c

    rac7af4a r359e537  
    33 *
    44 * This uses Timer1 for timing measurments.
    5  * 
     5 *
    66 *  By Ray xu<rayx.cn@gmail.com>, modify form Mc9328mxl RTEMS DSP
    77 *
     
    1717 *  the number of microseconds since benchmark_timer_initialize() exitted.
    1818 *
    19  *  It is important that the timer start/stop overhead be determined 
     19 *  It is important that the timer start/stop overhead be determined
    2020 *  when porting or modifying this code.
    2121 *
     
    3232bool benchmark_timer_find_average_overhead;
    3333
    34    
     34
    3535/*
    3636 * Set up Timer 1
  • c/src/lib/libcpu/arm/mc9328mxl/clock/clockdrv.c

    rac7af4a r359e537  
    3838};
    3939
    40 /* If you follow the code, this is never used, so any value 
     40/* If you follow the code, this is never used, so any value
    4141 * should work
    4242 */
    4343#define CLOCK_VECTOR 0
    4444
    45    
     45
    4646/**
    4747 * When we get the clock interrupt
     
    7373 *   - clear any pending interrupts
    7474 *
    75  * Since you may want the clock always running, you can 
     75 * Since you may want the clock always running, you can
    7676 * enable interrupts here. If you do so, the clock_isr_on(),
    77  * clock_isr_off(), and clock_isr_is_on() functions can be 
     77 * clock_isr_off(), and clock_isr_is_on() functions can be
    7878 * NOPs.
    7979 */
     
    9696
    9797/**
    98  * Do whatever you need to shut the clock down and remove the 
     98 * Do whatever you need to shut the clock down and remove the
    9999 * interrupt handler. Since this normally only gets called on
    100100 * RTEMS shutdown, you may not need to do anything other than
  • c/src/lib/libcpu/arm/mc9328mxl/include/mc9328mxl.h

    rac7af4a r359e537  
    44 * Copyright (c) 2003 by Cogent Computer Systems
    55 * Written by Jay Monkman <jtm@lopingdog.com>
    6  *     
     6 *
    77 *  The license and distribution terms for this file may be
    88 *  found in the file LICENSE in this distribution or at
     
    7676#define MC9328MXL_TMR_TCTL_CAP_ANY            (3 << 6)
    7777#define MC9328MXL_TMR_TCTL_OM                 (bit(5))
    78 #define MC9328MXL_TMR_TCTL_IRQEN              (bit(4))               
     78#define MC9328MXL_TMR_TCTL_IRQEN              (bit(4))
    7979#define MC9328MXL_TMR_TCTL_CLKSRC_STOP        (0 << 1)
    8080#define MC9328MXL_TMR_TCTL_CLKSRC_PCLK1       (1 << 1)
    8181#define MC9328MXL_TMR_TCTL_CLKSRC_PCLK_DIV16  (2 << 1)
    8282#define MC9328MXL_TMR_TCTL_CLKSRC_TIN         (3 << 1)
    83 #define MC9328MXL_TMR_TCTL_CLKSRC_32KHX       (4 << 1) 
     83#define MC9328MXL_TMR_TCTL_CLKSRC_32KHX       (4 << 1)
    8484#define MC9328MXL_TMR_TCTL_TEN                (bit(0))
    8585
     
    222222#define MC9328MXL_UART_CR3_BPEN       (bit(0))
    223223
    224 #define MC9328MXL_UART_CR4_CTSTL(_x_) (((_x_) & 0x3f) << 10)     
     224#define MC9328MXL_UART_CR4_CTSTL(_x_) (((_x_) & 0x3f) << 10)
    225225#define MC9328MXL_UART_CR4_INVR       (bit(9))
    226226#define MC9328MXL_UART_CR4_ENIRI      (bit(8))
     
    314314#define MC9328MXL_PLL_SPCTL_MFN_MASK       (0x000003ff)
    315315#define MC9328MXL_PLL_SPCTL_MFN_SHIFT      (0)
    316    
     316
    317317
    318318#define MC9328MXL_GPIOA_DDIR    (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x00)))
  • c/src/lib/libcpu/arm/mc9328mxl/irq/bsp_irq_asm.S

    rac7af4a r359e537  
    1313 */
    1414#define __asm__
    15        
    16 /* 
     15
     16/*
    1717 * BSP specific interrupt handler for INT or FIQ. In here
    1818 * you do determine which interrupt happened and call its
     
    3030  mov   r1, r1, LSR #16         /* get the NIVECTOR into 16 LSbits */
    3131
    32   /* find the ISR's address based on the vector */     
     32  /* find the ISR's address based on the vector */
    3333  ldr   r0, =bsp_vector_table
    3434  mov   r1, r1, LSL #3          /* Shift vector to get offset into table */
  • c/src/lib/libcpu/arm/mc9328mxl/irq/bsp_irq_init.c

    rac7af4a r359e537  
    33 *
    44 * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
    5  *     
     5 *
    66 *  The license and distribution terms for this file may be
    77 *  found in the file LICENSE in this distribution or at
     
    1818extern void default_int_handler(void);
    1919
    20 /* 
    21  * Interrupt system initialization. Disable interrupts, clear 
     20/*
     21 * Interrupt system initialization. Disable interrupts, clear
    2222 * any that are pending.
    2323 */
  • c/src/lib/libcpu/arm/mc9328mxl/irq/irq.c

    rac7af4a r359e537  
    33 *
    44 * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
    5  *     
     5 *
    66 *  The license and distribution terms for this file may be
    77 *  found in the file LICENSE in this distribution or at
     
    3939{
    4040    rtems_interrupt_level level;
    41    
     41
    4242    if (!isValidInterrupt(irq->name)) {
    4343      return 0;
     
    6666        irq->on(irq);
    6767    }
    68    
     68
    6969    rtems_interrupt_enable(level);
    70    
     70
    7171    return 1;
    7272}
    7373
    74 /* 
     74/*
    7575 * Remove and interrupt handler
    7676 *
  • c/src/lib/libcpu/arm/mc9328mxl/irq/irq.h

    rac7af4a r359e537  
    33 *
    44 * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
    5  *     
     5 *
    66 *  The license and distribution terms for this file may be
    77 *  found in the file LICENSE in this distribution or at
     
    2828 * Include some preprocessor value also used by assember code
    2929 */
    30  
     30
    3131#include <rtems.h>
    3232#include <mc9328mxl.h>
     
    3838
    3939/* possible interrupt sources on the MC9328MXL */
    40 #define BSP_INT_UART3_PFERR       0 
    41 #define BSP_INT_UART3_RTS         1     
    42 #define BSP_INT_UART3_DTR         2     
    43 #define BSP_INT_UART3_UARTC       3       
    44 #define BSP_INT_UART3_TX          4   
    45 #define BSP_INT_PEN_UP            5 
     40#define BSP_INT_UART3_PFERR       0
     41#define BSP_INT_UART3_RTS         1
     42#define BSP_INT_UART3_DTR         2
     43#define BSP_INT_UART3_UARTC       3
     44#define BSP_INT_UART3_TX          4
     45#define BSP_INT_PEN_UP            5
    4646#define BSP_INT_CSI               6
    47 #define BSP_INT_MMA_MAC           7   
     47#define BSP_INT_MMA_MAC           7
    4848#define BSP_INT_MMA               8
    4949#define BSP_INT_COMP              9
    50 #define BSP_INT_MSIRQ            10 
    51 #define BSP_INT_GPIO_PORTA       11       
    52 #define BSP_INT_GPIO_PORTB       12       
    53 #define BSP_INT_GPIO_PORTC       13       
    54 #define BSP_INT_LCDC             14 
    55 #define BSP_INT_SIM_IRQ          15   
    56 #define BSP_INT_SIM_DATA         16     
     50#define BSP_INT_MSIRQ            10
     51#define BSP_INT_GPIO_PORTA       11
     52#define BSP_INT_GPIO_PORTB       12
     53#define BSP_INT_GPIO_PORTC       13
     54#define BSP_INT_LCDC             14
     55#define BSP_INT_SIM_IRQ          15
     56#define BSP_INT_SIM_DATA         16
    5757#define BSP_INT_RTC              17
    58 #define BSP_INT_RTC_SAM          18   
    59 #define BSP_INT_UART2_PFERR      19       
    60 #define BSP_INT_UART2_RTS        20     
    61 #define BSP_INT_UART2_DTR        21     
    62 #define BSP_INT_UART2_UARTC      22       
    63 #define BSP_INT_UART2_TX         23     
    64 #define BSP_INT_UART2_RX         24     
    65 #define BSP_INT_UART1_PFERR      25       
    66 #define BSP_INT_UART1_RTS        26     
    67 #define BSP_INT_UART1_DTR        27     
    68 #define BSP_INT_UART1_UARTC      28       
    69 #define BSP_INT_UART1_TX         29     
    70 #define BSP_INT_UART1_RX         30     
    71 #define BSP_INT_RES31            31 
    72 #define BSP_INT_RES32            32 
    73 #define BSP_INT_PEN_DATA         33   
     58#define BSP_INT_RTC_SAM          18
     59#define BSP_INT_UART2_PFERR      19
     60#define BSP_INT_UART2_RTS        20
     61#define BSP_INT_UART2_DTR        21
     62#define BSP_INT_UART2_UARTC      22
     63#define BSP_INT_UART2_TX         23
     64#define BSP_INT_UART2_RX         24
     65#define BSP_INT_UART1_PFERR      25
     66#define BSP_INT_UART1_RTS        26
     67#define BSP_INT_UART1_DTR        27
     68#define BSP_INT_UART1_UARTC      28
     69#define BSP_INT_UART1_TX         29
     70#define BSP_INT_UART1_RX         30
     71#define BSP_INT_RES31            31
     72#define BSP_INT_RES32            32
     73#define BSP_INT_PEN_DATA         33
    7474#define BSP_INT_PWM              34
    75 #define BSP_INT_MMC_IRQ          35   
    76 #define BSP_INT_SSI2_TX          36   
    77 #define BSP_INT_SSI2_RX          37   
    78 #define BSP_INT_SSI2_ERR         38   
     75#define BSP_INT_MMC_IRQ          35
     76#define BSP_INT_SSI2_TX          36
     77#define BSP_INT_SSI2_RX          37
     78#define BSP_INT_SSI2_ERR         38
    7979#define BSP_INT_I2C              39
    8080#define BSP_INT_SPI2             40
    8181#define BSP_INT_SPI1             41
    82 #define BSP_INT_SSI_TX           42 
    83 #define BSP_INT_SSI_TX_ERR       43     
    84 #define BSP_INT_SSI_RX           44   
    85 #define BSP_INT_SSI_RX_ERR       45     
    86 #define BSP_INT_TOUCH            46 
    87 #define BSP_INT_USBD0            47 
    88 #define BSP_INT_USBD1            48 
    89 #define BSP_INT_USBD2            49 
    90 #define BSP_INT_USBD3            50 
    91 #define BSP_INT_USBD4            51 
    92 #define BSP_INT_USBD5            52 
    93 #define BSP_INT_USBD6            53 
    94 #define BSP_INT_UART3_RX         54   
    95 #define BSP_INT_BTSYS            55 
    96 #define BSP_INT_BTTIM            56 
    97 #define BSP_INT_BTWUI            57 
    98 #define BSP_INT_TIMER2           58 
    99 #define BSP_INT_TIMER1           59   
    100 #define BSP_INT_DMA_ERR          60   
     82#define BSP_INT_SSI_TX           42
     83#define BSP_INT_SSI_TX_ERR       43
     84#define BSP_INT_SSI_RX           44
     85#define BSP_INT_SSI_RX_ERR       45
     86#define BSP_INT_TOUCH            46
     87#define BSP_INT_USBD0            47
     88#define BSP_INT_USBD1            48
     89#define BSP_INT_USBD2            49
     90#define BSP_INT_USBD3            50
     91#define BSP_INT_USBD4            51
     92#define BSP_INT_USBD5            52
     93#define BSP_INT_USBD6            53
     94#define BSP_INT_UART3_RX         54
     95#define BSP_INT_BTSYS            55
     96#define BSP_INT_BTTIM            56
     97#define BSP_INT_BTWUI            57
     98#define BSP_INT_TIMER2           58
     99#define BSP_INT_TIMER1           59
     100#define BSP_INT_DMA_ERR          60
    101101#define BSP_INT_DMA              61
    102 #define BSP_INT_GPIO_PORTD       62     
     102#define BSP_INT_GPIO_PORTD       62
    103103#define BSP_INT_WDT              63
    104104#define BSP_MAX_INT              64
    105              
     105
    106106typedef struct {
    107107    rtems_irq_hdl       vector;
  • c/src/lib/libcpu/arm/mc9328mxl/timer/timer.c

    rac7af4a r359e537  
    66 * Copyright (c) 2004 Cogent Computer Systems
    77 *        Written by Jay Monkman <jtm@lopingdog.com>
    8  *     
     8 *
    99 *  The license and distribution terms for this file may be
    1010 *  found in the file LICENSE in this distribution or at
     
    1818 *  the number of microseconds since benchmark_timer_initialize() exitted.
    1919 *
    20  *  It is important that the timer start/stop overhead be determined 
     20 *  It is important that the timer start/stop overhead be determined
    2121 *  when porting or modifying this code.
    2222 *
     
    3333bool benchmark_timer_find_average_overhead;
    3434
    35    
     35
    3636/*
    3737 * Set up Timer 1
     
    3939void benchmark_timer_initialize( void )
    4040{
    41     MC9328MXL_TMR2_TCTL = (MC9328MXL_TMR_TCTL_CLKSRC_PCLK1 | 
     41    MC9328MXL_TMR2_TCTL = (MC9328MXL_TMR_TCTL_CLKSRC_PCLK1 |
    4242                            MC9328MXL_TMR_TCTL_FRR |
    4343                            MC9328MXL_TMR_TCTL_TEN);
     
    8181
    8282  /* convert to nanoseconds */
    83   total = (total * 1000)/ g_freq; 
     83  total = (total * 1000)/ g_freq;
    8484
    8585  if ( benchmark_timer_find_average_overhead == 1 ) {
    86     return (int) total; 
     86    return (int) total;
    8787  } else if ( total < LEAST_VALID ) {
    88       return 0;       
     88      return 0;
    8989  }
    9090  /*
  • c/src/lib/libcpu/arm/pxa255/ffuart/ffuart.c

    rac7af4a r359e537  
    3232
    3333/* Pointers to functions for handling the UART. */
    34 console_fns ffuart_fns = 
    35 { 
     34console_fns ffuart_fns =
     35{
    3636    libchip_serial_default_probe,
    3737    ffuart_first_open,
     
    4646
    4747
    48 /* 
     48/*
    4949 * This is called the first time each device is opened. Since
    50  * the driver is polled, we don't have to do anything. If the driver 
    51  * were interrupt driven, we'd enable interrupts here. 
    52  */
    53 static int ffuart_first_open(int major, int minor, void *arg) 
     50 * the driver is polled, we don't have to do anything. If the driver
     51 * were interrupt driven, we'd enable interrupts here.
     52 */
     53static int ffuart_first_open(int major, int minor, void *arg)
    5454{
    5555    return 0;
     
    5757
    5858
    59 /* 
     59/*
    6060 * This is called the last time each device is closed.  Since
    61  * the driver is polled, we don't have to do anything. If the driver 
    62  * were interrupt driven, we'd disable interrupts here. 
    63  */
    64 static int ffuart_last_close(int major, int minor, void *arg) 
     61 * the driver is polled, we don't have to do anything. If the driver
     62 * were interrupt driven, we'd disable interrupts here.
     63 */
     64static int ffuart_last_close(int major, int minor, void *arg)
    6565{
    6666    return 0;
     
    7474 * the character in lowest 8 bits of returned int.
    7575 */
    76 static int ffuart_read(int minor) 
     76static int ffuart_read(int minor)
    7777{
    7878    char c;
     
    9191        return -1;
    9292    }
    93    
    94     c  = ffuart->rbr & 0xff; 
    95    
     93
     94    c  = ffuart->rbr & 0xff;
     95
    9696    return c;
    9797}
    9898
    9999
    100 /* 
    101  * Write buffer to UART 
     100/*
     101 * Write buffer to UART
    102102 *
    103103 * return 1 on success, -1 on error
     
    125125            }
    126126        }
    127        
     127
    128128        c = (char) buf[i];
    129129#if ON_SKYEYE != 1
     
    141141#endif
    142142        ffuart->rbr = c;
    143        
     143
    144144        /* the TXRDY flag does not seem to update right away (is this true?) */
    145145        /* so we wait a bit before continuing */
     
    148148        }
    149149    }
    150    
     150
    151151    return 1;
    152152}
     
    156156{
    157157
    158  
     158
    159159    console_tbl *console_entry;
    160160    ffuart_reg_t  *ffuart;
     
    164164
    165165
    166    
     166
    167167    if (console_entry == NULL) {
    168168        return;
    169169    }
    170    
     170
    171171    ffuart = (ffuart_reg_t *)console_entry->ulCtrlPort1;
    172172    ffuart->lcr |= DLAB;
     
    192192
    193193/* This is for setting baud rate, bits, etc. */
    194 static int ffuart_set_attributes(int minor, const struct termios *t) 
     194static int ffuart_set_attributes(int minor, const struct termios *t)
    195195{
    196196    return 0;
     
    203203 */
    204204/***********************************************************************/
    205 /* 
     205/*
    206206 * Read from UART. This is used in the exit code, and can't
    207207 * rely on interrupts.
     
    214214
    215215/*
    216  * Write a character to the console. This is used by printk() and 
     216 * Write a character to the console. This is used by printk() and
    217217 * maybe other low level functions. It should not use interrupts or any
    218218 * RTEMS system calls. It needs to be very simple
  • c/src/lib/libcpu/arm/pxa255/include/ffuart.h

    rac7af4a r359e537  
    4848
    4949#endif
    50  
     50
  • c/src/lib/libcpu/arm/pxa255/irq/bsp_irq_asm.S

    rac7af4a r359e537  
    22 * PXA255 Interrupt handler by Yang Xi <hiyangxi@gmail.com>
    33 * Copyright (c) 2004 by Jay Monkman <jtm@lopgindog.com>
    4  *     
     4 *
    55 *  The license and distribution terms for this file may be
    66 *  found in the file LICENSE in this distribution or at
     
    1111
    1212#define __asm__
    13        
     13
    1414        .globl bsp_interrupt_dispatch
    1515bsp_interrupt_dispatch :
  • c/src/lib/libcpu/arm/pxa255/irq/bsp_irq_init.c

    rac7af4a r359e537  
    22 * PXA255 interrupt controller by Yang Xi <hiyangxi@gmail.com>
    33 * Copyright (c) 2004 by Jay Monkman <jtm@lopgindog.com>
    4  * 
     4 *
    55 *  The license and distribution terms for this file may be
    66 *  found in the file LICENSE in this distribution or at
     
    2121void (*IRQ_table[PRIMARY_IRQS])(uint32_t vector);
    2222
    23 /* 
    24  * Interrupt system initialization. Disable interrupts, clear 
     23/*
     24 * Interrupt system initialization. Disable interrupts, clear
    2525 * any that are pending.
    2626 */
  • c/src/lib/libcpu/arm/pxa255/irq/irq.c

    rac7af4a r359e537  
    22 * PXA255 Interrupt handler by Yang Xi <hiyangxi@gmail.com>
    33 * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
    4  *     
     4 *
    55 *  The license and distribution terms for this file may be
    66 *  found in the file LICENSE in this distribution or at
     
    3333{
    3434    rtems_interrupt_level level;
    35    
     35
    3636    if (!isValidInterrupt(irq->name)) {
    3737        return 0;
    3838    }
    39    
     39
    4040    /*
    41      * Check if default handler is actually connected. If not, issue 
    42      * an error. Note: irq->name is a number corresponding to the 
    43      * interrupt number .  We 
    44      * convert it to a long word offset to get source's vector register 
     41     * Check if default handler is actually connected. If not, issue
     42     * an error. Note: irq->name is a number corresponding to the
     43     * interrupt number .  We
     44     * convert it to a long word offset to get source's vector register
    4545     */
    4646        if (IRQ_table[irq->name] != dummy_handler) {
    4747        return 0;
    4848        }
    49    
     49
    5050    _CPU_ISR_Disable(level);
    51    
     51
    5252    /*
    5353     * store the new handler
    5454     */
    5555    IRQ_table[irq->name] = irq->hdl;
    56    
     56
    5757    /*
    5858     * unmask interrupt
     
    6161
    6262
    63    
     63
    6464    /*
    6565     * Enable interrupt on device
     
    6868        irq->on(irq);
    6969    }
    70    
     70
    7171    _CPU_ISR_Enable(level);
    72    
     72
    7373    return 1;
    7474}
    7575
    76 /* 
     76/*
    7777 * Remove and interrupt handler
    7878 */
     
    8080{
    8181    rtems_interrupt_level level;
    82  
     82
    8383    if (!isValidInterrupt(irq->name)) {
    8484        return 0;
     
    9797     */
    9898    XSCALE_INT_ICMR  =  XSCALE_INT_ICMR  & (~(1 << irq->name));
    99    
     99
    100100    /*
    101101     * Disable interrupt on device
     
    109109     */
    110110    IRQ_table[irq->name] = dummy_handler;
    111    
     111
    112112    _CPU_ISR_Enable(level);
    113113
  • c/src/lib/libcpu/arm/pxa255/irq/irq.h

    rac7af4a r359e537  
    22 * Interrupt handler Header file for PXA By Yang Xi <hiyangxi@gmail.com>
    33 * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
    4  *     
     4 *
    55 *  The license and distribution terms for this file may be
    66 *  found in the file LICENSE in this distribution or at
     
    2222 * Include some preprocessor value also used by assember code
    2323 */
    24  
     24
    2525#include <rtems.h>
    2626#include <pxa255.h>
     
    7878
    7979/*
    80  * function to get the current RTEMS irq handler for ptr->name. 
     80 * function to get the current RTEMS irq handler for ptr->name.
    8181 */
    8282int BSP_get_current_rtems_irq_handler   (rtems_irq_connect_data* ptr);
  • c/src/lib/libcpu/arm/pxa255/timer/timer.c

    rac7af4a r359e537  
    99 *  the number of microseconds since Timer_initialize() exitted.
    1010 *
    11  *  It is important that the timer start/stop overhead be determined 
     11 *  It is important that the timer start/stop overhead be determined
    1212 *  when porting or modifying this code.
    1313 *
     
    3030
    3131/*
    32  * Use the timer count register to measure. 
     32 * Use the timer count register to measure.
    3333 * The frequency of it is 3.4864MHZ
    3434 * The longest period we are able to capture is 4G/3.4864MHZ
     
    6363  else
    6464    total += 0xffffffff - tick_time; /*Round up but not overflow*/
    65      
     65
    6666  if ( benchmark_timer_find_average_overhead == true )
    6767    return total;          /*Counter cycles*/
  • c/src/lib/libcpu/arm/s3c2400/clock/support.c

    rac7af4a r359e537  
    4242uint32_t get_HCLK(void)
    4343{
    44     if (rCLKDIVN & 0x2) 
     44    if (rCLKDIVN & 0x2)
    4545        return get_FCLK()/2;
    4646    else
    47         return get_FCLK();   
     47        return get_FCLK();
    4848}
    4949
  • c/src/lib/libcpu/arm/s3c2400/include/s3c2400.h

    rac7af4a r359e537  
    473473} LCDCON1;
    474474
    475 typedef union { 
     475typedef union {
    476476  struct {
    477477    unsigned VSPW:6;    /* TFT: Vertical sync pulse width determines the */
  • c/src/lib/libcpu/arm/s3c2400/irq/bsp_irq_asm.S

    rac7af4a r359e537  
    1515
    1616#define __asm__
    17                
    18 /* 
    19  * Function to obtain, execute an IT handler and acknowledge the IT 
     17
     18/*
     19 * Function to obtain, execute an IT handler and acknowledge the IT
    2020 */
    2121
    2222        .globl bsp_interrupt_dispatch
    23        
    24 bsp_interrupt_dispatch :     
     23
     24bsp_interrupt_dispatch :
    2525
    2626        ldr     r0, =0x14400014  /* Read rINTOFFSET */
     
    2929        ldr     r0, =bsp_vector_table
    3030        ldr     r0, [r0, r1, LSL #2]    /* Read the address */
    31        
     31
    3232        stmdb     sp!,{lr}
    3333        ldr     lr, =IRQ_return         /* prepare the return from handler  */
    34        
     34
    3535        mov pc, r0
    3636
  • c/src/lib/libcpu/arm/s3c2400/irq/bsp_irq_init.c

    rac7af4a r359e537  
    1919extern void default_int_handler();
    2020
    21 void BSP_rtems_irq_mngt_init() 
     21void BSP_rtems_irq_mngt_init()
    2222{
    2323    long *vectorTable;
  • c/src/lib/libcpu/arm/s3c2400/irq/irq.c

    rac7af4a r359e537  
    4242    rtems_irq_hdl         *HdlTable;
    4343    rtems_interrupt_level  level;
    44    
     44
    4545    if (!isValidInterrupt(irq->name)) {
    4646        return 0;
     
    5454        return 0;
    5555    }
    56    
     56
    5757    rtems_interrupt_disable(level);
    5858
     
    7979    rtems_irq_hdl         *HdlTable;
    8080    rtems_interrupt_level  level;
    81  
     81
    8282    if (!isValidInterrupt(irq->name)) {
    8383        return 0;
     
    104104     */
    105105    *(HdlTable + irq->name) = default_int_handler;
    106          
     106
    107107    rtems_interrupt_enable(level);
    108108
  • c/src/lib/libcpu/arm/s3c2400/irq/irq.h

    rac7af4a r359e537  
    2424 * Include some preprocessor value also used by assember code
    2525 */
    26  
     26
    2727#include <rtems.h>
    2828#include <s3c2400.h>
     
    4242#define BSP_EINT6             6
    4343#define BSP_EINT7             7
    44 #define BSP_INT_TICK          8 
    45 #define BSP_INT_WDT           9 
    46 #define BSP_INT_TIMER0       10   
    47 #define BSP_INT_TIMER1       11   
    48 #define BSP_INT_TIMER2       12   
    49 #define BSP_INT_TIMER3       13   
    50 #define BSP_INT_TIMER4       14   
    51 #define BSP_INT_UERR01       15   
    52 #define _res0                16       
    53 #define BSP_INT_DMA0         17 
    54 #define BSP_INT_DMA1         18 
    55 #define BSP_INT_DMA2         19 
    56 #define BSP_INT_DMA3         20 
    57 #define BSP_INT_MMC          21 
    58 #define BSP_INT_SPI          22 
    59 #define BSP_INT_URXD0        23   
    60 #define BSP_INT_URXD1        24   
    61 #define BSP_INT_USBD         25 
    62 #define BSP_INT_USBH         26 
    63 #define BSP_INT_IIC          27 
    64 #define BSP_INT_UTXD0        28   
    65 #define BSP_INT_UTXD1        29   
    66 #define BSP_INT_RTC          30 
    67 #define BSP_INT_ADC          31 
    68 #define BSP_MAX_INT          32 
     44#define BSP_INT_TICK          8
     45#define BSP_INT_WDT           9
     46#define BSP_INT_TIMER0       10
     47#define BSP_INT_TIMER1       11
     48#define BSP_INT_TIMER2       12
     49#define BSP_INT_TIMER3       13
     50#define BSP_INT_TIMER4       14
     51#define BSP_INT_UERR01       15
     52#define _res0                16
     53#define BSP_INT_DMA0         17
     54#define BSP_INT_DMA1         18
     55#define BSP_INT_DMA2         19
     56#define BSP_INT_DMA3         20
     57#define BSP_INT_MMC          21
     58#define BSP_INT_SPI          22
     59#define BSP_INT_URXD0        23
     60#define BSP_INT_URXD1        24
     61#define BSP_INT_USBD         25
     62#define BSP_INT_USBH         26
     63#define BSP_INT_IIC          27
     64#define BSP_INT_UTXD0        28
     65#define BSP_INT_UTXD1        29
     66#define BSP_INT_RTC          30
     67#define BSP_INT_ADC          31
     68#define BSP_MAX_INT          32
    6969
    7070extern void *bsp_vector_table;
    7171#define VECTOR_TABLE &bsp_vector_table
    72  
     72
    7373/*
    7474 * Type definition for RTEMS managed interrupts
     
    102102     * RTEMS may well need such a function when restoring normal interrupt
    103103     * processing after a debug session.
    104      * 
    105      */
    106     rtems_irq_enable            on;     
     104     *
     105     */
     106    rtems_irq_enable            on;
    107107
    108108    /*
     
    179179 *      5) restore the C scratch registers...
    180180 *      6) restore initial execution flow
    181  * 
     181 *
    182182 */
    183183int BSP_install_rtems_irq_handler       (const rtems_irq_connect_data*);
  • c/src/lib/libcpu/arm/s3c2400/timer/timer.c

    rac7af4a r359e537  
    1515 *  the number of microseconds since benchmark_timer_initialize() exitted.
    1616 *
    17  *  It is important that the timer start/stop overhead be determined 
     17 *  It is important that the timer start/stop overhead be determined
    1818 *  when porting or modifying this code.
    1919 *
     
    3030bool benchmark_timer_find_average_overhead;
    3131
    32    
     32
    3333/*
    3434 * Set up Timer 1
     
    3838    uint32_t cr;
    3939
    40     /* stop TIMER1*/ 
     40    /* stop TIMER1*/
    4141    cr=rTCON & 0xFFFFF0FF;
    4242    rTCON=(cr | (0x0 << 8));
     
    4646    rTCFG1=(cr | (0<<4));
    4747
    48     /* input freq=PLCK/2 Mhz*/ 
    49     g_freq = get_PCLK() / 2000; 
     48    /* input freq=PLCK/2 Mhz*/
     49    g_freq = get_PCLK() / 2000;
    5050    rTCNTB1 = 0xFFFF;
    5151
    52     /* start TIMER1 with manual reload */ 
     52    /* start TIMER1 with manual reload */
    5353    cr=rTCON & 0xFFFFF0FF;
    5454    rTCON=(cr | (0x1 << 9));
    5555    rTCON=(cr | (0x1 << 8));
    56  
     56
    5757    g_start =  rTCNTO1;
    5858}
     
    8484     *  interrupts.
    8585     */
    86    
     86
    8787    total = (g_start - t);
    8888
    8989    /* convert to microseconds */
    90     total = (total*1000) / g_freq; 
     90    total = (total*1000) / g_freq;
    9191
    9292    if ( benchmark_timer_find_average_overhead == 1 ) {
    93         return (int) total; 
     93        return (int) total;
    9494    } else if ( total < LEAST_VALID ) {
    95         return 0;       
     95        return 0;
    9696    }
    9797
  • c/src/lib/libcpu/arm/s3c2410/irq/irq.h

    rac7af4a r359e537  
    2424 * Include some preprocessor value also used by assember code
    2525 */
    26  
     26
    2727#include <rtems.h>
    2828#include <s3c2410.h>
     
    4141#define BSP_EINT8_23          5
    4242#define BSP_nBATT_FLT         7
    43 #define BSP_INT_TICK          8 
    44 #define BSP_INT_WDT           9 
    45 #define BSP_INT_TIMER0       10   
    46 #define BSP_INT_TIMER1       11   
    47 #define BSP_INT_TIMER2       12   
    48 #define BSP_INT_TIMER3       13   
    49 #define BSP_INT_TIMER4       14   
    50 #define BSP_INT_UART2        15   
    51 #define BSP_INT_LCD          16       
    52 #define BSP_INT_DMA0         17 
    53 #define BSP_INT_DMA1         18 
    54 #define BSP_INT_DMA2         19 
    55 #define BSP_INT_DMA3         20 
    56 #define BSP_INT_SDI          21 
    57 #define BSP_INT_SPI0         22 
    58 #define BSP_INT_UART1        23   
    59 #define BSP_INT_USBD         25 
    60 #define BSP_INT_USBH         26 
    61 #define BSP_INT_IIC          27 
    62 #define BSP_INT_UART0        28   
    63 #define BSP_INT_SPI1         29   
    64 #define BSP_INT_RTC          30 
    65 #define BSP_INT_ADC          31 
    66 #define BSP_MAX_INT          32 
     43#define BSP_INT_TICK          8
     44#define BSP_INT_WDT           9
     45#define BSP_INT_TIMER0       10
     46#define BSP_INT_TIMER1       11
     47#define BSP_INT_TIMER2       12
     48#define BSP_INT_TIMER3       13
     49#define BSP_INT_TIMER4       14
     50#define BSP_INT_UART2        15
     51#define BSP_INT_LCD          16
     52#define BSP_INT_DMA0         17
     53#define BSP_INT_DMA1         18
     54#define BSP_INT_DMA2         19
     55#define BSP_INT_DMA3         20
     56#define BSP_INT_SDI          21
     57#define BSP_INT_SPI0         22
     58#define BSP_INT_UART1        23
     59#define BSP_INT_USBD         25
     60#define BSP_INT_USBH         26
     61#define BSP_INT_IIC          27
     62#define BSP_INT_UART0        28
     63#define BSP_INT_SPI1         29
     64#define BSP_INT_RTC          30
     65#define BSP_INT_ADC          31
     66#define BSP_MAX_INT          32
    6767
    6868extern void *bsp_vector_table;
    6969#define VECTOR_TABLE &bsp_vector_table
    70  
     70
    7171/*
    7272 * Type definition for RTEMS managed interrupts
     
    100100     * RTEMS may well need such a function when restoring normal interrupt
    101101     * processing after a debug session.
    102      * 
    103      */
    104     rtems_irq_enable            on;     
     102     *
     103     */
     104    rtems_irq_enable            on;
    105105
    106106    /*
     
    177177 *      5) restore the C scratch registers...
    178178 *      6) restore initial execution flow
    179  * 
     179 *
    180180 */
    181181int BSP_install_rtems_irq_handler       (const rtems_irq_connect_data*);
  • c/src/lib/libcpu/arm/shared/arm920/mmu.c

    rac7af4a r359e537  
    109109        while (sects > 0) {
    110110            lvl1_base[vbase] = MMU_SET_LVL1_SECT(pbase << 20,
    111                                                  MMU_SECT_AP_ALL, 
    112                                                  0, 
    113                                                  c, 
     111                                                 MMU_SECT_AP_ALL,
     112                                                 0,
     113                                                 c,
    114114                                                 b);
    115115            pbase++;
     
    250250    mmu_set_ctrl(reg);
    251251}
    252    
     252
  • c/src/lib/libcpu/bfin/cache/cache.c

    rac7af4a r359e537  
    11/*  Blackfin Cache Support
    2  * 
     2 *
    33 *  Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
    44 *             written by Allan Hessenflow <allanh@kallisti.com>
     
    1010 *  $Id$
    1111 */
    12  
     12
    1313
    1414#include <rtems.h>
  • c/src/lib/libcpu/bfin/clock/clock.c

    rac7af4a r359e537  
    11/*  RTEMS Clock Tick Driver for Blackfin.  Uses Blackfin Core Timer.
    2  * 
     2 *
    33 *  Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
    44 *             written by Allan Hessenflow <allanh@kallisti.com>
     
    1010 *  $Id$
    1111 */
    12  
     12
    1313
    1414#include <rtems.h>
  • c/src/lib/libcpu/bfin/clock/rtc.c

    rac7af4a r359e537  
    1111 *  $Id$
    1212 */
    13  
     13
    1414
    1515#include <rtems.h>
     
    2222/* The following are inside RTEMS -- we are violating visibility!!!
    2323 * Perhaps an API could be defined to get days since 1 Jan.
    24  */ 
     24 */
    2525extern const uint16_t   _TOD_Days_to_date[2][13];
    2626
     
    4343  rtems_time_of_day time_buffer;
    4444  rtems_status_code status;
    45  
    46   status = rtems_clock_get( RTEMS_CLOCK_GET_TOD, &time_buffer ); 
     45
     46  status = rtems_clock_get( RTEMS_CLOCK_GET_TOD, &time_buffer );
    4747  if (status == RTEMS_SUCCESSFUL){
    4848    setRealTime(&time_buffer);
     
    5757{
    5858  rtems_time_of_day time_buffer;
    59  
    60   getRealTime(&time_buffer); 
    61   rtems_clock_set( &time_buffer ); 
     59
     60  getRealTime(&time_buffer);
     61  rtems_clock_set( &time_buffer );
    6262}
    6363
     
    7171  uint32_t days;
    7272  rtems_time_of_day tod_temp;
    73  
     73
    7474  tod_temp = *tod;
    75  
     75
    7676  days = (tod_temp.year - TOD_BASE_YEAR) * 365 + \
    7777          _TOD_Days_to_date[0][tod_temp.month] + tod_temp.day - 1;
     
    8080  else
    8181    days +=  Leap_years_until_now (tod_temp.year);
    82  
     82
    8383  *((uint32_t volatile *)RTC_STAT) = (days << RTC_STAT_DAYS_SHIFT)|
    8484                                     (tod_temp.hour << RTC_STAT_HOURS_SHIFT)|
     
    100100  rtems_time_of_day tod_temp = { 0, 0, 0 };
    101101  int n, Leap_year;
    102  
    103   rtc_reg = *((uint32_t volatile *)RTC_STAT); 
    104  
     102
     103  rtc_reg = *((uint32_t volatile *)RTC_STAT);
     104
    105105  days = (rtc_reg >> RTC_STAT_DAYS_SHIFT) + 1;
    106  
     106
    107107  /* finding year */
    108108  tod_temp.year = days/365 + TOD_BASE_YEAR;
    109109  if (days%365 >  Leap_years_until_now (tod_temp.year - 1)) {
    110110    days = (days%365) -  Leap_years_until_now (tod_temp.year - 1);
    111   } else { 
     111  } else {
    112112    tod_temp.year--;
    113113    days = (days%365) + 365 -  Leap_years_until_now (tod_temp.year - 1);
    114114  }
    115115
    116   /* finding month and day */ 
     116  /* finding month and day */
    117117  Leap_year = (((!(tod_temp.year%4)) && (tod_temp.year%100)) ||
    118118              (!(tod_temp.year%400)))?1:0;
  • c/src/lib/libcpu/bfin/clock/tod.h

    rac7af4a r359e537  
    11/*  tod.h
    2  * 
     2 *
    33 *  Real Time Clock definitions for eZKit533.
    44 *
     
    1212 *
    1313 *  $Id$
    14  */ 
     14 */
    1515
    1616
  • c/src/lib/libcpu/bfin/include/sicRegs.h

    rac7af4a r359e537  
    1818#define SIC_IMASK                (SIC_BASE_ADDRESS + 0x000c)
    1919#define SIC_IAR_BASE_ADDRESS     (SIC_BASE_ADDRESS + 0x0010)
    20 #define SIC_IAR_PITCH                                   0x04 
     20#define SIC_IAR_PITCH                                   0x04
    2121#define SIC_IAR0                 (SIC_BASE_ADDRESS + 0x0010)
    2222#if SIC_IAR_COUNT > 1
  • c/src/lib/libcpu/bfin/interrupt/interrupt.c

    rac7af4a r359e537  
    11/*  Support for Blackfin interrupt controller
    2  * 
     2 *
    33 *  Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
    44 *             written by Allan Hessenflow <allanh@kallisti.com>
     
    1010 *  $Id$
    1111 */
    12  
     12
    1313
    1414#include <rtems.h>
  • c/src/lib/libcpu/bfin/interrupt/interrupt.h

    rac7af4a r359e537  
    7474   out all enabled) */
    7575void bfin_interrupt_enable_global(int source, bool enable);
    76  
     76
    7777#ifdef __cplusplus
    7878}
  • c/src/lib/libcpu/bfin/mmu/mmu.c

    rac7af4a r359e537  
    11/*  Blackfin MMU Support
    2  * 
     2 *
    33 *  Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
    44 *             written by Allan Hessenflow <allanh@kallisti.com>
     
    1010 *  $Id$
    1111 */
    12  
     12
    1313
    1414#include <rtems.h>
  • c/src/lib/libcpu/bfin/serial/spi.c

    rac7af4a r359e537  
    22
    33/*  SPI driver for Blackfin
    4  * 
     4 *
    55 *  Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
    66 *             written by Allan Hessenflow <allanh@kallisti.com>
     
    1212 *  $Id$
    1313 */
    14  
     14
    1515
    1616#include <stdlib.h>
  • c/src/lib/libcpu/bfin/serial/spi.h

    rac7af4a r359e537  
    4141extern rtems_libi2c_bus_ops_t bfin_spi_libi2c_bus_ops;
    4242
    43  
     43
    4444void bfin_spi_isr(int source);
    4545
  • c/src/lib/libcpu/bfin/serial/twi.c

    rac7af4a r359e537  
    22
    33/*  TWI (I2C) driver for Blackfin
    4  * 
     4 *
    55 *  Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
    66 *             written by Allan Hessenflow <allanh@kallisti.com>
     
    1212 *  $Id$
    1313 */
    14  
     14
    1515
    1616#include <stdlib.h>
     
    5050  if (channel < 0 || channel >= N_BFIN_TWI)
    5151    return RTEMS_INVALID_NUMBER;
    52    
     52
    5353  base = config->base;
    54   twi[channel].base = base;   
     54  twi[channel].base = base;
    5555
    5656  result = rtems_semaphore_create(rtems_build_name('t','w','i','s'),
     
    7878  BFIN_REG16(base, TWI_CLKDIV_OFFSET) = config->fast ?
    7979                                        ((8 << TWI_CLKDIV_CLKHI_SHIFT) |
    80                                          (17 << TWI_CLKDIV_CLKLOW_SHIFT)) : 
     80                                         (17 << TWI_CLKDIV_CLKLOW_SHIFT)) :
    8181                                        ((33 << TWI_CLKDIV_CLKHI_SHIFT) |
    8282                                         (67 << TWI_CLKDIV_CLKLOW_SHIFT));
  • c/src/lib/libcpu/bfin/serial/uart.c

    rac7af4a r359e537  
    11/*  UART driver for Blackfin
    2  * 
     2 *
    33 *  Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA
    44 *             written by Allan Hessenflow <allanh@kallisti.com>
     
    1010 *  $Id$
    1111 */
    12  
     12
    1313
    1414#include <rtems.h>
     
    3535
    3636  base = uartsConfig->channels[minor].base_address;
    37  
     37
    3838  *(uint16_t volatile *) (base + UART_IER_OFFSET) = 0;
    3939
     
    6161  int c;
    6262  char *base;
    63  
    64   base = uartsConfig->channels[minor].base_address;
    65  
     63
     64  base = uartsConfig->channels[minor].base_address;
     65
    6666  /* check to see if driver is using interrupts so this call will be
    6767     harmless (though non-functional) in case some debug code tries to
    68      use it */ 
     68     use it */
    6969  if (!uartsConfig->channels[minor].use_interrupts &&
    7070      *((uint16_t volatile *) (base + UART_LSR_OFFSET)) & UART_LSR_DR)
     
    8888void bfin_uart_poll_write(int minor, char c) {
    8989  char *base;
    90  
     90
    9191  base = uartsConfig->channels[minor].base_address;
    9292
     
    159159static void enableInterrupts(int minor) {
    160160  char *base;
    161  
     161
    162162  base = uartsConfig->channels[minor].base_address;
    163163
  • c/src/lib/libcpu/bfin/serial/uart.h

    rac7af4a r359e537  
    5151void bfin_uart_isr(int source);
    5252
    53  
     53
    5454#ifdef __cplusplus
    5555}
  • c/src/lib/libcpu/bfin/timer/timer.c

    rac7af4a r359e537  
    55 *  benchmark_timer_initialize() and benchmark_timer_read().  benchmark_timer_read() usually returns
    66 *  the number of microseconds since benchmark_timer_initialize() exitted.
    7  * 
     7 *
    88 *  Copyright (c) 2006 by Atos Automacao Industrial Ltda.
    99 *             written by Alain Schaefer <alain.schaefer@easc.ch>
     
    1616 *  $Id$
    1717 */
    18  
     18
    1919
    2020#include <rtems.h>
     
    2727/*
    2828 * benchmark_timer_initialize
    29  * 
     29 *
    3030 * Blackfin processor has a counter for clock cycles.
    3131 */
     
    4141  asm ("BITSET(R2,1);");
    4242  asm ("SYSCFG = R2");
    43  
     43
    4444}
    4545
     
    6565  register uint32_t cycles asm ("R2");
    6666
    67   /* stop counter */ 
     67  /* stop counter */
    6868  asm("R2 = SYSCFG;");
    6969  asm("BITCLR(R2,1);");
     
    7575
    7676  /* converting to microseconds */
    77   total = clicks / (CCLK/1000000); 
     77  total = clicks / (CCLK/1000000);
    7878
    7979  if ( benchmark_timer_find_average_overhead == 1 )
  • c/src/lib/libcpu/m68k/shared/misc/m68kidle.c

    rac7af4a r359e537  
    2929 *  Output parameters:  NONE
    3030 */
    31  
     31
    3232void *_CPU_Thread_Idle_body( uintptr_t ignored )
    3333{
  • c/src/lib/libcpu/m68k/shared/misc/memProbe.c

    rac7af4a r359e537  
    1 /* 
     1/*
    22 * Address Probing for M68k/ColdFire
    33 */
  • c/src/lib/libcpu/mips/au1x00/include/au1x00.h

    rac7af4a r359e537  
    44 * Copyright (c) 2005 by Cogent Computer Systems
    55 * Written by Jay Monkman <jtm@lopingdog.com>
    6  *     
     6 *
    77 *  The license and distribution terms for this file may be
    88 *  found in the file LICENSE in this distribution or at
     
    190190
    191191/*
    192  * SDCS0 - 
    193  * SDCS1 - 
    194  * SDCS2 - 
     192 * SDCS0 -
     193 * SDCS1 -
     194 * SDCS2 -
    195195 */
    196196#define MEM_SDMODE0             0x00552229
     
    198198#define MEM_SDMODE2             0x00552229
    199199
    200 #define MEM_SDADDR0             0x001003F8 
     200#define MEM_SDADDR0             0x001003F8
    201201#define MEM_SDADDR1             0x001023F8
    202202#define MEM_SDADDR2             0x001043F8
     
    246246
    247247
    248 #define AU1X00_SYS_TOYTRIM(x)    (*(volatile uint32_t*)(x + 0x00))   
     248#define AU1X00_SYS_TOYTRIM(x)    (*(volatile uint32_t*)(x + 0x00))
    249249#define AU1X00_SYS_TOYWRITE(x)   (*(volatile uint32_t*)(x + 0x04))
    250250#define AU1X00_SYS_TOYMATCH0(x)  (*(volatile uint32_t*)(x + 0x08))
     
    316316    uint32_t _rsv1;
    317317} au1x00_macdma_rx_t;
    318                                            
     318
    319319
    320320typedef struct {
     
    324324    uint32_t _rsv0;
    325325} au1x00_macdma_tx_t;
    326                                            
     326
    327327#define AU1X00_MAC_CTRL_RA                (bit(31))
    328328#define AU1X00_MAC_CTRL_EM                (bit(30))
     
    393393
    394394#define AU1X00_MAC_DMA_TXSTAT_PR          (bit(31))
    395 #define AU1X00_MAC_DMA_TXSTAT_CC_MASK     (0xf << 10)     
     395#define AU1X00_MAC_DMA_TXSTAT_CC_MASK     (0xf << 10)
    396396#define AU1X00_MAC_DMA_TXSTAT_LO          (bit(9))
    397397#define AU1X00_MAC_DMA_TXSTAT_DF          (bit(8))
     
    426426} au1x00_uart_t;
    427427
    428 extern au1x00_uart_t *uart0;   
    429 extern au1x00_uart_t *uart3;   
     428extern au1x00_uart_t *uart0;
     429extern au1x00_uart_t *uart3;
    430430
    431431/*
  • c/src/lib/libcpu/mips/au1x00/vectorisrs/maxvectors.c

    rac7af4a r359e537  
    1 /* 
     1/*
    22 *  This file contains the maximum number of vectors.  This can not
    3  *  be determined without knowing the RTEMS CPU model. 
     3 *  be determined without knowing the RTEMS CPU model.
    44 *
    55 *  COPYRIGHT (c) 1989-2000.
  • c/src/lib/libcpu/mips/au1x00/vectorisrs/vectorisrs.c

    rac7af4a r359e537  
    11/*
    2  *  Au1x00 Interrupt Vectoring 
     2 *  Au1x00 Interrupt Vectoring
    33 *
    44 * Copyright (c) 2005 by Cogent Computer Systems
    55 * Written by Jay Monkman <jtm@lopingdog.com>
    6  *     
     6 *
    77 *  The license and distribution terms for this file may be
    88 *  found in the file LICENSE in this distribution or at
     
    4545      unsigned long zero = 0;
    4646      /*
    47        * I don't see a good way to disable the compare 
     47       * I don't see a good way to disable the compare
    4848       * interrupt, so let's just ignore it.
    4949       */
     
    5757      CALL_ISR( AU1X00_IRQ_PERF, frame );
    5858  }
    59  
     59
    6060  /* Interrupt controller 0 */
    6161  if ( cause & 0x0c ) {
    6262      call_vectored_isr(frame, cause, (void *)AU1X00_IC0_ADDR);
    6363  }
    64  
     64
    6565  /* Interrupt controller 1 */
    6666  if ( cause & 0x30 ) {
    6767      call_vectored_isr(frame, cause, (void *)AU1X00_IC1_ADDR);
    6868  }
    69  
     69
    7070  /* SW[0] */
    7171  if ( cause & 0x01 )
    7272      CALL_ISR( AU1X00_IRQ_SW0, frame );
    73  
     73
    7474  /* SW[1] */
    75   if ( cause & 0x02 ) 
     75  if ( cause & 0x02 )
    7676      CALL_ISR( AU1X00_IRQ_SW1, frame );
    7777}
     
    9191
    9292static void call_vectored_isr(
    93     CPU_Interrupt_frame *frame, 
    94     uint32_t cause, 
     93    CPU_Interrupt_frame *frame,
     94    uint32_t cause,
    9595    void *ctrlr
    9696    )
  • c/src/lib/libcpu/mips/clock/ckinit.c

    rac7af4a r359e537  
    8585 * These are set by clock driver during its init
    8686 */
    87  
     87
    8888rtems_device_major_number rtems_clock_major = ~0;
    8989rtems_device_minor_number rtems_clock_minor;
     
    161161   */
    162162
    163   mips_timer_rate = rtems_configuration_get_microseconds_per_tick() * 
     163  mips_timer_rate = rtems_configuration_get_microseconds_per_tick() *
    164164     bsp_clicks_per_microsecond;
    165165  mips_set_timer( mips_timer_rate );
     
    196196{
    197197  Install_clock( Clock_isr );
    198  
     198
    199199  /*
    200200   * make major/minor avail to others such as shared memory driver
    201201   */
    202  
     202
    203203  rtems_clock_major = major;
    204204  rtems_clock_minor = minor;
    205  
     205
    206206  return RTEMS_SUCCESSFUL;
    207207}
  • c/src/lib/libcpu/mips/clock/clock.S

    rac7af4a r359e537  
    1 /*  clock.s 
     1/*  clock.s
    22 *
    33 *  This file contains the assembly code for the IDT 4650 clock driver.
  • c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.c

    rac7af4a r359e537  
    173173  cmdSave = MG5UART_GETREG( pMG5UART, MG5UART_COMMAND_REGISTER );
    174174
    175   MG5UART_SETREG( pMG5UART, 
    176                   MG5UART_COMMAND_REGISTER, 
     175  MG5UART_SETREG( pMG5UART,
     176                  MG5UART_COMMAND_REGISTER,
    177177                  (cmdSave & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift)) | (cmd << shift) );
    178178
     
    306306  MG5UART_SETREG( pMG5UART_port, MG5UART_BAUD_RATE, baudcmd );
    307307
    308   MG5UART_SETREG( pMG5UART, 
    309                   MG5UART_COMMAND_REGISTER, 
     308  MG5UART_SETREG( pMG5UART,
     309                  MG5UART_COMMAND_REGISTER,
    310310                  cmd = (cmdSave & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift)) | (cmd << shift) );
    311311
     
    353353  cmdSave = MG5UART_GETREG( pMG5UART, MG5UART_COMMAND_REGISTER );
    354354
    355   MG5UART_SETREG( pMG5UART, 
    356                   MG5UART_COMMAND_REGISTER, 
     355  MG5UART_SETREG( pMG5UART,
     356                  MG5UART_COMMAND_REGISTER,
    357357                  (cmdSave & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift)) | (cmd << shift) );
    358358  rtems_interrupt_enable(Irql);
     
    394394  timeout = 2000;
    395395
    396   while( --timeout ) 
     396  while( --timeout )
    397397  {
    398398    status = MG5UART_GETREG(pMG5UART, MG5UART_STATUS_REGISTER) >> shift;
     
    412412
    413413#if 0
    414      if(_System_state_Is_up(_System_state_Get())) 
     414     if(_System_state_Is_up(_System_state_Get()))
    415415     {
    416416       rtems_task_wake_after(RTEMS_YIELD_PROCESSOR);
     
    474474
    475475MG5UART_STATIC void mg5uart_process_isr_rx_error(
    476    int  minor, 
    477    uint32_t   mask 
     476   int  minor,
     477   uint32_t   mask
    478478)
    479479{
     
    525525   uint32_t        pMG5UART;
    526526   int             shift;
    527    
     527
    528528   pMG5UART      = Console_Port_Tbl[minor].ulCtrlPort1;
    529529
     
    534534   else
    535535      shift = MONGOOSEV_UART1_IRQ_SHIFT;
    536      
     536
    537537   MG5UART_SETREG(
    538538      pMG5UART,
     
    550550    *  by writing data to the uart, so just disable the tx interrupt sources.
    551551    */
    552  
     552
    553553   Console_Port_Data[minor].bActive = FALSE;
    554554
     
    660660  MG5UART_SETREG(pMG5UART_port, MG5UART_TX_BUFFER, *buf);
    661661
    662   if( Console_Port_Data[minor].bActive == FALSE ) 
     662  if( Console_Port_Data[minor].bActive == FALSE )
    663663  {
    664664     Console_Port_Data[minor].bActive = TRUE;
     
    691691   * poll each byte in the string out of the port.
    692692   */
    693   while (nwrite < len) 
     693  while (nwrite < len)
    694694  {
    695695    mg5uart_write_polled(minor, *buf++);
     
    735735  }
    736736
    737   if ( status & MONGOOSEV_UART_RX_READY ) 
     737  if ( status & MONGOOSEV_UART_RX_READY )
    738738  {
    739739     return (int) MG5UART_GETREG(pMG5UART_port, MG5UART_RX_BUFFER);
    740   } 
    741   else 
     740  }
     741  else
    742742  {
    743743     return -1;
  • c/src/lib/libcpu/mips/mongoosev/duart/mg5uart_reg.c

    rac7af4a r359e537  
    2121#define _MG5UART_MULTIPLIER 1
    2222#define _MG5UART_NAME(_X) _X
    23 #define _MG5UART_TYPE uint32_t 
     23#define _MG5UART_TYPE uint32_t
    2424#endif
    2525
     
    2727  (_MG5UART_TYPE *)((_base) + ((_reg) * _MG5UART_MULTIPLIER ))
    2828
    29 /* 
     29/*
    3030 *  MG5UART Get Register Routine
    3131 */
  • c/src/lib/libcpu/mips/mongoosev/include/mongoose-v.h

    rac7af4a r359e537  
    123123#define MONGOOSEV_UART_ALL_STATUS_BITS             0x001F
    124124
    125 /* 
    126  *  The Peripheral Interrupt Status, Cause, and Mask registers have the 
    127  *  same bit assignments although some revisions of the document have 
    128  *  the Cause and Status registers incorrect. 
     125/*
     126 *  The Peripheral Interrupt Status, Cause, and Mask registers have the
     127 *  same bit assignments although some revisions of the document have
     128 *  the Cause and Status registers incorrect.
    129129 */
    130130
     
    194194*/
    195195#define MONGOOSEV_COMMAND_ENABLE_EDAC   MONGOOSEV_EDAC_SERR_BIT
    196 #define MONGOOSEV_COMMAND_OVERRIDE_EDAC MONGOOSEV_EDAC_MERR_BIT         
     196#define MONGOOSEV_COMMAND_OVERRIDE_EDAC MONGOOSEV_EDAC_MERR_BIT
    197197
    198198
  • c/src/lib/libcpu/mips/mongoosev/vectorisrs/maxvectors.c

    rac7af4a r359e537  
    1 /* 
     1/*
    22 *  This file contains the maximum number of vectors.  This can not
    3  *  be determined without knowing the RTEMS CPU model. 
     3 *  be determined without knowing the RTEMS CPU model.
    44 *
    55 *  COPYRIGHT (c) 1989-2000.
     
    1818
    1919/*
    20  *  The Synova Mongoose-V attached one of the eight interrupt bits 
     20 *  The Synova Mongoose-V attached one of the eight interrupt bits
    2121 *  to a Peripheral Function Interrupt Cause Register on-CPU.
    22  *  This results in: 2 software interrupts, 5 interrupts 
     22 *  This results in: 2 software interrupts, 5 interrupts
    2323 *  through the IP bits, and 32 more from the PFICR.  Some of
    2424 *  these are reserved but for simplicity in processing, we
  • c/src/lib/libcpu/mips/mongoosev/vectorisrs/vectorisrs.c

    rac7af4a r359e537  
    9292
    9393
    94 static uint32_t   READ_CAUSE(void) 
     94static uint32_t   READ_CAUSE(void)
    9595{
    9696   mips_get_cause( _ivcause );
     
    141141      {
    142142         CALL_ISR( MONGOOSEV_IRQ_SOFTWARE_1, frame );
    143       } 
     143      }
    144144      if ( cshifted & 0x02 )       /* SW[1] */
    145145      {
     
    157157      if( (cshifted = READ_CAUSE()) & 0x3 ) goto intvect;
    158158   }
    159    
     159
    160160   if ( cshifted & 0x08 )       /* IP[1] ==> INT1 == TIMER2*/
    161161   {
     
    165165      if( (cshifted = READ_CAUSE()) & 0x7 ) goto intvect;
    166166   }
    167    
     167
    168168   if ( cshifted & 0x10 )       /* IP[2] ==> INT2 */
    169169   {
     
    173173      if( (cshifted = READ_CAUSE()) & 0xf ) goto intvect;
    174174   }
    175    
     175
    176176   if ( cshifted & 0x20 )       /* IP[3] ==> INT3 == FPU interrupt */
    177177   {
     
    181181      if( (cshifted = READ_CAUSE()) & 0x1f ) goto intvect;
    182182   }
    183    
     183
    184184   if ( cshifted & 0x40 )       /* IP[4] ==> INT4, external interrupt */
    185185   {
     
    199199
    200200/*
    201       for (bit=0, pf_mask = 1;    bit < 32;     bit++, pf_mask <<= 1 ) 
     201      for (bit=0, pf_mask = 1;    bit < 32;     bit++, pf_mask <<= 1 )
    202202      {
    203203         if ( pf_icr & pf_mask )
     
    209209            if( (cshifted = READ_CAUSE()) & 0xff ) break;
    210210         }
    211       } 
     211      }
    212212*/
    213213
     
    218218       * to serve as a interrupt cause test mask.
    219219       */
    220       for( bit=0, pf_mask = 0xff;    (bit < 32 && pf_icr);     (bit+=8, pf_mask <<= 8) ) 
     220      for( bit=0, pf_mask = 0xff;    (bit < 32 && pf_icr);     (bit+=8, pf_mask <<= 8) )
    221221      {
    222222         if ( pf_icr & pf_mask )
  • c/src/lib/libcpu/mips/r46xx/vectorisrs/maxvectors.c

    rac7af4a r359e537  
    1 /* 
     1/*
    22 *  This file contains the maximum number of vectors.  This can not
    3  *  be determined without knowing the RTEMS CPU model. 
     3 *  be determined without knowing the RTEMS CPU model.
    44 *
    55 *  COPYRIGHT (c) 1989-2000.
  • c/src/lib/libcpu/mips/rm52xx/vectorisrs/maxvectors.c

    rac7af4a r359e537  
    1 /* 
     1/*
    22 *  This file contains the maximum number of vectors.  This can not
    3  *  be determined without knowing the RTEMS CPU model. 
     3 *  be determined without knowing the RTEMS CPU model.
    44 *
    55 *  COPYRIGHT (c) 1989-2000.
  • c/src/lib/libcpu/mips/rm52xx/vectorisrs/vectorisrs.c

    rac7af4a r359e537  
    11/*
    2  *  RM5231 Interrupt Vectoring 
     2 *  RM5231 Interrupt Vectoring
    33 *
    44 *  vectorisrs.c,v 1.6 2004/06/23 18:16:36
  • c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S

    rac7af4a r359e537  
    3333        nop
    3434ENDFRAME(exc_dbg_code)
    35        
     35
    3636/* XXX this is dependent on IDT/SIM and needs to be addressed */
    3737FRAME(exc_utlb_code,sp,0,ra)
     
    4141ENDFRAME(exc_utlb_code)
    4242
    43 /* 
     43/*
    4444 * MIPS ISA Level 32
    4545 * XXX Again, reliance on SIM. Not good.??????????
     
    7070        nop
    7171ENDFRAME(exc_norm_code)
    72        
    73 /* 
     72
     73/*
    7474 * MIPS ISA Level 3
    7575 * XXX Again, reliance on SIM. Not good.
  • c/src/lib/libcpu/mips/tx39/vectorisrs/maxvectors.c

    rac7af4a r359e537  
    1 /* 
     1/*
    22 *  This file contains the maximum number of vectors.  This can not
    3  *  be determined without knowing the RTEMS CPU model. 
     3 *  be determined without knowing the RTEMS CPU model.
    44 *
    55 *  COPYRIGHT (c) 1989-2000.
  • c/src/lib/libcpu/mips/tx39/vectorisrs/vectorisrs.c

    rac7af4a r359e537  
    11/*
    2  *  TX3904 Interrupt Vectoring 
     2 *  TX3904 Interrupt Vectoring
    33 *
    44 *  $Id$
     
    3939    CALL_ISR( MIPS_INTERRUPT_BASE + v, frame );
    4040  }
    41    
     41
    4242  if ( cause & 0x02 )       /* SW[0] */
    4343    CALL_ISR( TX3904_IRQ_SOFTWARE_1, frame );
  • c/src/lib/libcpu/mips/tx49/include/tx4925.h

    rac7af4a r359e537  
    2727
    2828/* Pin Configuration register bits */
    29 #define SELCHI  0x00100000             
     29#define SELCHI  0x00100000
    3030#define SELTMR0 0x00000200
    3131
     
    6565
    6666
    67 /* 
     67/*
    6868 *      Interrupt Controller Registers
    6969 */
  • c/src/lib/libcpu/mips/tx49/include/tx4938.h

    rac7af4a r359e537  
    4242
    4343/* Pin Configuration register bits */
    44 #define SELCHI  0x00100000             
     44#define SELCHI  0x00100000
    4545#define SELTMR0 0x00000200
    4646
     
    8080
    8181
    82 /* 
     82/*
    8383 *      Interrupt Controller Registers
    8484 */
  • c/src/lib/libcpu/mips/tx49/vectorisrs/maxvectors.c

    rac7af4a r359e537  
    1 /* 
     1/*
    22 *  This file contains the maximum number of vectors.  This can not
    3  *  be determined without knowing the RTEMS CPU model. 
     3 *  be determined without knowing the RTEMS CPU model.
    44 *
    55 *  COPYRIGHT (c) 1989-2000.
  • c/src/lib/libcpu/mips/tx49/vectorisrs/vectorisrs.c

    rac7af4a r359e537  
    11/*
    2  *  TX4925 Interrupt Vectoring 
     2 *  TX4925 Interrupt Vectoring
    33 *
    44 *  vectorisrs.c,v 1.6 2004/06/23 18:16:36
     
    3636    CALL_ISR( MIPS_INTERRUPT_BASE + v, frame );
    3737  }
    38    
     38
    3939  if ( pending & 0x01 )       /* IP[0] */
    4040    CALL_ISR( TX4925_IRQ_SOFTWARE_1, frame );
     
    5454  printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n",
    5555      vector, cause, sr );
    56  
     56
    5757  while(1);     /* Lock it up */
    58  
     58
    5959  rtems_fatal_error_occurred(1);
    6060}
  • c/src/lib/libcpu/powerpc/e500/mmu/e500_mmu.h

    rac7af4a r359e537  
    88 */
    99
    10 /* 
     10/*
    1111 * Authorship
    1212 * ----------
     
    1414 *     Till Straumann <strauman@slac.stanford.edu>, 2005-2007,
    1515 *         Stanford Linear Accelerator Center, Stanford University.
    16  * 
     16 *
    1717 * Acknowledgement of sponsorship
    1818 * ------------------------------
     
    2020 *     the Stanford Linear Accelerator Center, Stanford University,
    2121 *         under Contract DE-AC03-76SFO0515 with the Department of Energy.
    22  * 
     22 *
    2323 * Government disclaimer of liability
    2424 * ----------------------------------
     
    2929 * disclosed, or represents that its use would not infringe privately owned
    3030 * rights.
    31  * 
     31 *
    3232 * Stanford disclaimer of liability
    3333 * --------------------------------
    3434 * Stanford University makes no representations or warranties, express or
    3535 * implied, nor assumes any liability for the use of this software.
    36  * 
     36 *
    3737 * Stanford disclaimer of copyright
    3838 * --------------------------------
    3939 * Stanford University, owner of the copyright, hereby disclaims its
    4040 * copyright and all other rights in this software.  Hence, anyone may
    41  * freely use it for any purpose without restriction. 
    42  * 
     41 * freely use it for any purpose without restriction.
     42 *
    4343 * Maintenance of notices
    4444 * ----------------------
     
    4949 * software made or distributed by the recipient that contains a copy or
    5050 * derivative of this software.
    51  * 
     51 *
    5252 * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03
    53  */ 
     53 */
    5454
    5555#include <rtems.h>
     
    9999rtems_e500_dmptlbc(FILE *f);
    100100
    101 /* 
     101/*
    102102 * Read a TLB entry from the hardware; if it is a TLB1 entry
    103103 * then the current settings are stored in the
  • c/src/lib/libcpu/powerpc/e500/mmu/mmu.c

    rac7af4a r359e537  
    1616 *        are only two entries per 'way'.
    1717 *
    18  *        Since this is a real-time OS we want to stay away from 
     18 *        Since this is a real-time OS we want to stay away from
    1919 *        software TLB replacement.
    2020 */
    2121
    22 /* 
     22/*
    2323 * Authorship
    2424 * ----------
     
    2626 *     Till Straumann <strauman@slac.stanford.edu>, 2005-2007,
    2727 *         Stanford Linear Accelerator Center, Stanford University.
    28  * 
     28 *
    2929 * Acknowledgement of sponsorship
    3030 * ------------------------------
     
    3232 *     the Stanford Linear Accelerator Center, Stanford University,
    3333 *         under Contract DE-AC03-76SFO0515 with the Department of Energy.
    34  * 
     34 *
    3535 * Government disclaimer of liability
    3636 * ----------------------------------
     
    4141 * disclosed, or represents that its use would not infringe privately owned
    4242 * rights.
    43  * 
     43 *
    4444 * Stanford disclaimer of liability
    4545 * --------------------------------
    4646 * Stanford University makes no representations or warranties, express or
    4747 * implied, nor assumes any liability for the use of this software.
    48  * 
     48 *
    4949 * Stanford disclaimer of copyright
    5050 * --------------------------------
    5151 * Stanford University, owner of the copyright, hereby disclaims its
    5252 * copyright and all other rights in this software.  Hence, anyone may
    53  * freely use it for any purpose without restriction. 
    54  * 
     53 * freely use it for any purpose without restriction.
     54 *
    5555 * Maintenance of notices
    5656 * ----------------------
     
    6161 * software made or distributed by the recipient that contains a copy or
    6262 * derivative of this software.
    63  * 
     63 *
    6464 * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03
    65  */ 
     65 */
    6666
    6767/* 8450 MSR definitions; note that there are *substantial* differences
     
    231231        }
    232232        for ( i=0; i<16; i++ ) {
    233                 if ( !rtems_e500_tlb_va_cache[i].att.v ) 
    234                         continue;       
     233                if ( !rtems_e500_tlb_va_cache[i].att.v )
     234                        continue;
    235235                myprintf(f,"#%2i: TID 0x%03x, TS %i, ea 0x%08x .. 0x%08x\n",
    236236                        i,
     
    260260}
    261261
    262 /* 
     262/*
    263263 * Read a TLB entry from the hardware; if it is a TLB1 entry
    264264 * then the current settings are stored in the
     
    501501        mas1 |= MAS1_IPROT | MAS1_TID(tid);
    502502
    503         if ( sz >= 0 ) 
     503        if ( sz >= 0 )
    504504                mas1 |= MAS1_V | MAS1_TSIZE(sz);
    505505
     
    669669                if ( (key & ~E500_SELTLB_1) > 15 ) {
    670670                        myprintf(stderr,"Invalid TLB index; TLB1 index must be < 16\n");
    671                         return -1;     
     671                        return -1;
    672672                }
    673673        } else if ( key > 255 ) {
    674674                        myprintf(stderr,"Invalid TLB index; TLB0 index must be < 256\n");
    675                         return -1;     
     675                        return -1;
    676676        }
    677677
  • c/src/lib/libcpu/powerpc/mpc55xx/esci/esci.c

    rac7af4a r359e537  
    191191
    192192        /* Connect TTY */
    193         e->tty = tty;   
     193        e->tty = tty;
    194194
    195195        /* Enable interrupts */
     
    381381        }
    382382        cr1.B.SBR = br;
    383                  
     383
    384384        /* Number of data bits */
    385385        if ((t->c_cflag & CSIZE) != CS8) {
     
    391391        cr1.B.PE = (t->c_cflag & PARENB) ? 1 : 0;
    392392        cr1.B.PT = (t->c_cflag & PARODD) ? 1 : 0;
    393        
     393
    394394        /* Stop bits */
    395395        if ( t->c_cflag & CSTOPB ) {
     
    485485{
    486486        rtems_status_code sc = RTEMS_SUCCESSFUL;
    487         int console_done = 0; 
    488         int termios_do_init = 1; 
     487        int console_done = 0;
     488        int termios_do_init = 1;
    489489        rtems_device_minor_number i = 0;
    490490        mpc55xx_esci_driver_entry *e = NULL;
    491        
     491
    492492        for (i = 0; i < MPC55XX_ESCI_NUMBER; ++i) {
    493493                e = &mpc55xx_esci_driver_table [i];
  • c/src/lib/libcpu/powerpc/mpc55xx/include/dspi.h

    rac7af4a r359e537  
    1919 */
    2020
    21 /** 
     21/**
    2222 * @defgroup mpc55xx_dspi Deserial Serial Peripheral Interface (DSPI)
    23  * 
     23 *
    2424 * @ingroup mpc55xx
    2525 */
  • c/src/lib/libcpu/powerpc/mpc55xx/include/esci.h

    rac7af4a r359e537  
    1919 */
    2020
    21 /** 
     21/**
    2222 * @defgroup mpc55xx_esci Enhanced Serial Communication Interface (eSCI).
    23  * 
     23 *
    2424 * @ingroup mpc55xx
    2525 */
  • c/src/lib/libcpu/powerpc/mpc55xx/include/mpc55xx.h

    rac7af4a r359e537  
    2323 */
    2424
    25 /** 
     25/**
    2626 * @defgroup mpc55xx_config Configuration files
    27  * 
     27 *
    2828 * @ingroup mpc55xx
    29  * 
     29 *
    3030 * Makefiles, configure scripts etc.
    3131 */
  • c/src/lib/libcpu/powerpc/mpc55xx/include/regs.h

    rac7af4a r359e537  
    28102810        .CDF = { .R = 0 },
    28112811        .DLAST_SGA = 0,
    2812         .BMF = { .R = 0 } 
     2812        .BMF = { .R = 0 }
    28132813    };
    28142814
  • c/src/lib/libcpu/powerpc/mpc55xx/irq/irq.c

    rac7af4a r359e537  
    4242                *priority = MPC55XX_INTC_INVALID_PRIORITY;
    4343                return RTEMS_INVALID_NUMBER;
    44         }             
     44        }
    4545}
    4646
     
    5959        } else {
    6060                return RTEMS_INVALID_NUMBER;
    61         }             
     61        }
    6262}
    6363
     
    7272        } else {
    7373                return RTEMS_INVALID_NUMBER;
    74         }             
     74        }
    7575}
    7676
     
    8585        } else {
    8686                return RTEMS_INVALID_NUMBER;
    87         }             
     87        }
    8888}
    8989
  • c/src/lib/libcpu/powerpc/mpc55xx/misc/copy.S

    rac7af4a r359e537  
    9696        addi r8, r8, 32
    9797        bdnz zero_big_data
    98        
     98
    9999        /* Return */
    100100        blr
     
    146146        addi r8, r8, 128
    147147        bdnz zero_big_line
    148        
     148
    149149        /* Return */
    150150        blr
  • c/src/lib/libcpu/powerpc/mpc5xx/clock/clock.c

    rac7af4a r359e537  
    5959 * These are set by clock driver during its init
    6060 */
    61  
     61
    6262rtems_device_major_number rtems_clock_major = ~0;
    6363rtems_device_minor_number rtems_clock_minor;
    64  
     64
    6565/*
    6666 *  ISR Handler
     
    7171  usiu.piscr |= USIU_PISCR_PS;                  /* acknowledge interrupt */
    7272  usiu.piscrk = 0;
    73  
     73
    7474  Clock_driver_ticks++;
    7575  rtems_clock_tick();
     
    8282  extern uint32_t bsp_clicks_per_usec;
    8383
    84   /* calculate and set modulus */ 
     84  /* calculate and set modulus */
    8585  pit_value = (rtems_configuration_get_microseconds_per_tick() *
    8686               bsp_clicks_per_usec) - 1 ;
    87  
     87
    8888  if (pit_value > 0xffff) {           /* pit is only 16 bits long */
    8989    rtems_fatal_error_occurred(-1);
     
    115115  /* disable PIT and PIT interrupts */
    116116  usiu.piscrk = USIU_UNLOCK_KEY;
    117   usiu.piscr &= ~(USIU_PISCR_PTE | USIU_PISCR_PIE); 
     117  usiu.piscr &= ~(USIU_PISCR_PTE | USIU_PISCR_PIE);
    118118  usiu.piscrk = 0;
    119119}
     
    121121int clockIsOn(void* unused)
    122122{
    123   if (usiu.piscr & USIU_PISCR_PIE) 
     123  if (usiu.piscr & USIU_PISCR_PIE)
    124124    return 1;
    125125  return 0;
     
    158158{
    159159  Install_clock( Clock_isr );
    160  
     160
    161161  /*
    162162   * make major/minor avail to others such as shared memory driver
    163163   */
    164  
     164
    165165  rtems_clock_major = major;
    166166  rtems_clock_minor = minor;
    167  
     167
    168168  return RTEMS_SUCCESSFUL;
    169169}
  • c/src/lib/libcpu/powerpc/mpc5xx/console-generic/console-generic.c

    rac7af4a r359e537  
    1515 *  Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
    1616 *
    17  *  Derived from 
     17 *  Derived from
    1818 *    c/src/lib/libcpu/powerpc/mpc8xx/console_generic/console_generic.c:
    1919 *  Author: Jay Monkman (jmonkman@frasca.com)
     
    8585};
    8686
    87  
     87
    8888/*
    8989 * Termios callback functions
     
    9292int
    9393m5xx_uart_firstOpen(
    94   int major, 
    95   int minor, 
     94  int major,
     95  int minor,
    9696  void *arg
    9797)
     
    110110int
    111111m5xx_uart_lastClose(
    112   int major, 
     112  int major,
    113113  int minor,
    114114  void* arg
     
    130130  volatile m5xxSCIRegisters_t *regs = sci_descs[minor].regs;
    131131  int c = -1;
    132  
     132
    133133  if ( regs ) {
    134134    while ( (regs->scsr & QSMCM_SCI_RDRF) == 0 )
     
    140140}
    141141
    142 int 
     142int
    143143m5xx_uart_write(
    144144  int minor,
     
    171171}
    172172
    173 int 
     173int
    174174m5xx_uart_setAttributes(
    175175  int minor,
     
    180180  uint16_t sccr1 = sci_descs[minor].regs->sccr1;
    181181  int baud;
    182  
     182
    183183  /*
    184184   * Check that port number is valid
    185185   */
    186   if ( (minor < SCI1_MINOR) || (minor > SCI2_MINOR) ) 
     186  if ( (minor < SCI1_MINOR) || (minor > SCI2_MINOR) )
    187187    return RTEMS_INVALID_NUMBER;
    188188
     
    213213    extern uint32_t bsp_clock_speed;
    214214    sccr0 &= ~QSMCM_SCI_BAUD(-1);
    215     sccr0 |= 
     215    sccr0 |=
    216216      QSMCM_SCI_BAUD((bsp_clock_speed + (16 * baud)) / (32 * baud));
    217217  }
    218      
     218
    219219  /* Number of data bits -- not available with MPC5xx SCI */
    220220  switch ( t->c_cflag & CSIZE ) {
     
    237237  else
    238238    sccr1 &= ~QSMCM_SCI_PE;
    239  
     239
    240240  if ( t->c_cflag & PARODD )
    241241    sccr1 |= QSMCM_SCI_PT;
     
    249249  else
    250250    sccr1 &= ~QSMCM_SCI_RE;
    251    
     251
    252252  /* Write hardware registers */
    253253  sci_descs[minor].regs->sccr0 = sccr0;
    254254  sci_descs[minor].regs->sccr1 = sccr1;
    255  
     255
    256256  return RTEMS_SUCCESSFUL;
    257257}
    258258
    259259
    260 /* 
     260/*
    261261 * Interrupt handling.
    262262 */
     
    265265{
    266266  int minor;
    267  
     267
    268268  for ( minor = 0; minor < NUM_PORTS; minor++ ) {
    269269    sci_desc *desc = &sci_descs[minor];
    270270    int sccr1 = desc->regs->sccr1;
    271271    int scsr = desc->regs->scsr;
    272        
    273     /* 
     272
     273    /*
    274274     * Character received?
    275275     */
     
    307307   * Check that minor number is valid.
    308308   */
    309   if ( (minor < SCI1_MINOR) || (minor > SCI2_MINOR) ) 
     309  if ( (minor < SCI1_MINOR) || (minor > SCI2_MINOR) )
    310310    return;
    311311
     
    314314   */
    315315  m5xx_uart_setAttributes(minor, &default_termios);
    316    
     316
    317317  /*
    318318   * Connect interrupt if not yet done.
     
    326326    irq_data.off  = m5xx_sci_nop;       /* can't disable both channels here */
    327327    irq_data.isOn = m5xx_sci_isOn;
    328    
     328
    329329    if (!CPU_install_rtems_irq_handler (&irq_data)) {
    330330      printk("Unable to connect SCI Irq handler\n");
  • c/src/lib/libcpu/powerpc/mpc5xx/exceptions/raw_exception.c

    rac7af4a r359e537  
    6262        case ASM_NMEBREAK_VECTOR:
    6363          return 1;
    64         default: 
     64        default:
    6565          return 0;
    6666      }
     
    8686   * to get the previous handler before accepting to disconnect.
    8787   */
    88   if (exception_handler_table[except->exceptIndex] != 
     88  if (exception_handler_table[except->exceptIndex] !=
    8989      default_raw_except_entry.hdl.raw_hdl) {
    9090    return 0;
     
    9292
    9393  rtems_interrupt_disable(level);
    94  
     94
    9595  raw_except_table[except->exceptIndex] = *except;
    9696
     
    9898  if (except->on)
    9999        except->on(except);
    100  
     100
    101101  rtems_interrupt_enable(level);
    102102  return 1;
     
    108108    return 0;
    109109  }
    110    
     110
    111111  *except = raw_except_table[except->exceptIndex];
    112    
     112
    113113  return 1;
    114114}
     
    117117{
    118118  rtems_interrupt_level level;
    119  
     119
    120120  if (!mpc5xx_vector_is_valid(except->exceptIndex)){
    121121    return 0;
     
    136136  if (except->off)
    137137        except->off(except);
    138   exception_handler_table[except->exceptIndex] = 
     138  exception_handler_table[except->exceptIndex] =
    139139    default_raw_except_entry.hdl.raw_hdl;
    140  
     140
    141141  raw_except_table[except->exceptIndex] = default_raw_except_entry;
    142142  raw_except_table[except->exceptIndex].exceptIndex = except->exceptIndex;
    143143
    144144  rtems_interrupt_enable(level);
    145    
     145
    146146  return 1;
    147147}
     
    157157  unsigned              i;
    158158  rtems_interrupt_level level;
    159  
     159
    160160  /*
    161161   * store various accelerators
  • c/src/lib/libcpu/powerpc/mpc5xx/exceptions/raw_exception.h

    rac7af4a r359e537  
    6363
    6464/*
    65  * Type definition for raw exceptions. 
     65 * Type definition for raw exceptions.
    6666 */
    6767
     
    7474  rtems_exception_handler_t*    raw_hdl;
    7575}rtems_raw_except_hdl;
    76  
     76
    7777typedef void (*rtems_raw_except_enable)         (const struct __rtems_raw_except_connect_data__*);
    7878typedef void (*rtems_raw_except_disable)        (const struct __rtems_raw_except_connect_data__*);
     
    9494   * board specific hardware to manage exceptions and thus the
    9595   * "on" routine must enable the except at processor level only.
    96    * 
     96   *
    9797   */
    98     rtems_raw_except_enable     on;     
     98    rtems_raw_except_enable     on;
    9999  /*
    100100   * function for disabling raw exceptions. In order to be consistent
     
    103103   * board specific hardware to manage exceptions and thus the
    104104   * "on" routine must disable the except both at device and PIC level.
    105    * 
     105   *
    106106   */
    107107  rtems_raw_except_disable      off;
  • c/src/lib/libcpu/powerpc/mpc5xx/include/console.h

    rac7af4a r359e537  
    99 *  found in found in the file LICENSE in this distribution or at
    1010 *  http://www.rtems.com/license/LICENSE.
    11  * 
     11 *
    1212 *  $Id$
    1313 */
  • c/src/lib/libcpu/powerpc/mpc5xx/include/mpc5xx.h

    rac7af4a r359e537  
    4545 *      Corrections/additions:                                           *
    4646 *        Copyright (c) 1999, National Research Council of Canada        *
    47  * 
     47 *
    4848 *  MPC5xx port sponsored by Defence Research and Development Canada - Suffield
    4949 *  Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca)
     
    341341#define UIMB_UMCR_IRQMUX(x)     ((x)<<29)
    342342#define UIMB_UMCR_HSPEED        (1<<28)
    343  
     343
    344344/*
    345345 *************************************************************************
     
    347347 *************************************************************************
    348348 */
    349  
    350  
     349
     350
    351351#define QSMCM_ILDSCI(x)        ((x)<<8)    /* SCI interrupt level */
    352352
     
    418418  uint32_t      pdmcr;
    419419  uint8_t       _pad2[0x100-0x40];
    420  
     420
    421421  /*
    422422   * MEMC Block
     
    429429  uint16_t      mstat;
    430430  uint8_t       _pad9[0x200-0x17A];
    431  
     431
    432432  /*
    433433   * System integration timers
     
    451451  uint16_t      _pad_14_2;
    452452  uint8_t       _pad15[0x280-0x24c];
    453  
     453
    454454  /*
    455455   * Clocks and Reset
     
    463463  uint16_t      vsrmcr;
    464464  uint8_t       _pad16[0x300-0x292];
    465  
     465
    466466  /*
    467467   * System integration timers keys
     
    480480  uint32_t      pitck;
    481481  uint8_t       _pad19[0x380-0x348];
    482  
     482
    483483  /*
    484484   * Clocks and Reset Keys
     
    542542/*
    543543 * Queued Serial Multi-Channel Module (QSMCM)
    544  */ 
     544 */
    545545typedef struct m5xxQSMCMRegisters_ {
    546546  uint16_t      qsmcmmcr;
  • c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.c

    rac7af4a r359e537  
    1717 *  $Id$
    1818 */
    19  
     19
    2020#include <rtems.h>
    2121#include <rtems/score/apiext.h>
     
    2929 * suitable for programming into an I/O device's interrupt level field.
    3030 */
    31  
     31
    3232int CPU_irq_level_from_symbolic_name(const rtems_irq_number name)
    3333{
    3434  if (CPU_USIU_EXT_IRQ_0 <= name && name <= CPU_USIU_INT_IRQ_7)
    3535    return (name - CPU_USIU_EXT_IRQ_0) / 2;
    36    
     36
    3737  if (CPU_UIMB_IRQ_8 <= name && name <= CPU_UIMB_IRQ_31)
    3838    return 8 + (name - CPU_UIMB_IRQ_8);
     
    8585
    8686/*
    87  * Masks used to mask off the interrupts. For exmaple, for ILVL2, the 
    88  * mask is used to mask off interrupts ILVL2, IRQ3, ILVL3, ... IRQ7   
    89  * and ILVL7.                                                         
     87 * Masks used to mask off the interrupts. For exmaple, for ILVL2, the
     88 * mask is used to mask off interrupts ILVL2, IRQ3, ILVL3, ... IRQ7
     89 * and ILVL7.
    9090 *
    9191 */
     
    135135static int isValidInterrupt(int irq)
    136136{
    137   if ( (irq < CPU_MIN_OFFSET) || (irq > CPU_MAX_OFFSET) 
     137  if ( (irq < CPU_MIN_OFFSET) || (irq > CPU_MAX_OFFSET)
    138138        || (irq == CPU_UIMB_INTERRUPT) )
    139139    return 0;
     
    165165{
    166166  int usiu_irq_index;
    167  
     167
    168168  if (!is_usiu_irq(irqLine))
    169169    return 1;
     
    182182  if (!is_usiu_irq(irqLine))
    183183    return 1;
    184  
     184
    185185  usiu_irq_index = ((int) (irqLine) - CPU_USIU_IRQ_MIN_OFFSET);
    186186  ppc_cached_irq_mask &= ~(1 << (31-usiu_irq_index));
     
    208208{
    209209    rtems_interrupt_level       level;
    210  
     210
    211211    if (!isValidInterrupt(irq->name)) {
    212212      return 0;
     
    229229     */
    230230    rtems_hdl_tbl[irq->name] = *irq;
    231    
     231
    232232    if (is_uimb_irq(irq->name)) {
    233233      /*
     
    236236      CPU_irq_enable_at_uimb (irq->name);
    237237    }
    238    
     238
    239239    if (is_usiu_irq(irq->name)) {
    240240      /*
     
    255255        if (irq->on)
    256256        irq->on(irq);
    257    
     257
    258258    rtems_interrupt_enable(level);
    259259
     
    274274{
    275275    rtems_interrupt_level       level;
    276  
     276
    277277    if (!isValidInterrupt(irq->name)) {
    278278      return 0;
     
    312312       * disable exception at processor level
    313313       */
    314     }   
     314    }
    315315
    316316    /*
     
    425425    new_msr = msr | MSR_EE;
    426426    _CPU_MSR_SET(new_msr);
    427    
     427
    428428    rtems_hdl_tbl[CPU_DECREMENTER].hdl(rtems_hdl_tbl[CPU_DECREMENTER].handle);
    429429
     
    449449     */
    450450    usiu.sipend = (1 << (31 - irq));
    451    
     451
    452452    if (uimbIntr)  {
    453453      /*
    454454       * Look at the bits set in the UIMB interrupt-pending register.  The
    455        * highest-order set bit indicates the handler we will run. 
     455       * highest-order set bit indicates the handler we will run.
    456456       *
    457457       * Unfortunately, we can't easily mask individual UIMB interrupts
     
    460460       */
    461461      int uipend = imb.uimb.uipend << 8;
    462      
     462
    463463      if (uipend == 0) {        /* spurious interrupt?  use last vector */
    464         irq = CPU_UIMB_IRQ_MAX_OFFSET; 
     464        irq = CPU_UIMB_IRQ_MAX_OFFSET;
    465465      }
    466466      else {
     
    474474    new_msr = msr | MSR_EE;
    475475    _CPU_MSR_SET(new_msr);
    476    
     476
    477477    rtems_hdl_tbl[irq].hdl(rtems_hdl_tbl[irq].handle);
    478478