Changeset 356b8c7b in rtems


Ignore:
Timestamp:
Aug 19, 2013, 12:22:26 PM (6 years ago)
Author:
Pavel Pisa <pi@…>
Branches:
4.10
Children:
db99ce7c
Parents:
a791d39
git-author:
Pavel Pisa <pi@…> (08/19/13 12:22:26)
git-committer:
Sebastian Huber <sebastian.huber@…> (08/19/13 12:25:22)
Message:

bsp/csb336: Memory map update to support i.MX1 based PiMX1 as well.

CSB336 i.MX1/i.MXS memory map organization

  • SDRAM starts at address 0x08000000 but 2 MB are reserved for boot-block/loader (or other use) before RTEMS image origin/load address (that is kept from previous setup)
  • Caching of 30 MB of SDRAM used for RTEMS (start at 0x08200000) is changed to writeback mode which provides higher throughput.
  • The first 1 MB of RTEMS dedicated SDRAM is remapped to address 0 to provide area for ARM CPU exceptions table.
  • Internal registers and rest of the Flash (above 1 MB) are mapped one to one. Registers region is extended to 2 MB to cover eSRAM found on i.MX1 chip variant.
  • The first two megabytes of SDRAM unused by RTEMS are mapped with attributes to allow specific purposes.
  • the first MB (at address 0x08000000) is nocached to allow directly set some values read by booot-block after warm reset
  • the second MB (at address 0x08100000) is set for write-through caching. That allows to use memory for LCD frame-buffer without need to flush cache after each redraw.

Signed-off-by: Pavel Pisa <pi@…>

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/csb336/startup/memmap.c

    ra791d39 r356b8c7b  
    2020mmu_sect_map_t mem_map[] = {
    2121/*  <phys addr>  <virt addr> <size> <flags> */
    22     {0x08200000, 0x00000000,   1,    MMU_CACHE_NONE},     /* Mirror of SDRAM */
     22    {0x08200000, 0x00000000,   1,    MMU_CACHE_WBACK},    /* Mirror of SDRAM */
    2323    {0x00100000, 0x00100000,   1,    MMU_CACHE_NONE},     /* Bootstrap ROM */
    24     {0x00200000, 0x00200000,   1,    MMU_CACHE_NONE},     /* Internal Regs */
    25     {0x08000000, 0x08000000,  32,    MMU_CACHE_WTHROUGH}, /* SDRAM */
     24    {0x00200000, 0x00200000,   2,    MMU_CACHE_NONE},     /* Internal Regs + eSRAM */
     25
     26    {0x08000000, 0x08000000,   1,    MMU_CACHE_NONE},     /* SDRAM */
     27    {0x08100000, 0x08100000,   1,    MMU_CACHE_WTHROUGH}, /* SDRAM */
     28    {0x08200000, 0x08200000,  30,    MMU_CACHE_WBACK},    /* SDRAM */
     29
    2630    {0x10000000, 0x10000000,   8,    MMU_CACHE_NONE},     /* CS0 - Flash */
    2731    {0x12000000, 0x12000000,   1,    MMU_CACHE_NONE},     /* CS1 - enet */
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