Changeset 33d0666 in rtems


Ignore:
Timestamp:
Apr 15, 2014, 2:20:17 PM (5 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, master
Children:
2e06be4
Parents:
b80f920
git-author:
Sebastian Huber <sebastian.huber@…> (04/15/14 14:20:17)
git-committer:
Sebastian Huber <sebastian.huber@…> (04/16/14 07:07:33)
Message:

score: Critical fix for SMP

The _Scheduler_SMP_Allocate_processor() and _Thread_Dispatch() exchange
information without locks. Make sure we use the right load/store
ordering.

Location:
cpukit/score
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/include/rtems/score/cpustdatomic.h

    rb80f920 r33d0666  
    5555
    5656/**
    57  * @brief the enumeration Atomic_Memory_barrier specifies the detailed regular
    58  * memory synchronization operations used in the atomic operation API
    59  * definitions.
     57 * @brief Memory order according to ISO/IEC 9899:2011.
    6058 */
    6159typedef enum {
    62   /** no operation orders memory. */
    6360  ATOMIC_ORDER_RELAXED = memory_order_relaxed,
    64   /** a load operation performs an acquire operation on the affected memory
    65   * location. This flag guarantees that the effects of load operation are
    66   * completed before the effects of any later data accesses.
    67   */
    6861  ATOMIC_ORDER_ACQUIRE = memory_order_acquire,
    69   /** a store operation performs a release operation on the affected memory
    70   * location. This flag guarantee that all effects of all previous data
    71   * accesses are completed before the store operation takes place.
    72   */
    73   ATOMIC_ORDER_RELEASE = memory_order_release
     62  ATOMIC_ORDER_RELEASE = memory_order_release,
     63  ATOMIC_ORDER_SEQ_CST = memory_order_seq_cst
    7464} Atomic_Order;
    7565
  • cpukit/score/include/rtems/score/schedulersmpimpl.h

    rb80f920 r33d0666  
    9393    _Thread_Set_CPU( heir, cpu_of_victim );
    9494
     95    cpu_of_victim->heir = heir;
     96
    9597    /*
    96      * FIXME: Here we need atomic store operations with a relaxed memory order.
    97      * The _CPU_SMP_Send_interrupt() will ensure that the change can be
    98      * observed consistently.
     98     * It is critical that we first update the heir and then the dispatch
     99     * necessary so that _Thread_Dispatch() cannot miss an update.
    99100     */
    100     cpu_of_victim->heir = heir;
     101    _Atomic_Fence( ATOMIC_ORDER_RELEASE );
     102
    101103    cpu_of_victim->dispatch_necessary = true;
    102104
  • cpukit/score/src/threaddispatch.c

    rb80f920 r33d0666  
    9898  while ( per_cpu->dispatch_necessary ) {
    9999#endif
     100    per_cpu->dispatch_necessary = false;
     101
     102#if defined( RTEMS_SMP )
     103    /*
     104     * It is critical that we first update the dispatch necessary and then the
     105     * read the heir so that we don't miss an update by
     106     * _Scheduler_SMP_Allocate_processor().
     107     */
     108    _Atomic_Fence( ATOMIC_ORDER_SEQ_CST );
     109#endif
     110
    100111    heir = per_cpu->heir;
    101     per_cpu->dispatch_necessary = false;
    102112    per_cpu->executing = heir;
     113
    103114#if defined( RTEMS_SMP )
    104115    executing->is_executing = false;
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