Ignore:
Timestamp:
Jul 17, 2016, 4:21:48 PM (5 years ago)
Author:
Pavel Pisa <pisa@…>
Branches:
5, master
Children:
577e7fb
Parents:
a48c052
git-author:
Pavel Pisa <pisa@…> (07/17/16 16:21:48)
git-committer:
Pavel Pisa <pisa@…> (07/20/16 14:46:04)
Message:

bsps/arm: do not disable MMU during translation table management operations.

Disabling MMU requires complex cache flushing and invalidation
operations. There is almost no way how to do that right
on SMP system without stopping all other CPUs. On the other hand,
there is documented sequence of operations which should be used
according to ARM manual and it guarantees even distribution
of maintenance operations to other cores for last generation
of Cortex-A cores with multiprocessor extension.

This change could require addition of appropriate entry
to arm_cp15_start_mmu_config_table for some BSPs to ensure
that MMU table stays accessible after MMU is enabled

{

.begin = (uint32_t) bsp_translation_table_base,
.end = (uint32_t) bsp_translation_table_base + 0x4000,
.flags = ARMV7_MMU_DATA_READ_WRITE_CACHED

}

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/arm/shared/include/arm-cp15.h

    ra48c052 r33381218  
    561561
    562562ARM_CP15_TEXT_SECTION static inline void
     563arm_cp15_tlb_invalidate_entry_all_asids(const void *mva)
     564{
     565  ARM_SWITCH_REGISTERS;
     566
     567  mva = ARM_CP15_TLB_PREPARE_MVA(mva);
     568
     569  __asm__ volatile (
     570    ARM_SWITCH_TO_ARM
     571    "mcr p15, 0, %[mva], c8, c7, 3\n"
     572    ARM_SWITCH_BACK
     573    : ARM_SWITCH_OUTPUT
     574    : [mva] "r" (mva)
     575  );
     576}
     577
     578ARM_CP15_TEXT_SECTION static inline void
    563579arm_cp15_tlb_instruction_invalidate(void)
    564580{
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