Changeset 33381218 in rtems for c/src/lib/libcpu/arm/shared/include/arm-cp15.h

Timestamp:

Jul 17, 2016, 4:21:48 PM (5 years ago)

Author:

Pavel Pisa <pisa@…>

Branches:

5, master

Children:

577e7fb

Parents:

a48c052

git-author:

Pavel Pisa <pisa@…> (07/17/16 16:21:48)

git-committer:

Pavel Pisa <pisa@…> (07/20/16 14:46:04)

Message:

bsps/arm: do not disable MMU during translation table management operations.

Disabling MMU requires complex cache flushing and invalidation
operations. There is almost no way how to do that right
on SMP system without stopping all other CPUs. On the other hand,
there is documented sequence of operations which should be used
according to ARM manual and it guarantees even distribution
of maintenance operations to other cores for last generation
of Cortex-A cores with multiprocessor extension.

This change could require addition of appropriate entry
to arm_cp15_start_mmu_config_table for some BSPs to ensure
that MMU table stays accessible after MMU is enabled

{

.begin = (uint32_t) bsp_translation_table_base,
.end = (uint32_t) bsp_translation_table_base + 0x4000,
.flags = ARMV7_MMU_DATA_READ_WRITE_CACHED

}

File:

• c/src/lib/libcpu/arm/shared/include/arm-cp15.h (modified) (1 diff)

c/src/lib/libcpu/arm/shared/include/arm-cp15.h

@@ -561 +561 @@
 
 ARM_CP15_TEXT_SECTION static inline void
+arm_cp15_tlb_invalidate_entry_all_asids(const void *mva)
+{
+  ARM_SWITCH_REGISTERS;
+
+  mva = ARM_CP15_TLB_PREPARE_MVA(mva);
+
+  __asm__ volatile (
+    ARM_SWITCH_TO_ARM
+    "mcr p15, 0, %[mva], c8, c7, 3\n"
+    ARM_SWITCH_BACK
+    : ARM_SWITCH_OUTPUT
+    : [mva] "r" (mva)
+  );
+}
+
+ARM_CP15_TEXT_SECTION static inline void
 arm_cp15_tlb_instruction_invalidate(void)
 {